MC44605_技术文档

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The MC44605 is a high performance current mode controller that is

specifically designed for off–line converters. This circuit has several

distinguishing features that make it particularly suitable for

multisynchronized monitor applications.

The MC44605 synchronization arrangement enables operation from

16 kHz up to 130 kHz. This product was optimized to operate with

universal mains voltage, i.e., from 80 V to 280 V, and its high current

totem pole output makes it ideally suited for driving a power MOSFET.

The MC44605 protections enable a well–controlled and safe power

management. Four major faults while detected, activate the analogic

counter of a disabling block designed to perform a latched circuit

output inhibition.

MARKING

DIAGRAM

16

PDIP–16

P SUFFIX

CASE 648

1

MC44605P

AWLYYWW

16

1

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

Current Mode Controller

WW, W = Work Week

• Current Mode Operation up to 250 kHz Output Switching Frequency

• Inherent Feed Forward Compensation

• Latching PWM for Cycle–by–Cycle Current Limiting

• Oscillator with Precise Frequency Control

• Externally Programmable Reference Current

• Secondary or Primary Sensing (Availability of Error Amplifier Output)

• Synchronization Facility

PIN CONNECTIONS

V

R

ref

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

C

WSCD* Program

Output

Gnd

Voltage Feedback Input

Error Amp Output

• High Current Totem Pole Output

• V Undervoltage Lockout with Hysteresis

cc

Max Power Limitation

Disabling Block (C )

ext

• Low Output dV/dT for Low EMI Radiations

• Low Start–Up and Operating Current

Safety/Protection Features

Overheating

Detection

Soft–Start Input

Current Sense Input

Osc Capacitor (C )

T

Demagnetization

Detection Input

Sync and

EHTOVP Input

• Soft–Start Feature

• Demagnetization (Zero Current Detection) Protection

• Overvoltage Protection Facility against Open Loop

(Top View)

• EHT Overvoltage Protection (E.H.T.OVP): Detection of too High

* Winding Short Circuit Detection

Synchronization Pulses

• Winding Short Circuit Detection (W.S.C.D.)

• Limitation of the Maximum Input Power (M.P.L.): Calculation of

Input Power for Overload Protection

• Overheating Detection (O.H.D.): to Prevent the Power Switch from

an Excessive Heating

ORDERING INFORMATION

Device

MC44605P

Package

Shipping

25 Units/Rail

PDIP–16

Latched Disabling Mode

• When one of the following faults is detected: EHT overvoltage,

Winding Short Circuit (WSCD), a too high input power (M.P.L.),

power switch overheating (O.H.D.), an analogic counter is activated

• If the counter is activated for a time that is long enough, the circuit

gets definitively disabled. The latch can only be reset by making

decrease the V down to about 3 V, i.e., practically by unplugging or

cc

turning off the SMPS.

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

May, 2000 – Rev. 2

MC44605/D

MC44605

Block Diagram

R

V

CC

ref

16

1

i

V

enable

ref

cc

Demagnetization

Detection Input

V

demag out

Demagnetization

Management

18 V

8

Supply

Initialization

Block

Reference

Block

UVLO1

UVLO2

V

Output

V

DT

I

2

3

4

C

ref

C

T

Dis

out

10

9

Oscillator

V

S

Output

Gnd

Buffer

Synchronization

and EHTOVP

Input

Set

PWM

Latch

Q

V

cs

Sf

Current

Sense

I

Reset

sense

W.S.C.D*

Comparator

V

CC

ref

E.H.T.OVP

Block

Thermal

Shutdown

V

shift

Over Voltage

Management

V

CC

V

WSCD

V

Level

shift

Programmation

V

UVLO2

CC

enable

V

cs

dis

C

Disabling

Block

MPL

OHD

ext 12

WSCD

Programmation

15

Sf

MPL

Dis

out

I

ref

dis

OHD

V

+

ref

V

2

Error

AMP

cs

Voltage

Feedback

Input

UVLO1

14

O.H.D.

block

MPL

block

–

Soft–Start

V

enable

CC

E/A Output 13

MC44605

7

5

6

11

Current Maximum

Over

Soft–Start

Input

Sense

Input

Power

Heating

Limitation Detection

*W.S.C.D. = Winding Short Circuit Detection

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2

MC44605

MAXIMUM RATINGS

Rating

Pin #

Symbol

Value

40

Unit

mA

V

Total Power Supply and Zener Current

(I

CC

+ I )

Z

Output Supply Voltage with Respect to Ground

2

1

V

18

C

V

CC

Output Current*

Source

Sink

3

mA

I

–750

750

O(Source)

I

O(Sink)

Output Energy (Capacitive Load per Cycle)

Soft–Start

W

5.0

µJ

V

SS

–0.3 to 2.2 V

–0.3 to 5.5 V

Current Sense, Voltage Feedback, E/A Output, C , R , MPL, OHD, C

WSCD

,

V

in

V

T

ref

ext

E.H.T.OVP, Sync Input Current

Source

mA

9

6

I

sync (Source)

EHT

–4.0

10

I

(Source)

Sink

9

6

I

sync (Sink)

EHT (Sink)

Demagnetization Detection Input Current

Source

Sink

8

mA

I

–4.0

10

demag–ib (Source)

I

demag–ib (Sink)

Error Amplifier Output Sink Current

13

I

20

E/A (Sink)

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation at T = 85°C

P

D

0.6

W

A

Thermal Resistance, Junction–to–Air

R

100

°C/W

θJA

Operating Junction Temperature

T

150

°C

J

Operating Ambient Temperature

T

A

–25 to +85

*Maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (V

CC

and V = 12 V, R

values T = –25° to +85°C unless otherwise noted.) (Note 1.)

= 10 kΩ, C = 2.2 nF, for typical values T = 25°C, for min/max

C

ref

T

A

Characteristic

OUTPUT SECTION (Note 2.)

Output Voltage*

Pin #

Symbol

Min

Typ

Max

Unit

3

V

Low Level Drop Voltage (I

(I

= 100 mA)

= 500 mA)

V

OL

–

1.0

1.4

1.2

2.0

Sink

High Level Drop Voltage (I

= 200 mA)

= 500 mA)

V

OH

–

1.5

2.0

2.7

Source

(I

Output Voltage During Initialization Phase

V

OL

V

CC

V

CC

V

CC

= 0 to 1.0 V, I

= 1.0 to 5.0 V, I

= 5.0 to 13 V, I

= 10 µA

–

0.1

1.0

Sink

= 100 µA

Sink

= 1.0 mA

Output Voltage Rising Edge Slew–Rate (C = 1.0 nF, T = 25°C)

dVo/dT

–

300

–

V/µs

L

J

Output Voltage Falling Edge Slew–Rate (C = 1.0 nF, T = 25°C)

–300

L

J

*V must be greater than 5.0 V.

C

1. Adjust V

above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

2. No output signal when the Error Amplifier output is in Low State, i.e., when for instance, V

= 2.7 V.

FB

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3

MC44605

ELECTRICAL CHARACTERISTICS (V

CC

and V = 12 V, R

values T = –25° to +85°C unless otherwise noted.) (Note 1.)

= 10 kΩ, C = 2.2 nF, for typical values T = 25°C, for min/max

C

ref

T

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

ERROR AMPLIFIER SECTION

Voltage Feedback Input (V

= 2.5 V)

14

V

2.4

–2.0

65

2.5

–0.6

70

2.6

–

V

µA

E/A out

= 2.5 V)

FB

Input Bias Current (V

I

FB–ib

FB

Open Loop Voltage Gain (V

= 2.0 V to 4.0 V)

A

VOL

–

dB

E/A out

Unity Gain Bandwidth

BW

MHz

T = 25°C

–

5.5

J

T

= –25° to +85°C

A

Voltage Feedback Input Line Regulation (V

Output Current

= 10 V to 15 V)

V

–10

–

10

mV

mA

CC

FBline–reg

13

Sink (V

T

A

= 1.5 V, V

= 2.7 V)

I

Sink

E/A out

= –25° to +85°C

FB

2.0

12

–

Source (V

T

A

= 5.0 V, V

= 2.3 V)

I

Source

E/A out

= –25° to +85°C

FB

–2.0

–0.2

Output Voltage Swing

V

High State (I

Low State (I

= 0.5 mA, V

= 2.3 V)

= 2.7 V)

V

OH

5.5

–

6.5

1.0

7.5

1.1

E/A out (source)

= 0.33 mA, V

FB

V

OL

E/A out (sink)

FB

CURRENT SENSE SECTION

Maximum Current Sense Input Threshold

(V = 2.3 V and V

7

V

cs–th

0.96

1.0

1.04

= 1.2 V)

Feedback (pin14) Soft–Start (pin11)

Input Bias Current

I

–10

–

–2.0

120

–

µA

cs–ib

Propagation Delay (Current Sense Input to Output at V

MOS transistor = 3.0 V)

of

t

200

ns

TH

PLH(In/Out)

OSCILLATOR AND SYNCHRONIZATION SECTION

Frequency (T = –25° to +85°C)

F

16

–

20

–

kHz

%/V

%/°C

–

A

OSC

Frequency Change with Voltage (V

= 10 V to 15 V)

∆F

/∆V

/∆T

0.05

–

CC

OSC

Frequency Change with Temperature (T = –25° to +85°C)

∆F

–

A

Ratio Charge Current/Reference Current (T = –25° to +85°C)

I

/I

0.39

72

0.48

78

A

charge ref

D

Free Mode Oscillator Ratio = I

/(I

+ I

)

75

%

discharge discharge charge

Synchronization Input Threshold Voltage

Negative Clamp Level (I = 2.0 mA)

9

V

–250

–0.65

–200

–0.5

–150

–0.34

mV

V

syncth

NEG–SYNC

syncth–in

UNDERVOLTAGE LOCKOUT SECTION

Start–up Threshold

1

V

13.6

8.3

14.5

–

15.4

9.6

V

stup–th

Disable Voltage After Threshold Turn–On (UVLO 1)

(T = –25° to +85°C)

A

V

disable1

Disable Voltage After Threshold Turn–On (UVLO 2)

(T = –25° to +85°C)

A

1

V

7.0

7.5

8.0

V

disable2

1. Adjust V

above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

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MC44605

ELECTRICAL CHARACTERISTICS (V

CC

and V = 12 V, R

values T = –25° to +85°C unless otherwise noted.) (Note 1.)

= 10 kΩ, C = 2.2 nF, for typical values T = 25°C, for min/max

C

ref

T

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

REFERENCE SECTION

Reference Output Voltage (V

CC

= 10 V to 15 V)

16

V

2.4

–500

–40

2.5

–

2.6

–100

40

V

ref

Reference Current Range (I = V /R , R = 5.0 k to 25 kΩ)

ref ref ref

I

µA

mV

ref

∆V

Reference Voltage Over I Range

ref

–

ref

DEMAGNETIZATION DETECTION SECTION (Note 2.)

Demagnetization Detect Input

8

Demagnetization Comparator Threshold (V

Decreasing)

V

50

–

–0.5

65

0.5

–

80

–

mV

µs

µA

pin9

Propagation Delay (Input to Output, Low to High)

Input Bias Current (V = 65 mV)

demag–th

t

PLH(In/Out)

I

demag

Minimum Off–Time when the pin 8 is grounded

Negative Clamp Level (I = –2.0 mA)

demag–lb

T

1.5

–0.50

0.50

3.0

4.5

–0.25

0.85

µs

V

DEM–GND

CLVL–neg

CLVL–pos

–0.38

0.72

demag

= +2.0 mA)

Positive Clamp Level (I

demag

V

SOFT–START SECTION (Note 3.)

Ratio Charge Current/I (T = –25° to +85°C)

I

/I

0.37

1.5

–

0.43

–

mA

V

ref

A

ss–ch ref

Discharge Current (V

= 1.0 V)

5.0

2.4

–

soft–start

discharge

Clamp Level

V

2.2

2.6

150

0.55

SS–CLVL

Circuit Inhibition Threshold*

Soft–Start Clamp Level (R

V

30

mV

V

SSinhi

V

= 5 kΩ)

V

0.45

0.5

CS

soft–start

CSsoft–start

*The circuit is shutdown if the Soft–Start pin voltage is lower than this level.

1. Adjust V above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

2. This function can be inhibited by connecting pin 8 to GND. In this case, there is a minimum off–time equal to T

3. The MC44605 can be shut down by connecting Soft–Start pin (pin 11) to Ground.

.

DEM–GND

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MC44605

ELECTRICAL CHARACTERISTICS (V

CC

and V = 12 V, R

values T = –25° to +85°C unless otherwise noted.) (Note 1.)

= 10 kΩ, C = 2.2 nF, for typical values T = 25°C, for min/max

C

ref

T

A

Characteristic

Pin #

Symbol

Min

Typ

Max

Unit

OVERVOLTAGE SECTION

Propagation Delay (V

Protection Level on V

> 18.1 V to V

Low)

(T = –25° to +85°C)

T

1.0

–

4.0

µs

CC

out

PHL(In/Out)

V

15.9

18.1

V

CC

A

CC prot

EHT OVP SECTION (Note 2.)

Negative Clamp Level (I

= –2.0 mA)

NEG–SYNC

–0.65

7.0

–0.5

7.4

–

–0.35

7.8

0

V

synch–in

EHT OVP Input Threshold

V

ref

EHT OVP Input Bias Current (V

= 0 V)

9

I

–5.0

µA

EHT OVP(pin 9)

EHTOVP

WINDING SHORT CIRCUIT DETECTION SECTION

WSCD Threshold with I

MPL & OHD SECTION

MPL Parameter*

= 200 µA

Vshift

70

100

120

mV

pin15

–1

V

Γ

0.185

2.4

0.240

2.5

0.295

2.6

MPL

MPL Comparator Threshold**

OHD Parameter***

V

MPL–th

–1

V

Γ

1.15

2.4

1.50

2.5

1.85

2.6

OHD

OHD Comparator Threshold****

V

OHD–th

*This parameter is defined in the MPL §. This parameter is obtained by measuring the MPL pin average current and dividing this result by the

corresponding squared V , the measured frequency value and the C value deducted from the measured frequency value.

CS

Measurement conditions: V

is typically equal to 18 kHz – R = 10 kΩ 1%, C = 2.2 nF).

**The MPL comparator output is Dis

***This parameter is defined in the OHD §. This parameter is obtained by measuring the OHD pin average current and dividing this result by

T

= 2.3 V, V

soft–start(pin 11)

= 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency

Feedback(pin 14)

ref

T

.

MPL

the corresponding squared V

value and multiplying it by the R value.

ref

CS

Measurement conditions: V

is typically equal to 18 kHz – R = 10 kΩ 1%, C = 2.2 nF).

= 2.3 V, V = 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency

Feedback(pin 14)

soft–start(pin 11)

ref

T

****The OHD comparator output is Dis

.

OHD

DISABLING BLOCK SECTION

Delay Pulse Width

T

–

4.0

–

µs

WSCD

/I

Ratio (EHTOVP and WSCD Disabling Capacitor Charge

Current)I

I

90

100

110

%

Dis–H ref

ref

Ratio (MPL and OHD Disabling Capacitor Charge Current)I

I

/I

2.7

1.0

3.1

–

3.5

5.0

%

V

ref

Dis–L ref

Minimum V

CC

Value Enabling the Disabling Block Latch*

V

CCDis

*Once a fault detection activated it, the Disabling Block Latch gets reset when the V

becomes lower than this threshold.

CC

TOTAL DEVICE

Power Supply Current

I

mA

CC

Startup–Up (V

= 5.0 V with V

= 9.0 V with V

= 12 V with V

increasing)

–

0.35

20

0.55

25

CC

Operating T = –25°C to +85°C*

A

Disabling Mode (V

= 6.0 V)**

–

0.55

CC

Power Supply Zener Voltage (I

Thermal Shutdown

= 35 mA)

V

18.5

–

V

CC

Z

–

155

°C

*Refer to Note 1.

**This consumption is measured while the circuit is inhibited by the Definitive Latch.

1. Adjust V above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction

CC

temperature as close to ambient as possible.

2. This function can be inhibited by connecting pin 9 to GND. In this case, the synchronization block is inhibited too and the MC44605 works

in free mode.

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MC44605

1

Name

Pin Description

This pin is the positive supply of the IC.

The output high state, V , is set by the voltage applied to this pin. With a

V

CC

2

C

OH

separate connection to the power source, it gives the possibility to set by

means of an external resistor the output source current at a different value

than the sink current.

3

4

Output

GND

The output current capability is suited for driving a power MOSFET.

The ground pin is a single return typically connected back to the power

source. It is used as control and power ground.

5

Maximum Power Limitation

This block enables to estimate the input power. When this calculated power

is detected as too high, a fault information is sent to the disabling block in

order to definitively disable the circuit.

6

7

Over–Heating Detection

Current Sense Input

This block estimates the MOSFET heating. When this calculated heating is

too high, the device gets definitively disabled (disabling block action).

A voltage proportional to the current flowing into the power switch is

connected to this input. The PWM latch uses this information to terminate

the conduction of the output buffer. A maximum level of 1 V allows to limit

the inductor current.

8

Demagnetization Detection

A voltage delivered by an auxiliary transformer winding provides to the

demagnetization pin an indication of the magnetization state of the flyback

energy reservoir. A zero voltage detection corresponds to a complete core

demagnetization. The demagnetization detection prevents the oscillator

from a re–start and so the circuit from a new conduction phase, if the

fly–back is not in a dead–time state. This function can be inhibited by

connecting Pin 8 to GND but in this case, there is a minimum off–time

typically equal to 3 µs.

9

Synchronization and E.H.T.OVP Input

Activating the synchronization input pin with a pulse higher or equal to the

negative threshold (typically –200 mV) allows the next switching period to

be reinitialized. The oscillator is free when connecting Pin 9 to GND.

When the E.H.T.OVP pin receives a voltage that is greater than 7.5 V, the

disabling block C

disabled if the C

ext

incorporated to detect and disable the device when the synchronization

pulses are too high.

capacitor is charged so that the circuit gets definitively

voltage becomes higher than V . This block is

ref

ext

10

11

12

Oscillator Capacitor C

Soft–Start

The free mode oscillator frequency is programmed by the capacitor C

T

choice together with the R resistance value. C , connected between

ref

T

pin 10 and GND, generates the oscillator sawtooth.

A capacitor connected to this pin can temporary reduce the maximum

inductor peak current. By this way, a soft–start can be performed. By

connecting pin 11 to Ground, the MC44605 is shut down.

C

(Disabling Block)

When a too high synchronization pulse voltage (E.H.T.OVP) or a winding

ext

short circuit (WSCD) is detected, the capacitor C

is charged using

ext

. In the case of a MPL or OHD fault detection, C

a current source I

is charged using I

Dis– H

. If the C

ext

,

capacitor voltage gets higher than V

Dis–L

ext ref

the circuit is definitively disabled. Then, to restart, the converter must be

switched off in order to make V decrease down to about 0 V.

CC

13

14

E/A Output

The error amplifier output is made available for loop compensation.

Voltage Feedback

This is the inverting input of the Error Amplifier. It can be connected to the

Switching Mode Power Supply output through an optical (or else) feedback

loop or to the subdivided V voltage in case of primary sensing technic.

CC

15

16

Winding Short Circuit Detection

Programmation

The W.S.C.D. block is incorporated to detect the transformer Winding Short

Circuits. This function is performed by detecting the inductor overcurrents

thanks to a comparator which threshold is programmable to be well

adapted to any application.

R

The R value fixes the internal reference current that is particularly used to

ref

perform the precise oscillator waveform. The current range goes from 100

ref

µA up to 500 µA.

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7

MC44605

Summary of the Main Design Equations

The following table consists of equations enabling to dimension a multisynchronized SMPS operating in discontinuous

mode.

Pout

max

is the maximum power the load may draw in normal working.

is easily deducted by dividing Pout

Pout

max

The maximum input power Pin

by the efficiency (η). In this kind of application, the efficiency is generally

max

η

taken equal to 80%.

The inductor value Lp must be chosen lower than Lp

this value (to optimize the application design–in).

or ideally equal to

max

2

2·Vac

NVo

min

In effect, if Lp was higher than Lp

, a synchronized and discontinuous

max

working could not be guaranteed (in some cases, the demagnetization

phase would not be finished while a new conduction phase should start to

follow the synchronization).

Lp

max

Ipk

2

fsync

max

Ipk

max

is the maximum inductor peak current. This current is obtained

when the power to transfer is maximum at the minimum synchronization

frequency (60 W output, 30 kHz in the proposed application).

2

max

fsync

max

L

min

d

is the maximum duty cycle. The duty cycle is maximum at the lowest

max

Lp fsync

max

d

input voltage when the power demand is maximum while the

synchronization frequency also is maximum.

d

max

Vac

min

Pon

Ipk

is the maximum Mosfet on–time losses that are proportional to

max

, d

and Rds (on–time Mosfet resistor).

1

3

max max

on

2

Pon

Rds

Ipk

max

on

max

This conduction losses estimation enables to dimension the power Mosfet.

(V )max is the maximum voltage the power switch must be able to face.

DS

)

In fact, this calculation does not take into account the turnings off spikes.

So, it is necessary to take a margin of at least about 50 V.

(V

DS

max

2

Vac

(N Vout)

Vout

max

(V )max is the maximum voltage the high voltage secondary diode must

D

be able to face. Because of the turning off spikes, a margin must also be

taken.

Vac

max

N

(V ) max

D

2

(A ) and (ni) are the magnetic parameters.

L

(ni)

N

n

Ipk

max

Vout

(ni)

max

must not exceed the ferrite (ni). Otherwise, the transformer may get

saturated when the peak current is high.

(A ) is the ferrite constant that links the primary inductor value to the

L

P

2

.

A

squared number of primary turns: Lp = A x n

L

p

L

2

)

(N

n

Vout

+

Error Amplifier

1.0 mA

Compensation

A fully compensated Error Amplifier with access to the

inverting input and output is provided. It features a typical

DC voltage gain of 70 dB. The non inverting input is

internally biased at 2.5 V and is not pinned out. The

converter output voltage is typically divided down and

monitored by the inverting input. The maximum input bias

current with the inverting input at 2.5 V is –2.0 µA. This can

cause an output voltage error that is equal to the product of

the input bias current and the equivalent input divider source

resistance.

Error

Amplifier

13

14

R

FB

f

2R

2.5 V

C

f

R

Voltage

Feedback

Input

Current

Sense

Comparator

1.0 V

Gnd

MC44605

4

From Power Supply Output

R

2

1

Figure 1. Error Amplifier Compensation

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8

MC44605

The Error Amp Output (Pin 13) is provided for external

V

1.4 V

(pin13)

3

I

loop compensation. The output voltage is offset by two

diodes drops ( 1.4 V) and divided by three before it

connects to the inverting input of the Current Sense

Comparator. This guarantees that no drive pulses appear at

the Source Output (Pin 3) when Pin 13 is at its lowest state

pk

R

S

The Current Sense Comparator threshold is internally

clamped to 1.0 V. Therefore the maximum peak switch

current is:

(V ). This occurs when the power supply is operating and

OL

1 V

I

pk(max)

the load is removed, or at the beginning of a soft–start

interval. The Error Amp minimum feedback resistance is

limited by the amplifier’s minimum source current (0.2 mA)

R

S

Undervoltage Lockout Section

and the required output voltage (V ) to reach the current

OH

sense comparator’s 1.0 V clamp level:

As depicted in Figure 3, an undervoltage lockout has been

incorporated to guarantee that the IC is fully functional

before allowing the system working.

(3 1 V) 1.4 V

R1(min)

22 kΩ

0.2 mA

In effect, the V

is connected to the non inverting input

CC

of a comparator that has an upper threshold equal to 14,5 V

(typical V ) and a lower one equal to 7.5 V (typical

Current Sense Comparator and PWM Latch

stup–th

). This hysteresis comparator enables or disables

The MC44605 operates as a current mode controller. The

circuit uses a current sense comparator to compare the

inductor current to the threshold level established by the

Error Amplifier output (Pin 13). When the current reaches

the threshold, the current sense comparator terminates the

output switch conduction that has been initiated by the

oscillator, by resetting the PWM Latch. Thus the errorsignal

controls the peak inductor current on a cycle–by–cycle

basis. This configuration ensures that only one single pulse

appears at the Source Output during the appropriate

oscillator cycle.

V

disable 2

the reference block that generates the voltage and current

sources required by the system.

Thisblockparticularly,producesV (pin16voltage)and

ref

I

thatisdeterminedbytheresistorR connectedbetween

ref

pin 16 and the ground:

V

ref

I

where V

2.5 V (typically)

ref

R

ref

V

CC

(Pin 1)

R

ref

V

in

Pin 16

V

ref enable

V

C

14

START–UP

UVLO

out

Dis

Reference Block:

Voltage and Current

Sources Generator

R

1

0

2

Q1

V

demag out

3

1

0

(V , I , ...)

ref ref

VS

S

R

3

V

START–UP

14.5 V

disable

7.5 V

Q

Thermal

Protection

C

UVLO1

PWM

Latch

UVLO1

(to SOFTSTART)

Current

Sense

Substrate

V

disable1

9.0 V

R

MC44605

Current Sense

Comparator

7

R

C

S

Figure 3. V

CC

Management

Figure 2. Output Totem Pole

In addition to this, V is compared to a second threshold

CC

level that is nearly equal to 9 V (V ) so that a signal

disable1

The inductor current is converted to a voltage by inserting

UVLO1 is generated to reset the soft start block and so, to

disable the output stage (refer to the Soft–Start §) as soon as

the ground referenced sense resistor R in series with the

S

power switch Q1.

V

becomes lower than V . In this way, the circuit

CC

disable 1

This voltage is monitored by the Current Sense Input

(Pin 7) and compared to a level derived from the Error Amp

output. The peak inductor current under normal operating

conditions is controlled by the voltage at Pin 13 where:

is reset and made ready for a next start–up, before the

reference block is disabled (refer to Figure 3). Thus, finally

the upper limit for the minimum normal operating voltage

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9

MC44605

is9.4V(maximumvalueofV

)andsotheminimum

= 13.6 V].

The MC44605 oscillator achieves four functions:

— it fixes the free mode frequency

disable1

hysteresis is 4.2 V. [(V

)

stup–th min

The large hysteresis and the low start–up current of the

MC44605 make it ideally suited for off–line converter

applications where efficient bootstrap start–up techniques

are required.

— it takes into account the synchronization signal

— it does not allow a new power switch conduction if the

flyback is not in a dead–time state when the circuit

works in demagnetization mode (pin 8 connected)

— it builds the Sf pulse required by the MPL block

During the operating mode, the oscillator sawtooth can

vary between a valley value (1.6 V typically) and a peak one

(3.6 V typically) and presents three distinct phases:

Soft–Start Control Section

The V value is clamped down to the pin 11 voltage.

cs

So, if a capacitor is connected to this pin, its voltage

increases slowly at the start–up (the capacitor is charged by

— the C charge

T

— the C discharge

T

an internal current source 0.4 I ). So, V is limited during

ref

cs

— the phase during which the oscillator voltage is

maintained equal to its valley value. This happens at

the end of a discharge cycle when the synchronization

the start–up and then a soft–start is performed.

This pin can be used to inhibit the circuit by applying a

voltage that is lower than V

(refer to page 4).

SSinhi

or demagnetization condition does not allow a new C

T

Particularly, the MC44605 can be shutdown by connecting

the soft–start pin to ground.

charge phase. During this sequence, I

compensates the charge current I

REGUL

.

charge

The oscillator has two working modes:

As soon as V

is detected (that is V lower than

dis1

cc

V

), a signal UVLO1 is generated until the V falls

disable1 cc

— a free one when there is no synchronization

— a synchronized one.

In the free working, the oscillator grows up from its valley

value to its peak one for the charge phase and when once the

down to V (refer to the undervoltage lockout section §).

dis2

During the delay between the disable1 and the disable2,

using a transistor controlled by UVLO1, the pin 11 voltage

is made equal to zero in order to make the soft–start

arrangement ready to work for the next re–start.

peak value is reached, a discharge sequence makes the C

T

voltage decrease down to its valley value. When the

decrease phase is finished, a new charge cycle occurs if the

V

ref

demagnetization condition is achieved (V

high).

DT

gets high.

Vcs

0.4 I

Otherwise there is a REGUL phase until V

ref

DT

In the synchronized mode, the charge cycle is only

allowed when the synchronization signal gets high while a

Pin 11

Output

Inhibition

D

2.4 V

Soft

Start

Capacitor

Z

dead time has been detected (V

high). This charge phase

is stopped when the synchronization signal has got low and

DT

UVLO1

V

when the oscillator voltage is higher than V , the

int

intermediary voltage level used to generate the calibrated

SSlnhi

pulse Sf by comparing the C voltage to this threshold. So,

T

when these two conditions are performed, a discharge

sequence is set until the oscillator voltage is equal to its

MC44605

valley value. Then, the C voltage is maintained constant

T

thanks to the “REGUL” arrangement until the next

synchronization pulse.

Figure 4. Soft–Start

In both cases, during the charge phase, a signal V is

S

generated.WhenSfbecomeshigh.V getshighandremains

S

Oscillator Section (Figures 5 & 5b)

in this state until the PWN latch is set of Sf is low. Then, V

S

The oscillator and synchronization behavior is

represented in Figure 5b.

keeps low until the next Sf high level. This oscillator

behavior is obtained using the process described in

Figure 5b.

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10

MC44605

a – Free mode

Inductor

current

V

DT

Oscillator

V

int

Sf

Output

b – Synchronized mode

Synchro

input

Inductor

current

V

DT

Oscillator

V

int

Sf

Output

Figure 5b. Oscillator Behavior

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11

MC44605

V

ref

In effect, the output of the latch L1 is:

— high during the oscillator capacitor charge and during

the REGUL phase

— low for the oscillator capacitor discharge

Now, the latch L2 is set when the L1 output is high and the

synchronization condition is performed (that is: sync = 1 –

free mode or synchro signal high state) and during the

I

charge

C

OSCINT

sync

Vint

&

DISCH

PWM

Latch

Output

C

OSC HIGH

dead–time(V high).So,thislatchissetfortheC charge.

DT

T

3.6 V

On the other hand, this latch is reset by the signal used to

reset L1. Consequently, it is reset at the end of the charge

phase.

&

Sf

C

PWM

Latch

Set

OSCINT

&

So, in any case, Q is:

VS

L2

— high during the C charge cycle

T

C

OSC LOW

— low in the other cases

Q

1.6 V

L2

Thus, this latch enables to obtain a signal that is high for

the charge phase and low in the other cases, whatever the

mode (synchronized or free) and whatever the

synchronization pulses width (higher than the delay

necessaryfor the oscillator to reach its intermediary value or

lower than this delay) in the synchronized mode.

That is why:

V

(from demag

block)

DT

C <1.6 V

T

sync

&

S QQ

L1

R

10

L2

C

T

Q

R

DISCH

C

OSC REGUL

— the discharge current source must be connected to the

1

0

oscillator capacitor when Q is low. The condition

(C voltage higher than the valley value) is added to

T

L1

stop the discharge phase as soon as the oscillator

voltage is detected as lower than the valley value

(without any delay due to the L1 latch propagation

time).

&

0

1

Q

L2

I

regul

I

discharge

MC44605

— the REGUL current source must be connected when:

• Q is high (charge or REGUL phase)

L1

• Q is low (the oscillator is not in a charge phase)

Figure 5. Oscillator

L2

On the other hand, the oscillator charge is stopped when:

— the oscillator voltage reaches the peak value in the

free mode

Synchronization Section (Note 1)

The synchronization block consists of a protection

arrangement similar to the demagnetization block one (a

diode + a negative active clamping system (Note 2)). In

addition to this, a high value resistor (R – about 50 kΩ) is

incorporated as the pin 9 input is also used by the EHTOVP

section.

The signal obtained at the output of this protection

arrangement, is compared to a negative threshold (–200 mV,

typically) so that when the synchronization pulse applied to

thepin9(througharesistororaresistorsdividertoadaptthis

input to the EHTOVP function), is higher than this

threshold, the system considers that the synchronization

condition is performed (free mode or synchronization signal

high level).

— the oscillator voltage is higher than the intermediary

value (V ) and the synchronization signal is negative,

int

in the synchronized mode.

Consequently, in any case, Q that is high during the

L2

oscillator charge phase, is high for the delay during which

the oscillator voltage grows from the valley value up to the

intermediaryone. That is why the signal Sf (refer to theMPL

block) that must be high when the oscillator voltage is

between the valley value and the intermediary one during

the charge phase (Q high), is obtained using an AND gate

L2

with the following inputs:

— Q (Q high <=> charge phase)

L2 L2

— C

(C

high<=>theC voltageislower

OSCINT OSCINT T

than the intermediary value).

So, using the output of this AND gate, Sf is obtained.

This signal Sf is connected to a logic block consisting of

two AND gates and an OR one. This block aims at supplying

a signal VS that:

— gets high as soon as Sf becomes high if the PWM

latch output is low

Note 1. The synchronization can be inhibited by connecting the

pin 9 to the ground. By this means, a free mode is

obtained.

Note 2. This negative active clamping system works even if the

circuit is off. This feature is really useful as

synchronization pulses may be applied while the product

is off.

— gets low as soon as the PWM latch is set and then

remains low until the next cycle.

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12

MC44605

V

A diode D is incorporated to clamp the positive applied

CC

Synchro.

Signal

voltages while an active clamping system limit the negative

voltages to typically –0.33 V. This negative clamp level is

high enough to avoid the substrate diode switching on.

E.H.T. OVP

Block

Negative Active

Clamping System

A

latch system is incorporated to keep the

Pin 9

demagnetization block output level low as soon as a voltage

lower than 65 mV is detected and as long as a new restart is

produced (high level on the output (refer to Figure 8). This

process avoids that any ringing on the signal used on the

pin 8, disrupts the demagnetization detection (refer to

Figure 7). Finally, this method results in a very accurate

R

sync

–200 mV

MC44605

demagnetizationphase detection, andthe signal V drawn

DT

from this block is high only for the dead time. Therefore, an

oscillator re–start and so, a new power switch conduction is

only allowed during the dead–time.

Figure 6. Synchronization

For a higher safety, the V

output of the

demagout

Demagnetization Section

demagnetization block is also directly connected to the

output, to disable it during the demagnetization phase (refer

to the block diagram).

The demagnetization detection can be inhibited by

connectingpin 8 to the ground but in this case, a timer (about

3 µs) that is incorporated to set the latch when it can not be

This block is incorporated to detect the complete core

demagnetization in order to prevent the power MOSFET

from switching on if the converter is not in a dead time

phase. That is why this block inhibits any oscillator re–start

as long as the inductor current is not finished (from the

beginning of the on–time to the end of the demagnetization

phase).

set by V

Figure 8).

, results in a minimum off–time (refer to

demagout

In a fly–back, a good means to detect the demagnetization

Output

phase consists in using the V

this voltage is:

winding voltage. In effect,

CC

Buffer

— negative during the on–time,

— positive during the off–time,

— equal to zero for the dead–time with generally a

ringing (refer to Figure 7).

3

s

R

Q

Demag

V

CC

Q

S

Zero

Current

Detection

Negative Active

Clamping System

V

demag out

0.75 V

V

pin 8

Pin 8

65 mV

C DEM

D

65 mV

Oscillator

V

DT

–0.33 V

Figure 8. Demagnetization Block

On–Time Off–Time Dead–Time

Overvoltage Protection Section

Figure 7. Demagnetization Detection

The overvoltage arrangement compares a portion V to

cc

(2,5 V) (refer to Figure 9). In fact, this threshold

V

ref

corresponds to a V

That is why, the MC44605 demagnetization detection

consists of a comparator that compares the V winding

equal to to 17 V. When the V is

CC

cc

CC

voltage to a reference that is typically equal to 65 mV.

higher than this level, the output is latched off until a new

circuit re–start.

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13

MC44605

V

ref

For instance, if this threshold value is required to be equal

to 30 V, V must be equal to 7.5 V when the

V

CC

pin9

synchronization pulse value is 30 V.

So, in this case:

In

Delay

Out

5.0 µs

τ

T

r2

30

7.5

2.5 V

r1 r2

0

Enable

Then, the ratio (r1/r2) can be deducted:

V

OVP out

r1

3

τ

In

Out

r2

Delay

C

OVLO

So, as r1 and r2 must be negligible in relation to R (about

50 kΩ), the couple of resistors can be chosen as follows:

2.0 µs

2.5 V

(V

(If V

= 1.0,

OVP out

the Output is Disabled)

)

ref

r1

3 kΩ

and:

Figure 9. Overvoltage Protection

r2

1 kΩ

A delay (2 µs) is incorporated in order to avoid any

activation due to interferences by only taking into account

the overvoltages that last at least 2 µs.

Winding Short Circuit Detection Section (WSCD)

The MC44605 being designed to control a Fly–Back

SMPS, this block is incorporated to detect a short circuit on

a transformer winding or on an output diode (refer to

Figure 11).

The V

is connected when once the circuit has

CC

started–up in order to limit the circuit start–up consumption

(T is switched on when once V has been generated).

ref

The overvoltage section is enabled 5 µs after the regulator

has started to allow the reference V to stabilize.

ref

+

E.H.T. Overvoltage Protection Section

+

AC Line

L

p

+

This block uses the synchronization input as this section

isincorporatedtodetecttoohighsynchronizationpulsesand

then to activate the device definitive latch in this case.

L

leak

MC44605

V

CC

Synchro.

Pulses

Synchronization

Block

R

S

Negative Active

Clamping System

r1

Disabling

Block

Figure 11. Winding Short Circuit Fault

Pin 9

r2

C

2R

EHTOVP

E.H.T.

OVP

In the case of a Winding Short Circuit, the primary

inductor L is short circuited and then the current increase

p

4 V

R

is only controlled by the leakage inductor L

.

leak

V

ref

In current mode, the power switch conduction is stopped

when the inductor current is detected as high enough, by the

MC44605

controller. In fact, when the current sense resistor (R )

s

voltage gets equal to V , the current sense comparator

cs

switches to reset the output.

Figure 10. E.H.T. OVP

Now, the circuit has a propagation delay and the power

switch needs some time to turn off. Consequently, there is a

This block consists of a high impedance resistors bridge

(R is nearly equal to 50 kΩ – refer to Figure 10) so that the

EHTovp threshold is 7.5 V. So, using an external resistors

bridge (r1, r2 <<R), the synchronization pulse level above

which the working must be considered as wrong, can be

adjusted.

delay δt between the moment at which the R voltage gets

s

equal to V and the actual current increase stop. So, this

cs

results in an overcurrent (refer to Figure 12).

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14

MC44605

Finally, when there is a winding short circuit, an

overcurrent is detected by the WSCD comparator. The

output of this comparator, V , is connected to the

(V

CS

+ V

)/R

shift S

(Vin x t/L

leak

WSCD

disabling block (refer to the disabling block §).

Vin x t/L

p

Maximum Power Limitation Section (MPL)

V

CS

/R

S

The MPL block is designed to calculate this input power

using the following equation:

1

2

L

Ipk

f

P

where: Lp is the inductor value

time

t

Ipk is the inductor peak current

f is the switching frequency

Figure 12. Overcurrent in a WSCD Case

As V is proportional to the inductor peak current

cs

(V = R x Ipk), the squared Ipk value is estimated by

cs

s

2

building a current source proportional to V . This current

cs

Now, innormalworking, thisovercurrent Ipkisequalto:

is chopped by a calibrated pulse Sf, generated at each new

oscillator cycle (refer to Figure 14).

Finally, using an external resistor and capacitor network

Vin δt

Ipk

L

P

where: V is the input voltage (rectified a.c. line)

in

(R

, C

) on the MPL pin, a voltage V

,

MPL

While in a WSCD case:

proportional to the input power can be obtained.

Vin δt

In effect,

( Ipk)

WSCD

L

Leak

(Sf)

T

2

V

R

k

Vcs

MPL

Consequently, as the leakage inductor value is generally

much lower than the primary one (less than 5% generally),

the overcurrent is much higher in the WSCD case. That is

why this fault can be detected by detecting the high

overcurrents.

where: k

is the multiplier gain

MPL

(Sf) is the width of the calibrated pulse

T is the switching (oscillator) period

Now, as Sf is built comparing the oscillator to a constant

level, (Sf) is proportional to R and C :

So, the WSCD block consists of comparing the sensed

ref

T

currenttoareferenceequalto:(V +V

),whereV is

cs shift

shift

(Sf)

k1

R

C

a voltage proportional to the current injected in the pin 15

(refer to Figure 13).

ref

T

where: k1 is a constant

Ontheotherhand,k

MPL

thatisdependingonthereference

Vin

current source I , is proportional to 1/R

:

ref

1

k

k2

C

WSCD

MPL

I

R

sense

ref

Disabling

Block

Pin 7

where: k2 is a constant

So:

V

WSCD

Pin 15

3.75 Ω

2

V

R

k1 k2 Vcs

f

C

MPL

T

V

= 500

V

shift

shift shift

I

where: C is the oscillator capacitor

T

shift

Finally:

Vcs

2

V

R

Γ

Vcs

f

C

MC44605

MPL

T

where: Γ

is the MPL parameter as defined in the

MPL

Figure 13. WSCD

specification. This is a constant equal to the product

(k1 x k2).

Now, astheovercurrentleveldependsontheinputvoltage

Now, as:

V , it is preferable to use a V

proportional to this input

. So, the WSCD pin must

in

shift

voltage instead of a constant V

1

2

L

Ipk

f

shift

P

be connected to V through a resistor that fixes V

by

in

shift

adjusting the current injected in this pin 15.

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15

MC44605

and:

So:

where: p are the power switch on–time losses

on

R

is the conduction MOSFET resistor

dson

d is the duty cycle

As in the MPL section, the squared Ipk term is estimated

by building a current source proportional to Vcs .

The duty cycle is taken into account thanks to the action

on this current source of a “chopper” controlled by the

circuit output. By this means, the pin 6 average current is

proportional to the squared peak current multiplied to the

duty cycle (refer to Figure 14).

Vcs

R

Ipk

S

2

R

2

R

Γ

C

MPL

T

S

V

MPL

L

P

AcomparatorisusedtocompareV

MPL

of which, Dis

MPL

latch” of the disabling block. So, when the calculated power

is higher than the threshold, the circuit is definitively

disabled (the system considers that there is an overload

condition).

toV ,theoutput

ref

, is connected to the “definitive inhibition

So, using an external resistor and capacitor network

(R

,C

)onthispin,avoltageV

,proportionalto

OHD OHD

OHD

the conduction losses can be obtained.

LikeintheMPLblock,thisvoltageV

,iscomparedto

Finally, replacing V

the R

by 2.5 V (the threshold value),

value to be used, can be deducted:

OHD

MPL

2.5 V. If V

gets higher than this threshold, the disabling

OHD

block is activated by Dis

MPL

(output of the comparator).

choice enables to obtain a

OHD

1.25

L

P

The external resistor R

calculatedV

OHD

equal to 2.5 V when the conduction losses

R

MPL

2

S

Γ

C

R

(Pin)

max

OHD

MPL

T

are equal to their maximum value.

In effect,

Vcs

2

V

R

k

Vcs

d

OHD

where: k

is the multiplier gain

x

OHD

Now, as k

OHD

that is depending on the reference current

2

source I , is proportional to 1/R

:

k

Vcs

OHD

k

Vcs

MPL

ref

1

k

k2

T

MPL

Sf

T

OHD

R

ref

Output

where: k2 is a constant

So:

V

MPL

2

Vcs

R

V

R

k2

d

Dis

OHD

ref

Finally:

2.5 V

Disabling

Block

2

R

Γ

Vcs

d

OHD

V

OHD

R

ref

V

MPL

where: Γ

is the OHD parameter as defined in the

OHD

Dis

MPL

2.5 V

specification. This is a constant equal to k2.

Now, as:

MC44605

Vcs

R

Ipk

S

So, replacing Vcs and using the p equation:

on

Figure 14. OHD and MPL

2

R

3

R

Γ

OHD

dson

S

V

p

on

OHD

R

Overheating Detection Section (O.H.D.)

ref

So, by choosing the value of R

corresponding to V

ref

dissipation is such that the heating is higher than this

threshold, the “definitive inhibition latch” of the Disabling

Block is activated and so, the output gets definitively

disabled.

, the heating

is determined. If the MOSFET

OHD

In the MPL block, the converter input power is calculated.

In the O.H.D. block, that is the power MOSFET heating

which is calculated, using the following equation:

1

3

2

p

R

Ipk

d

on

dson

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16

MC44605

Consequently, by replacing V

OHD

value) in the last equation, the value R

deducted:

by 2.5 V (threshold

to use, can be

V

ref

OHD

104% I

ref

3.4% I

ref

2.5

R

ref

R

dson

(p

R

OHD

2

S

1

0

1

0

3

Γ

)

E.H.T.

OVP

Dis

on max

OHD

Q

V

S

R

WSCD

MPL

where: (p

)

are the maximum on time losses that are

on max

Pin 12

acceptable.

V

CC

Delay

4 S

Disabling Block Section

This section consists of a “definitive inhibition latch”

Definitive

Inhibition

Latch

(directly supplied by the V ) that disables the output (the

cc

output is forced to zero).

2.5 V

In effect, this block aims at definitively disabling the

circuit when one of the following faults is detected:

— a Winding Short Circuit

Output

Buffer

— too high synchronization pulses

— a too high input power

MC44605

— a too high power switch (MOSFET) heating

The signals corresponding to these faults are high when a

fault is detected (for instance, when the input power is

Figure 15. Disabling Block

detected as too high, Dis

When one (or several) of these four faults is detected, a

current source charges C (with a certain duty cycle) and

when its voltage becomes higher than V , the definitive

ref

inhibition latch is activated. Thus, the circuit gets

definitively disabled after a delay depending on C

According to the detected fault, the current that charges

is high).

This latch is reset when the V falls down to about 3 V.

cc

MPL

In this case, if a new start up is performed, the circuit will

work normally (until this fault or another one is detected).

Practically, to re–start after a fault has shutdown the

circuit, the converter must be turned off for a time long

ext

.

enoughtoenabletheV capacitordischarge(repairtime...).

ext

cc

C

is not the same:

The typical values are:

Note: As V

is generally a really narrow pulse, it is

ext

WSCD

necessary to add a latch and a delay to build a 4 µs width

pulse when V becomes high.

— 260 µA for EHTOVP and WSCD

— 8.5 µA for OHD and MPL

WSCD

when R is equal to 10 kΩ.

ref

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17

MC44605

Application Schematic

90 Vac to

264 Vac

1nF / 1KV

RFI

R1

1Ω / 5W

Filter

4.7 MΩ

C4....C7

1nF/500V

V

in

160 V/0.1 A

D1 ... D4

1N4007

100

400 V

F

MR856

100

2x150 KΩ//

47 KΩ

F

1.8 MΩ

47 nF

1N4934

70 V/0.2 A

47 kΩ/2W

SYNC

1N4937

100

25 V

F

1N4937

Laux

100 kΩ

3.3 kΩ

1 F

1.2 kΩ

27 KΩ

120 pF

8

7

6

5

4

3

2

1

9

2.2 nF

40 V/0.5 A

10

11

12

13

14

15

16

1nF

1N4937

470

1

F

100 kΩ

4.7

F

Lp

F

105

kΩ

4.7

F

10 nF

470

kΩ

1N4148

1 nF

340 KΩ

470 pF

1305 V/0.65 A

MTA4N60E

1N4934

1000

22 kΩ

1N4937

470 Ω

39 Ω

10 kΩ

1 kΩ

F

100 Ω

330 Ω

8 V/0.5 A

0.22 Ω

1 kΩ

22 kΩ

10 kΩ

220 nF

1N4934

1000

F

2.2 kΩ

270 Ω

226 kΩ

MOC8103

10 kΩ

1N4733

100 nF

V

in

2.2 kΩ

6.8 nF

33 nF

TL431

3.6 kΩ

65 W output SMPS controlled by the MC44605

Mains input range: 90 Vac <–> 264 Vac

Synchronization range: 30 kHz <–> 100 kHz

Orega Transformer ref. G5984–00

(Lp = 195 µH)

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18

MC44605

Performances

Input Voltage

90–260 Vac

Synchronization Range

30 to 100 kHz

160 V

100 mA

200 mA

500 mA

650 mA

500 mA

70 V

40 V

13.5 V

8 V

Outputs

110 Vac (Input)

220 Vac

80%

83%

81%

82%

80%

30 kHz

60 kHz

110 Vac

Measured Efficiency

(Pout = 64 W)

220 Vac

110 Vac

100 kHz

220 Vac

110 Vac

220 Vac

2.0 W

3.2 W

Standby Losses

(No Load – Pout = 0)

EHTovp Threshold

28 V

110 Vac (Input)

220 Vac

86 W (Input)

87 W

30 kHz

110 Vac

90 W

Maximum Power

Limitation

60 kHz

220 Vac

95 W

110 Vac

94 W

100 kHz

220 Vac

110 W

30 kHz

85 V

Overheating Detection

(Pout = 64 W):

The input rms levels at which

the circuit detects an OHD case.

60 kHz

76 V

100 kHz

Winding Short Circuit

Detection

Fully Functional

(Tested by short circuiting one output diode or one transformer winding)

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19

MC44605

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

CASE 648–08

ISSUE R

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

16

1

9

8

B

S

INCHES

DIM MIN MAX

0.770 18.80

MILLIMETERS

MIN

MAX

19.55

6.85

4.44

0.53

1.77

F

A

B

C

D

F

0.740

0.250

0.145

0.015

0.040

C

L

0.270

0.175

0.021

0.70

6.35

3.69

0.39

1.02

SEATING

PLANE

–T–

G

H

J

K

L

M

S

0.100 BSC

0.050 BSC

2.54 BSC

1.27 BSC

K

M

0.008

0.015

0.130

0.305

10

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295

0

2.80

7.50

0

G

D 16 PL

0.020

0.040

0.51

1.01

M

0.25 (0.010)

T A

GreenLine is a trademark of Motorola, Inc.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

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attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

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PUBLICATION ORDERING INFORMATION

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JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2745

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Email: ONlit@hibbertco.com

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EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC44605/D

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20


型号：	MC44605
厂家：	ONSEMI
描述：	High Safety, Latched Mode, GreenLine PWM Controller for (Multi)Synchronized Applications 高安全性，锁存模式， GREENLINE PWM控制器（多）同步应用控制器
文件：	总20页 (文件大小：331K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC44605 [ONSEMI]

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