MC74LVX245DTR2G [ONSEMI]
Octal Bus Transceiver;
| 型号： | MC74LVX245DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Octal Bus Transceiver 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX245
Octal Bus Transceiver
With 5 V−Tolerant Inputs
The MC74LVX245 is an advanced high speed CMOS octal bus
transceiver.
It is intended for two−way asynchronous communication between
data buses. The direction of data transmission is determined by the
level of the T/R input. The output enable pin (OE) can be used to
disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static
discharge.
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SOIC−20
TSSOP−20
DT SUFFIX
CASE 948E
DW SUFFIX
CASE 751D
Features
• High Speed: t = 4.7 ns (Typ) at V = 3.3 V
PD
CC
PIN ASSIGNMENT
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
V
CC
OE B0 B1 B2 B3 B4 B5 B6 B7
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
20 19 18 17 16 15 14
12
13
11
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
1
2
3
4
5
6
7
9
8
10
T/R A0 A1 A2 A3 A4 A5 A6 A7 GND
20−Lead (Top View)
• These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
Application Notes
• Do Not Force a Signal on an I/O Pin when it is an Active Output,
Damage May Occur
20
• All Floating (High Impedance) Input or I/O Pins must be Fixed by
Means of Pullup or Pulldown Resistors or Bus Terminator ICs
LVX245
AWLYYWWG
• A Parasitic Diode is Formed between the Bus and V Terminals
CC
1
Therefore, the LVX245 cannot be Used to Interface 5.0 V to 3.0 V
Systems Directly
SOIC−20
20
LVX
245
ALYWG
G
1
TSSOP−20
LVX245
A
WL, L
Y
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
WW, W
G or G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 5
MC74LVX245/D
MC74LVX245
OE 19
T/R 1
2
3
4
5
6
7
8
9
A0
A1
A2
A3
A4
A5
A6
A7
18
17
16
15
14
13
12
11
B0
B1
B2
B3
B4
B5
B6
B7
Figure 1. Logic Diagram
Table 1. PIN NAMES
Pins
Function
Output Enable Input
OE
T/R
Transmit/Receive Input
A0−A7
Bo−B7
Side A 3−State Inputs or 3−State Outputs
Side B 3−State Inputs or 3−State Outputs
INPUTS
OPERATING MODE
OE
L
T/R
L
Non−Inverting
B Data to A Bus
L
H
A Data to B Bus
Z
H
X
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State;
X = High or Low Voltage Level and Transitions are Acceptable; For I
reasons, Do Not Float Inputs
CC
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2
MC74LVX245
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
–0.5 to +7.0
–0.5 to +7.0
V
DC Input Voltage (T/R, OE)
DC Output Voltage
V
in
I/O
IK
V
–0.5 to V +0.5
V
CC
I
Input Diode Current
−20
mA
mA
mA
mA
mW
°C
I
Output Diode Current
DC Output Current, per Pin
20
25
OK
I
out
CC
I
DC Supply Current, V and GND Pins
75
CC
P
D
Power Dissipation
180
T
stg
Storage Temperature
–65 to +150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
V
in
DC Input Voltage (T/R, OE)
DC Output Voltage
5.5
V
V
I/O
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time
−40
0
+85
100
°C
ns/V
A
Dt/DV
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −40 to 85°C
A
V
CC
V
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
V
OH
High−Level Output Voltage
(V = V or V )
I
I
I
= −50 mA
= −50 mA
= −4 mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
in
IH
IL
V
OL
Low−Level Output Voltage
(V = V or V )
I
OL
I
OL
I
OL
= 50 mA
= 50 mA
= 4 mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
in
IH
IL
I
Input Leakage Current
V
= 5.5 V or GND
3.6
3.6
3.6
0.1
1.0
2.5
mA
mA
mA
in
in
(T/R, OE)
= V or V
IH
I
Maximum 3−State Leakage Current
V
in
0.2
5
OZ
IL
V
out
= V or GND
CC
I
Quiescent Supply Current
V
in
= V or GND
4.0
40.0
CC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MC74LVX245
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T = −40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Propagation Delay
Input to Output
V
V
V
= 2.7 V
C = 15 pF
C = 50 pF
L
6.1
8.6
10.7
14.2
1.0
1.0
13.5
17.0
ns
PLH
t
CC
CC
CC
L
PHL
= 3.3 0.3 V
= 2.7 V
C = 15 pF
4.7
7.2
6.6
10.1
1.0
1.0
8.0
11.5
L
C = 50 pF
L
,
Output Enable Time to
High and Low Level
C = 15 pF
9.0
11.5 20.4
16.9
1.0
1.0
20.5
24.0
ns
ns
ns
PZL
t
L
R = 1 kW
C = 50 pF
L
PZH
L
V
CC
= 3.3 0.3 V
C = 15 pF
7.1
9.6
11.0
14.5
1.0
1.0
13.0
16.5
L
R = 1 kW
C = 50 pF
L
L
,
Output Disable Time From
High and Low Level
V
CC
= 2.7 V
C = 50 pF
L
11.5 18.0
1.0
21.0
PLZ
t
R = 1 kW
PHZ
L
V
CC
= 3.3 0.3 V
C = 50 pF
L
9.6
12.8
1.0
14.5
R = 1 kW
L
t
t
Output−to−Output Skew
(Note 1)
V
CC
V
CC
= 2.7 V
= 3.3 0.3 V
C = 50 pF
1.5
1.5
1.5
1.5
OSHL
OSLH
L
C = 50 pF
L
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
CAPACITIVE CHARACTERISTICS
T
A
= 25°C
T = −40 to 85°C
A
Min
Typ
4
Max
Min
Max
Symbol
Parameter
Unit
pF
C
Input Capacitance (T/R, OE)
10
10
in
C
I/O
C
PD
Maximum 3−State I/O Capacitance
8
pF
Power Dissipation Capacitance (Note 2)
21
pF
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 3.3V, Measured in SOIC Package)
r
f
L
CC
T
A
= 25°C
Typ
0.5
Max
Symbol
Characteristic
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.8
−0.8
2.0
OLP
OL
Quiet Output Minimum Dynamic V
−0.5
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
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4
MC74LVX245
SWITCHING WAVEFORMS
V
CC
T/R
50%
GND
V
CC
V
CC
Input
50% V
OE
50% V
CC
CC
50%
A or B
GND
t
t
PLZ
GND
PZL
HIGH
t
t
PHL
PLH
IMPEDANCE
50% V
Output
B or A
CC
A or B
A or B
50% V
CC
V
+0.3V
-0.3V
OL
t
t
PHZ
PZH
V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 2.
Figure 3.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kW
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4. Propagation Delay Test Circuit
Figure 5. 3−State Test Circuit
ORDERING INFORMATION
†
Device
MC74LVX245DWR2G
Package
Shipping
SOIC−20
(Pb−Free)
1000 / Tape & Reel
2500 / Tape & Reel
MC74LVX245DTR2G
TSSOP−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC74LVX245
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
20X K REF
K
M
S
S
V
0.10 (0.004)
T U
S
K1
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T U
N
A
−V−
MILLIMETERS
INCHES
MIN
F
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
−W−
C
F
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
G
D
J
H
J1
K
DETAIL E
0.100 (0.004)
−T− SEATING
K1
L
6.40 BSC
0.252 BSC
0
PLANE
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74LVX245
PACKAGE DIMENSIONS
SOIC−20
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
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MC74LVX245/D
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