MMBTA13LT1 [ONSEMI]
Darlington Amplifier Transistors(NPN Silicon); 达林顿放大器晶体管（ NPN硅）
| 型号： | MMBTA13LT1 |
| 厂家： | 
ONSEMI |
| 描述： | Darlington Amplifier Transistors(NPN Silicon) |
| 文件： | 总8页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
MMBTA13LT1
MMBTA14LT1
Darlington Amplifier
Transistors
MMBTA14LT1 is a Preferred Device
NPN Silicon
MAXIMUM RATINGS
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Symbol
Value
30
Unit
Vdc
3
V
CES
CBO
EBO
1
V
V
30
Vdc
2
Emitter–Base Voltage
10
Vdc
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
300
mAdc
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
C
Symbol
Max
Unit
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
T
= 25°C
A
COLLECTOR 3
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
Thermal Resistance Junction to Ambient
Total Device Dissipation
R
BASE
1
qJA
P
D
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
417
mW/°C
°C/W
°C
EMITTER 2
Thermal Resistance Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
qJA
T , T
J stg
–55 to +150
MMBTA13LT1 = 1M; MMBTA14LT1 = 1N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Max
Unit
Collector–Emitter Breakdown Voltage
V
30
—
—
—
Vdc
nAdc
nAdc
(BR)CES
(I = 100 mAdc, V
C BE
= 0)
Collector Cutoff Current
(V = 30 Vdc, I = 0)
I
100
100
CBO
CB
Emitter Cutoff Current
(V = 10 Vdc, I = 0)
E
I
EBO
EB
C
1. FR–5 = 1.0 ꢀ 0.75 ꢀ 0.062 in.
2. Alumina = 0.4 ꢀ 0.3 ꢀ 0.024 in. 99.5% alumina.
Preferred devices are ON Semiconductor recommended choices for future use and best overall value.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
March, 2001 – Rev. 1
MMBTA13LT1/D
MMBTA13LT1 MMBTA14LT1
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
Symbol
Min
Max
Unit
(3)
ON CHARACTERISTICS
DC Current Gain
(I = 10 mAdc, V
C
h
FE
—
= 5.0 Vdc)
CE
MMBTA13
MMBTA14
5000
10,000
—
—
(I = 100 mAdc, V
C CE
= 5.0 Vdc)
MMBTA13
MMBTA14
10,000
20,000
—
—
Collector–Emitter Saturation Voltage
(I = 100 mAdc, I = 0.1 mAdc)
V
—
1.5
Vdc
Vdc
CE(sat)
C
B
Base–Emitter On Voltage
(I = 100 mAdc, V = 5.0 Vdc)
V
BE
—
2.0
C
CE
SMALL–SIGNAL CHARACTERISTICS
(4)
Current–Gain — Bandwidth Product
f
T
125
—
MHz
(I = 10 mAdc, V = 5.0 Vdc, f = 100 MHz)
C
CE
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
4. f = |h | • f .
test
T
fe
R
S
i
n
e
n
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
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MMBTA13LT1 MMBTA14LT1
NOISE CHARACTERISTICS
(V
= 5.0 Vdc, T = 25°C)
CE
A
500
2.0
BANDWIDTH = 1.0 Hz
≈ 0
BANDWIDTH = 1.0 Hz
R
S
1.0
0.7
0.5
200
100
50
I
C
= 1.0 mA
0.3
0.2
10 µA
100 µA
100 µA
10 µA
0.1
0.07
0.05
20
I
C
= 1.0 mA
10
0.03
0.02
5.0
10 20
50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
f, FREQUENCY (Hz)
10 20
50 100 200 500 1Ăk 2Ăk 5Ăk 10Ăk 20Ăk 50Ăk 100Ăk
f, FREQUENCY (Hz)
Figure 2. Noise Voltage
Figure 3. Noise Current
200
14
12
BANDWIDTH = 10 Hz TO 15.7 kHz
BANDWIDTH = 10 Hz TO 15.7 kHz
= 10 µA
100
70
10
8.0
6.0
4.0
2.0
I
C
10 µA
50
100 µA
100 µA
30
20
I
C
= 1.0 mA
1.0 mA
10
0
1.0 2.0
5.0
10
20
50 100 200
500 1000
1.0 2.0
5.0
10
20
50 100 200
500 1000
R , SOURCE RESISTANCE (kΩ)
S
R , SOURCE RESISTANCE (kΩ)
S
Figure 4. Total Wideband Noise Voltage
Figure 5. Wideband Noise Figure
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MMBTA13LT1 MMBTA14LT1
SMALL–SIGNAL CHARACTERISTICS
20
10
4.0
V
= 5.0 V
CE
f = 100 MHz
= 25°C
T
= 25°C
J
T
J
2.0
7.0
5.0
C
ibo
1.0
0.8
C
obo
0.6
0.4
3.0
2.0
0.2
0.04
0.1 0.2
0.4
1.0 2.0 4.0
10 20
40
0.5 1.0
2.0
0.5 10 20
50
100 200
500
V , REVERSE VOLTAGE (VOLTS)
R
I , COLLECTOR CURRENT (mA)
C
Figure 6. Capacitance
Figure 7. High Frequency Current Gain
200Ăk
3.0
2.5
2.0
1.5
1.0
0.5
T
= 125°C
J
T
= 25°C
J
100Ăk
70Ăk
50Ăk
I
C
=
50 mA
250 mA 500 mA
10 mA
25°C
30Ăk
20Ăk
10Ăk
7.0Ăk
5.0Ăk
-ā55°C
V
= 5.0 V
CE
3.0Ăk
2.0Ăk
500
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000
5.0 7.0 10
20 30
50 70 100
200 300
I , COLLECTOR CURRENT (mA)
C
I , BASE CURRENT (µA)
B
Figure 8. DC Current Gain
Figure 9. Collector Saturation Region
1.6
1.4
-ā1.0
-ā2.0
-ā3.0
-ā4.0
-ā5.0
-ā6.0
*APPLIES FOR I /I ≤ h /3.0
C B FE
25°C TO 125°C
T
= 25°C
J
*R
qVC
FOR V
CE(sat)
V
@ I /I = 1000
C B
-ā55°C TO 25°C
25°C TO 125°C
BE(sat)
1.2
1.0
0.8
0.6
V
@ V = 5.0 V
BE(on)
CE
q
FOR V
BE
VB
-ā55°C TO 25°C
V
@ I /I = 1000
C B
CE(sat)
5.0 7.0
10
20 30
50 70 100 200 300
500
5.0 7.0 10
20 30
50 70 100
200 300 500
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 10. “On” Voltages
Figure 11. Temperature Coefficients
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MMBTA13LT1 MMBTA14LT1
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
SINGLE PULSE
0.05
0.1
0.1
0.07
SINGLE PULSE
0.05
0.03
0.02
Z
Z
= r(t) • R
= r(t) • R ąT
θJA
ąT
J(pk)
- T = P
C
Z
Z
θJC(t)
θJA(t)
θJC J(pk)
(pk) θJC(t)
- T = P
A
(pk) θJA(t)
0.01
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0Ăk
2.0Ăk
5.0Ăk 10Ăk
t, TIME (ms)
Figure 12. Thermal Response
1.0Ăk
700
FIGURE A
1.0 ms
500
t
P
T
= 25°C
300
200
C
100 µs
T
A
= 25°C
P
P
P
P
1.0 s
100
70
50
t
1
30
20
CURRENT LIMIT
THERMAL LIMIT
1/f
SECOND BREAKDOWN LIMIT
t
1
DUTYĂCYCLE + t Ăf +
10
0.4 0.6
1
t
P
40
1.0
2.0
4.0 6.0
10
20
PEAK PULSE POWER = P
P
V , COLLECTOR-EMITTER VOLTAGE (VOLTS)
CE
Figure 13. Active Region Safe Operating Area Design Note: Use of Transient Thermal Resistance Data
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MMBTA13LT1 MMBTA14LT1
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
mined byT
of the die, R
, the maximum rated junction temperature
, the thermal resistance from the device
J(max)
θJA
junction to ambient, and the operating temperature, T .
A
Using the values provided on the data sheet for the SOT–23
package, P can be calculated as follows:
• Always preheat the device.
D
• The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T of 25°C,
A
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad . Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
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MMBTA13LT1 MMBTA14LT1
PACKAGE DIMENSIONS
SOT–23 (TO–236)
CASE 318–08
ISSUE AF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
INCHES
DIM MIN MAX
MILLIMETERS
S
C
B
MIN
2.80
1.20
0.89
0.37
1.78
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.69
1.02
2.64
0.60
1
2
A
B
C
D
G
H
J
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
V
G
0.0005 0.0040 0.013
0.0034 0.0070 0.085
K
L
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
0.35
0.89
2.10
0.45
S
V
H
J
D
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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MMBTA13LT1 MMBTA14LT1
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MMBTA13LT1/D
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