NB7NPQ7022M [ONSEMI]
3.3V USB 3.1 Dual Channel High Gain Linear Redriver;
| 型号： | NB7NPQ7022M |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V USB 3.1 Dual Channel High Gain Linear Redriver |
| 文件： | 总9页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7NPQ7022M
3.3 V USB 3.1 Dual Channel
High Gain Linear Redriver
Description
The NB7NPQ7022M is a 3.3 V dual channel, high gain, redriver for
USB 3.1 Gen 1 and USB 3.1 Gen 2 applications that supports both
5 Gbps and 10 Gbps data rates. Signal integrity degrades from PCB
traces, transmission cables, and inter−symbol interference (ISI). The
NB7NPQ7022M compensates for these losses by engaging varying
levels of equalization at the input receiver, and flat gain amplification
on the output transmitter. The Flat Gain and Equalization are
controlled by four level control pins. Each channel has a set of
independent control pins to make signal optimization possible.
After power up, periodic check of TX output is made for the receiver
connection. When the receiver is detected, the RX termination
becomes enabled and the device is set to perform the redriver function.
Note that both channels are independent of each other.
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1
UQFN16
CASE 523AF
The NB7NPQ7022M comes in a small 3 x 3 mm UQFN16 package
and is specified to operate across the entire industrial temperature
range of –40°C to 85°C.
Features
• 3.3 V ± 0.3 V Power Supply
MARKING DIAGRAM
NB7N
7022
ALYWG
G
• Low Power Consumption: 114 mA in Active Mode
• Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Termination Detection
• Integrated Input and Output Termination
• Independent, Selectable Equalization and Flat Gain
• Hot−Plug Capable
NB7N7022 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• Operating Temperature Range: −40°C to +85°C
• Small 3 x 3 x 0.5 mm UQFN16 Package, Flow Through Design for
Ease of PCB Layout
ORDERING INFORMATION
• This is a Pb−Free Device
Typical Applications
• USB3.1 Type−C and Type−A Signal Routing
• Mobile Phone and Tablet
• Computer, Laptop and Notebook
• External Storage Device
†
Device
NB7NPQ7022MMUTXG UQFN16 3000 / Tape
(Pb−Free) & Reel
Package
Shipping
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
July, 2018 − Rev. 0
NB7NPQ7022M/D
NB7NPQ7022M
CTRL_A0
CTRL_A1
Channel A Control Logic
A_RX−
A_RX+
B_TX−
B_TX+
A_TX−
Receiver/
Equalizer
Driver
A_TX +
B_RX−
Receiver/
Equalizer
Driver
B_RX+
Channel B Control Logic
CTRL_B0
CTRL_B1
Figure 1. Logic Diagram of NB7NPQ7022M
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2
NB7NPQ7022M
16 15 14 13
1
2
3
4
A_TX−
A_TX+
B_RX−
B_RX+
12
A_RX−
A_RX+
B_TX−
B_TX+
11
10
9
Exposed
Pad EP
5
6
7
8
Figure 2. UQFN16 Package Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin No. Pin Name
Type
Description
1
2
3
4
5
A_RX−
A_RX+
B_TX−
B_TX+
VCC
DIFF IN
Channel A Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
DIFF OUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
POWER
3.3 V power supply. VCC pins must be externally connected to power supply to guarantee proper oper-
ation.
6
7
8
CTRL_B0 LVCMOS IN Pin B0 for control of Flat Gain settings on Channel B having internal 100 kW pull up and 200 kW pull
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connect-
CC
ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
68 kW connected from pin to Ground. Refer Table 2 for the different settings.
CTRL_B1 LVCMOS IN Pin B1 for control of Equalization settings on Channel B having internal 100 kW pull up and 200 kW pull
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connect-
CC
ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
68 kW connected from pin to Ground. Refer Table 2 for the different settings.
GND
GND
Reference Ground. GND pins must be externally connected to power supply ground to guarantee
proper operation.
9
B_RX+
B_RX−
A_TX+
A_TX−
VCC
DIFF IN
Channel B Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC coupled.
10
11
12
13
Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC coupled.
DIFF OUT
POWER
3.3 V power supply. VCC pins must be externally connected to power supply to guarantee proper oper-
ation.
14
CTRL_A0 LVCMOS IN Pin A0 for control of Equalization settings on Channel A having internal 100 kW pull up and 200 kW pull
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connect-
CC
ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
68 kW connected from pin to Ground. Refer Table 2 for the different settings.
15
CTRL_A1 LVCMOS IN Pin A1 for Control of Flat Gain settings on Channel A having internal 100 kW pull up and 200 kW pull
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connect-
CC
ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
68 kW connected from pin to Ground. Refer Table 2 for the different settings.
16
GND
GND
GND
GND
Reference Ground. GND pins must be externally connected to power supply ground to guarantee
proper operation.
EP
Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The pad is not electrically connected to the die, but is recommended to be
soldered to GND on the PC Board.
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NB7NPQ7022M
Table 2. CONTROL PIN EFFECTS (Typical Values)
Channel A
Channel B
CTRL_A1 (FGA) CTRL_A0 (EQA)
CRTL_B1 (EQB)
CRTL_B0 (FGB)
Setting #
EQ (dB)
10.9
6.7
FG (dB)
1
L
L
L
R
F
H
L
L
R
F
H
L
L
L
−3
−3
−3
−3
−1.5
−1.5
−1.5
−1.5
0
2
3
L
L
8.9
4
L
L
13.1
10.9
6.7
5
R
R
R
R
F
F
F
F
H
H
H
H
R
R
R
R
F
F
F
F
H
H
H
H
6
R
F
H
L
R
F
H
L
7
8.9
8
13.1
10.9
6.7
9
10
R
F
H
L
R
F
H
L
0
11 (Default)
8.9
0
12
13
14
15
16
13.1
10.9
6.7
0
2
R
F
H
R
F
H
2
8.9
2
13.1
2
NOTE: EQ and FG can be set by adjusting the voltage to the control pins. There are 4 specific levels – HIGH “H” where pin is connected
to V , LOW “L” where pin is connected to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
CC
resistor 68 kW connected from pin to Ground. Please refer Table 7 for voltage levels.
Table 3. ATTRIBUTES
Parameter
ESD Protection
Human Body Model (all V Pins shorted together)
± 2 kV
± 1 kV
1.5 kV
CC
Human Body Model (V Pins not shorted together) (Note 1)
CC
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 2)
Level 1
UL 94 V−O @ 0.125 in
40517
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. ESD Human Body Model tested as per JEDEC standard JS−001−2017 (AEC−Q100−002)
2. For additional information, see Application Note AND8003/D.
Table 4. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 3)
V
CC
4.6
Voltage range at any input or output terminal
Differential I/O
V
V
+ 0.5
V
CC
CC
LVCMOS inputs
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.2
150
125
34
Storage Temperature Range, T
−65
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 4)
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. All voltage values are with respect to the GND terminals.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
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NB7NPQ7022M
Table 5. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
C
Main power supply
3.3
CC
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
°C
100
68
nF
kW
AC
Rext
External Resistor ± 5% for the control pin “R” setting
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. POWER SUPPLY CHARACTERISTICS
Parameter
Test Condition
100 MHz, test pattern
10 Gbps, compliance test pattern
Low Power Slumber mode current No input signal
Unplug mode current No output load is detected
5. Typ values use V = 3.3 V, T = 25°C.
Min
Typ (Note 5)
Max
Units
ICC
Active mode current
114
mA
0.51
0.24
mA
mA
CC
A
Table 7. LVCMOS CONTROL PIN CHARACTERISTICS 4−State LVCMOS Inputs (CTRL_A0, CTRL_A1, CTRL_B0, CTRL_B1)
Parameter
Test Conditions
Min
Typ
GND
Max
0.1 * V
Unit
V
V
IL
DC Input Setting “L” LOW
DC Input Setting “R” with Rext
Input pin connected to GND
CC
V
IR
Rext (typ 68kW) must be connected be- 0.23 * V
tween Pin and GND, [Logic 1/3 * V
0.33 * V
0.43 * V
V
CC
CC
CC
CC
CC
]
CC
V
IF
DC Input Setting “F” FLOAT
(Note 6)
Input pin is left FLOAT (open),
0.56 * V
0.92 * V
0.66 * V
0.76 * V
V
CC
CC
[Logic 2/3 * V
]
CC
V
DC Input Setting “H” HIGH
Internal pull up resistance
Internal pull down resistance
High level input current
Low level input current
Input pin connected to V
V
CC
V
IH
PU
PD
IH
CC
R
R
100
200
kW
kW
mA
mA
I
V
V
= 3.60 V
25
IN
I
IL
= GND, VCC = 3.60 V
−45
IN
6. FLOAT refers to a pin left in an open state, with no external connections.
Table 8. RECEIVER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Input differential voltage swing
AC−coupled, peak−to−peak differential
100
1200
mV
PP
RX−DIFF−pp
V
Common−mode voltage bias in
the receiver (DC)
V
CC
V
RX−CM
Z
Differential input Resistance (DC) Present after an USB device is detect-
80
20
100
25
120
30
W
RX−DIFF
ed on TX+/TX−
Z
Common−mode input Resistance Present after an USB device is detect-
W
RX−CM
(DC)
ed on TX+/TX−
Z
Common−mode input Resistance Present when no USB device is detect-
25
kW
RX−HIGH−IMP
with termination disabled (DC)
ed on TX+
V
Low Frequency Periodic Signaling Output voltage is considered squelched
(LFPS) Detect Threshold below 25 mV.
100
200
300
mV
PP
TH−LFPS−pp
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NB7NPQ7022M
Table 9. TRANSMITTER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
−1 dB compression point Output 100 MHz Sine Wave
swing at 100 MHz
900
mV
sw_100M
PPd
V
sw_5G
−1 dB compression point Output 5 GHz Sine Wave
swing at 5 GHz
900
mV
PPd
C
TX input capacitance to GND
At 2.5 GHz
1.25
100
pF
TX
Z
Differential output impedance
(DC)
Present after an USB device is detected
on TX+/TX−
80
20
120
30
W
TX−DIFF
Z
Common−mode output im-
pedance (DC)
Present after an USB device is detected
on TX+/TX−
25
90
W
TX−CM
I
TX short circuit current
TX+ or TX− shorted to GND
mA
V
TX−SC
V
Common−mode voltage bias in
the transmitter (DC)
100 mV, 50 MHz, 5 Gbps and 10 Gbps,
PRBS 2^7
V
− 0.8 VCC
TX−CM
CC
V
AC common−mode peak−to−peak Within U0 and at 50 MHz (LFPS)
100
10
mV
TX−CM−ACpp
PP
Voltage swing in active mode
V
Differential voltage swing during
electrical idle
Tested with a high−pass filter
0
mV
TX−IDLE−DIFF−ACpp
PP
V
Voltage change to allow receiver The change in voltage that triggers de-
325
35
600
mV
TX−RXDET
detect
tection of a receiver.
t , t
Output rise, fall time
20% − 80% of differential voltage mea-
sured 1 inch from the output pin, 1 GHz
clock, 800 mV differential amplitude
ps
R
F
t
Output rise, Fall time mismatch
Differential propagation delay
Idle exit time
20% − 80% of differential voltage mea-
5
ps
ps
ns
ns
RF−MM
sured 1 inch from the output pin
t
, t
Propagation delay between 50% level at
input and output
90
5
diff−LH diff−HL
t
50 MHz clock signal, EQ an FG setting
“FF (Default)”
idleExit
t
Idle entry time
50 MHz clock signal, EQ an FG setting
“FF (Default)”
20
idleEntry
Table 10. TIMING AND JITTER CHARACTERISTICS
Parameter
TIMING
Test Conditions
Min
Typ
Max
Unit
t
Time from power applied until RX Apply 0 V to V , connect USB termina-
100
ms
READY
CC
termination is enabled
tion to TX ± , apply 3.3 V to V , and mea-
CC
sure when Z
is enabled
RX−DIFF
JITTER FOR 5 Gbps
T
Total jitter (Notes 7, 8)
FG and EQ setting “FF”
0.035
UI
(Note 9)
JTX−EYE
D
R
Deterministic jitter (Note 8)
Random jitter (Note 8)
0.003
0.005
UI
UI
JTX
JTX
JITTER FOR 10 Gbps
T
Total jitter (Notes 7, 8)
FG and EQ setting “FF”
0.085
UI
(Note 9)
JTX−EYE
D
R
Deterministic jitter (Note 8)
Random jitter (Note 8)
0.040
0.007
UI
UI
JTX
JTX
−12
7. Includes RJ at 10
.
8. Measured at the ends of reference channel with a K28.5 pattern, VID = 1000 mVpp, −3.5 dB de−emphasis from source.
9. 5 Gbps, UI = 200 ps for 10 Gbps, UI = 100 ps Test condition
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NB7NPQ7022M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
VOH
VOL
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
t
R
t
F
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
APPLICATION GUIDELINES
LFPS Compliance Testing
bias (with an internal pull up resistor of 100 kW and pull down
resistor of 200 kW) the control pins to the correct voltage
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ7022M is tested as a part of a USB
compliant system to ensure that it maintains compliance
while increasing system performance.
(Logic 2/3 * V ). The low setting “L” can be set by pulling
CC
the control pin to ground. The high setting “H” can be set by
pulling the pin high to VCC. The R setting can be set by
ext
adding a 68 kW resistor from the control pin to ground. This
will bias the redriver internal voltage to Logic 1/3 * V
.
CC
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling (LFPS) to implement functions like exiting
low−power modes, performing warm resets and providing
link training between host and peripheral devices. LFPS
signaling consists of bursts of frequencies ranging between
10 to 50 MHz and can have specific burst lengths or repeat
rates.
Linear Equalization
The linear equalization that the NB7NPQ7022M provides
compensates for losses that occur naturally along board
traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping. LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1130 mV using 3 dB of flat gain.
Control Pin Settings
Control pins CTRL_A1 & CTRL_B0 controls the flat gain
and CTRL_A0 & CTRL_B1 controls the equalization of
channels A and B respectively.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the Flat Gain.
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NB7NPQ7022M
TYPICAL APPLICATION
Upto 13 dB loss
Upto
3 dB loss
CTRL_A0
CTRL_A1
Channel A Control Logic
A_TX−
A _RX −
220 nF
220 nF
220 nF
220 nF
220 nF
220 nF
330 nF
330 nF
Receiver /
Equalizer
Driver
A _RX +
A _TX +
B _TX −
B _RX −
Receiver /
Driver
Equalizer
B _TX +
B _RX +
Channel B Control Logic
kW
220
CTRL_B0
CTRL_B1
kW
220
Figure 5. USB 3.1 Host Side NB7NPQ7022M Application
Table 11. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.0 V to 3.6 V)
Operation Mode (Control Pin Selection)
Default FLOAT “F”, adjust based on application losses. Refer Table 2 for different
EQ and FG setting.
TX AC Coupling Capacitors
RX AC Coupling Capacitors
220 nF nominal, 75 nF to 265 nF, see Figure 5
330 − 470 nF nominal, see Figure 5
R
68 kW ± ±5%
ext
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 kW to 220 kW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7022M
Trace loss of FR4 after NB7NPQ7022M
DC Flat Gain Options
Up to 13 dB losses
Up To 3 dB losses. Keep as short as possible for best performance.
−3 dB, −1.5 dB, 0 dB, 2 dB
6.7 to 13.1 dB
Equalization Options
Differential Trace Impedance
90 W ± ±10%
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
Differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• Traces should be routed as straight and symmetric as
possible.
• RX and TX differential pairs should always be placed
and routed on the same layer directly above a ground
plane. This will help reduce EMI and noise on the data
lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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NB7NPQ7022M
PACKAGE DIMENSIONS
UQFN16 3x3, 0.5P
CASE 523AF
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
B
E
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
PIN ONE
REFERENCE
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
MILLIMETERS
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.127 REF
0.20 0.30
3.00 BSC
2X
0.10
C
DETAIL B
OPTIONAL CONSTRUCTION
4X SCALE
2X
D
D2
E
E2
e
1.60
3.00 BSC
1.60
0.50 BSC
1.80
0.10
C
TOP VIEW
1.80
A
DETAIL B
K
L
0.20
0.30
−−−
0.50
0.05
0.05
C
C
A3
17X
SOLDERING FOOTPRINT*
A1
NOTE 4
SEATING
PLANE
C
SIDE VIEW
0.50
PITCH
D2
DETAIL A
5
K
16X
0.60
2X
1.55
e/2
e
2X
3.30
9
E2
1
1
16X
0.29
13
16X L
16X
b
DIMENSIONS: MILLIMETERS
0.10
0.05
C
C
A
B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
BOTTOM VIEW
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