NBSG16MMNG [ONSEMI]
2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer; 2.5 V / 3.3 V ？多级输入到CML时钟/数据接收器/驱动器/转换器缓冲
| 型号： | NBSG16MMNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer |
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG16M
2.5 V/3.3 VꢀMultilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
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Description
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
MARKING
DIAGRAM*
16
1
Inputs incorporate internal 50 W termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
1
SG
16M
ALYW G
G
QFN−16
MN SUFFIX
CASE 485G
internal 50 W source termination resistor to V . The device
CC
generates 400 mV output amplitude with 50 W receiver resistor to
V
.
CC
The V pin is internally generated voltage supply available to this
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
BB
device only. For all single−ended input conditions, the unused
complementary differential input is connected to V as a switching
BB
reference voltage. V may also rebias AC coupled inputs. When
BB
used, decouple V via a 0.01 mF capacitor and limit current sourcing
BB
(Note: Microdot may be in either location)
or sinking to 0.5 mA. When not used, V output should be left open.
BB
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Maximum Input Clock Frequency > 10 GHz Typical
• Maximum Input Data Rate > 10 Gb/s Typical
• 120 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• Positive CML Output with Operating Range:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
V
CC
= 2.375 V to 3.465 V with V = 0 V
EE
• Negative CML Output with RSNECL or NECL Inputs with
Operating Range: V = 0 V with V = −2.375 V to −3.465 V
CC
EE
• CML Output Level; 400 mV Peak−to−Peak Output with
50 W Receiver Resistor to V
CC
• 50 W Internal Input and Output Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
• V Reference Voltage Output
BB
• Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 5
NBSG16M/D
NBSG16M
V
CC
V
BB
V
EE
V
EE
Exposed Pad (EP)
16
15
14
13
VTD
D
V
CC
1
2
3
4
12
11
10
9
Q
Q
V
NBSG16M
D
VTD
CC
5
6
7
8
V
CC
NC
V
V
EE
EE
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
Internal 50 W Termination Pin. See Table 2. (Note 3)
1
2
V
−
TD
D
LVDS, CML, ECL, LVTTL, Inverted Differential Input (Note 3)
LVCMOS Input
3
D
LVDS, CML, ECL, LVTTL, Noninverted Differential Input. (Note 3)
LVCMOS Input
4
5
V
−
−
Internal 50 W Termination Pin. See Table 2. (Note 3)
TD
V
CC
Positive Supply Voltage. All V pins must be externally connected to Power Supply to guar-
CC
antee proper operation.
6
7
NC
−
−
No Connect (Note 1)
V
Negative Supply Voltage. All V pins must be externally connected to Power Supply to guar-
antee proper operation.
EE
EE
CC
EE
8
9
V
−
−
Negative Supply Voltage. All V pins must be externally connected to Power Supply to guar-
antee proper operation.
EE
V
Positive Supply Voltage. All V pins must be externally connected to Power Supply to guar-
antee proper operation.
CC
10
11
12
Q
Q
CML Output
CML Output
−
Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
V
CC
Positive Supply Voltage. All V pins must be externally connected to Power Supply to guar-
CC
antee proper operation.
13
14
V
−
−
Negative Supply Voltage. All V pins must be externally connected to Power Supply to guar-
EE
EE
antee proper operation.
V
EE
Negative Supply Voltage. All V pins must be externally connected to Power Supply to guar-
EE
antee proper operation.
15
16
V
−
−
Internally Generated ECL Reference Output Voltage
BB
CC
V
Positive Supply Voltage. All V pins must be externally connected to Power Supply to guar-
CC
antee proper operation.
−
EP
−
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must
be attached to a heat−sinking conduit.
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50 W receiver termination resistor to V for proper operation.
CC
3. In the differential configuration when the input termination pin (V , V ) are connected to a common termination voltage, and if no signal
TD TD
is applied then the device will be susceptible to self−oscillation.
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2
NBSG16M
V
CC
V
CC
VTD
50 W
50 W
50 W
50 W
50 W
50 W
Q
Q
D
D
Q
Q
VTD
V
BB
16 mA
V
EE
V
EE
Figure 2. Logic Diagram
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
LVDS
Connect VTD and VTD to V
CC
Connect VTD and VTD together
AC−COUPLED
Bias VTD and VTD Inputs within (V
)
IHCMR
Common Mode Range
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL Termination Techniques
An external voltage should be applied to the
unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V /2 for
CC
LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 100 V
> 4 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 4)
QFN−16
Oxygen Index: 28 to 34
Pb Pkg
Level 1
Pb−Free Pkg
Level 1
Flammability Rating
Transistor Count
UL 94 V−0 @ 0.125 in
145
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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3
NBSG16M
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
3.6
Unit
V
V
CC
V
EE
V
I
Positive Power Supply
Negative Power Supply
V
V
EE
= 0 V
−3.6
V
CC
Positive Input
Negative Input
V
EE
V
CC
= 0 V
= 0 V
V v V
3.6
−3.6
V
V
I
I
CC
EE
V w V
V
INPP
Differential Input Voltage |D − D|
V
CC
V
CC
− V w 2.8 V
2.8
CC
V
EE
− V < 2.8 V
|V − V
|
EE
EE
I
I
I
Input Current Through R (50 W Resistor)
Static
Surge
45
80
mA
mA
IN
T
Output Current
Continuous
Surge
25
50
mA
mA
out
BB
V
BB
Sink/Source
1.0
mA
°C
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
A
T
−65 to +150
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
1S2P (Note 5)
QFN−16
4.0
°C/W
°C
JC
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
265
265
Pb−Free <2 to 3 sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power)
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4
NBSG16M
Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT V = 2.5 V; V = 0 V (Note 6)
CC
EE
−40°C
Typ
43
25°C
Typ
43
85°C
Typ
43
Min
Max
51
Min
Max
Min
Max
Symbol
Characteristic
Positive Power Supply Current
Output HIGH Voltage (Note 7)
Unit
mA
mV
I
37
37
51
37
51
CC
V
OH
V
CC
40
−
V
CC
10
−
V
CC
V
CC
40
−
V
CC
10
−
V
CC
V
CC
40
−
V
CC
10
−
V
CC
V
V
V
Output LOW Voltage (Note 6)
V
−
V
−
V
−
V
−
V
−
V −
CC
mV
V
OL
IH
IL
CC
CC
CC
CC
CC
400
330
400
330
400
330
Input HIGH Voltage
(Single−Ended) (Note 8)
V
+
V
−
V
V
+
V
−
V
V
+
V
−
V
CC
EE
CC
CC
EE
CC
CC
EE
CC
1.275
1.0*
1.275
1.0*
1..275
1.0*
Input LOW Voltage
(Single−Ended) (Note 8)
V
V
−
V
−
V
V
−
V
−
V
V
−
V −
IH
V
EE
CC
IH
EE
CC
IH
EE
CC
1.4*
0.150
1265
2.5
1.4*
0.150
1265
2.5
1.4*
0.150
1265
2.5
V
V
ECL Reference Voltage Output
1075
1.2
1170
1075
1.2
1170
1075
1.2
1170
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 8)
(Differential Configuration)
IHCMR
R
R
Internal Input Termination Resistor
45
45
50
50
55
55
45
45
50
50
55
55
45
45
50
50
55
55
W
W
TIN
Internal Output Termination
Resistor
TOUT
I
I
Input HIGH Current (@ V
)
60
25
100
50
60
25
100
50
60
25
100
50
mA
mA
IH
IH
Input LOW Current (@ V )
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −0.965 V.
CC
EE
7. All loading with 50 W to V
.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differen-
IHCMR
EE IHCMR
CC
IHCMR
tial input signal.
*Typicals used for testing purposes.
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NBSG16M
Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT V = 3.3 V; V = 0 V (Note 9)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
51
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
mA
mV
I
Positive Power Supply Current
Output HIGH Voltage (Note 10)
37
43
37
43
51
37
43
51
CC
V
V
V
V
V
CC
40
−
V
V
−
−
V
CC
V
CC
40
−
V
CC
10
−
V
CC
V
CC
40
−
V
CC
10
−
V
CC
OH
OL
IH
CC
10
Output LOW Voltage (Note 9)
V
−
V
−
V
−
V
−
V −
CC
330
mV
V
CC
400
CC
CC
CC
CC
330
400
330
400
Input HIGH Voltage
(Single−Ended) (Note 11)
V
+
V
−
V
CC
V
+
V
−
V
CC
V
+
V
−
V
CC
EE
CC
EE
CC
EE
CC
1.275
1.0*
1.275
1.0*
1.275
1.0*
Input LOW Voltage
(Single−Ended) (Note 11)
V
EE
V
−
V
IH
−
V
EE
V
−
V
IH
−
V
EE
V
−
V −
IH
V
IL
CC
CC
CC
1.4*
0.150
2065
3.3
1.4*
0.150
2065
3.3
1.4*
0.150
2065
3.3
V
V
ECL Reference Voltage Output
1875
1.2
1970
1875
1.2
1970
1875
1.2
1970
mV
V
BB
Input HIGH Voltage Common
Mode Range (Note 11)
(Differential Configuration)
IHCMR
R
R
Internal Input Termination Resistor
45
45
50
50
55
55
45
45
50
50
55
55
45
45
50
50
55
55
W
W
TIN
Internal Output Termination
Resistor
TOUT
I
I
Input HIGH Current (@ V
)
60
25
100
50
60
25
100
50
60
25
100
50
mA
mA
IH
IH
Input LOW Current (@ V )
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with V . V can vary +0.925 V to −0.165 V.
CC
EE
10.All loading with 50 W to V
.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differen-
IHCMR
EE IHCMR
CC
IHCMR
tial input signal.
*Typicals used for testing purposes.
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NBSG16M
Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT V = 0 V; V = −3.465 to −2.375 V (Note 12)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
51
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
I
Positive Power Supply Current
37
43
37
43
51
37
43
51
mA
CC
V
V
V
V
Output HIGH Voltage (Note 13)
V
−
V
V
−
−
V
V
−
V
−
V
V
−
V
−
V
CC
mV
mV
V
OH
OL
IH
CC
CC
CC
CC
CC
CC
CC
CC
40
10
40
10
40
10
Output LOW Voltage (Note 12)
V
−
V
−
V
−
V
−
V
−
CC
400
CC
CC
CC
CC
CC
330
400
330
400
330
Input HIGH Voltage
(Single−Ended) (Note 13)
V
1.275
+
V
−
V
CC
V
1.275
+
V
−
V
CC
V
1.275
+
V
−
V
CC
EE
CC
EE
CC
EE
CC
1.0*
1.0*
1.0*
Input LOW Voltage
(Single−Ended) (Note 13)
V
V
−
V
−
V
V
−
V
−
V
V
−
V −
IH
0.150
V
IL
EE
CC
IH
EE
CC
IH
EE
CC
1.4*
0.150
1.4*
0.150
1.4*
V
V
ECL Reference Voltage Output
−1425 −1330 −1235 −1425 −1330 −1235 −1425 −1330 −1235 mV
BB
Input HIGH Voltage Common
Mode Range (Note 14)
(Differential Configuration)
V
EE
+1.2
V
CC
V
EE
+1.2
V
CC
V
EE
+1.2
V
CC
V
IHCMR
R
R
Internal Input Termination Resistor
45
45
50
55
45
45
50
55
45
45
50
55
W
W
TIN
Internal Output Termination
Resistor
50
55
50
55
50
55
TOUT
I
I
Input HIGH Current (@ V
)
60
25
100
50
60
25
100
50
60
25
100
50
mA
mA
IH
IH
Input LOW Current (@ V )
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12.Input and output parameters vary 1:1 with V
.
CC
13.All loading with 50 W to V
.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differen-
IHCMR
EE IHCMR
CC
IHCMR
tial input signal.
*Typicals used for testing purposes.
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NBSG16M
Table 8. AC CHARACTERISTICS V = 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
CC
EE
CC
EE
−40°C
Min Typ
< 7 GHz 300 400
in
25°C
85°C
Max Min Typ
Max Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figure 4) (Note 15)
f
300 400
200 250
300
100
400
150
mV
OUTPP
f
< 10 GHz 200 250
in
t
t
,
Propagation Delay to
Output Differential
90
110
150
15
1
100 120
150
15
1
100
125
155
15
ps
PLH
PHL
t
t
Duty Cycle Skew (Note 16)
3
3
3
ps
ps
SKEW
RMS Random Clock Jitter (Note 18)
JITTER
f
< 10 GHz
0.2
8
0.2
0.2
8
1.0
15
in
Peak−to−Peak Data Dependent Jitter (Note 19)
f
in
< 10 Gb/s
15
8
15
V
Input Voltage Swing/Sensitivity
75
2500
75
2500
75
21
2500 mV
INPP
(Differential Configuration) (Note 17)
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
Q, Q 21
35
53
21
35
53
35
53 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
15.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V . Input edge rates 40 ps (20% − 80%).
CC
16.See Figure 8 t
= |t
− t
| for a nominal 50% differential clock input waveform.
skew
PLH
PHL
17.V
cannot exceed V − V . (Applicable only when V − V < 2500 mV). Input voltage swing is a single−ended measurement
INPP(max)
operating in differential mode.
18.Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
19.Additive Peak−to−Peak data dependent jitter with NRZ PRBS2 −1 data rate at 10 Gb/s.
CC EE CC EE
31
500
V
CC
− V = 3.3 V
EE
450
400
350
300
250
200
150
100
50
V
CC
− V = 2.5 V
EE
0
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
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NBSG16M
Application Information
All inputs can accept PECL, CML, and LVDS signal
levels. The input voltage can range from V to 1.2 V.
Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W).
CC
V
CC
V
CC
50 W 50 W
Q
D
Z
Z
50 W
50 W
SG16M
V
V
TD
SG16M
V
V
CC
Q
D
CC
TD
V
EE
V
EE
Figure 5. CML to CML Interface
V
CC
V
CC
50 W
D
Z
50 W
50 W
V
TD
V
PECL
Driver
Bias
SG16M
50 W
Z
D
R
T
R
T
Recommended R Values
T
V
Bias
V
TD
V
CC
R
T
5.0 V 290 W
V
EE
V
EE
V
EE
3.3 V 150 W
2.5 V 80 W
Figure 7. PECL to CML Receiver Interface
V
CC
V
CC
D
Z
50 W
50 W
V
TD
LVDS
Driver
SG16M
Z
D
V
TD
V
EE
V
EE
Figure 6. LVDS to CML Receiver Interface
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NBSG16M
D
V
V
(D) = V (D) − D (D)
IH IL
INPP
INPP
(D) = V (D) − D (D)
IH
IL
D
Q
V
V
(Q) = V (Q) − V (Q)
OH OL
OUTPP
OUTPP
(Q) = V (Q) − V (Q)
OH
OL
Q
t
PHL
t
PLH
Figure 8. AC Reference Measurement
V
CC
50 W
50 W
Z = 50 W
o
Q
D
D
Receiver
Device
Driver
Device
Z = 50 W
o
Q
Figure 9. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
ORDERING INFORMATION
†
Device
NBSG16MMN
Package
Shipping
QFN−16
123 Units / Rail
123 Units / Rail
NBSG16MMNG
QFN−16
(Pb−Free)
NBSG16MMNR2
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
NBSG16MMNR2G
QFN−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NBSG16M
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN 1
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
LOCATION
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
E2 1.65
1.85
0.10
0.08
C
C
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
SOLDERING FOOTPRINT*
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
e
L
16X
0.012
EXPOSED PAD
5
8
NOTE 5
4
9
E2
e
1.50
0.059
K
16X
3.25
0.128
12
1
16
13
16X b
0.30
0.012
0.10
0.05
C
C
A
B
BOTTOM VIEW
0.50
0.02
NOTE 3
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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