NBSG16MNR2 [ONSEMI]
2.5V/3.3V SiGe Differential Receiver/Driver with RSECLOutputs; 2.5V / 3.3V的SiGe差分接收器/驱动器RSECLOutputs
| 型号： | NBSG16MNR2 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V SiGe Differential Receiver/Driver with RSECLOutputs |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG16
2.5V/3.3VꢀSiGe Differential
Receiver/Driver with
RSECL* Outputs
*Reduced Swing ECL
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MARKING
The NBSG16 is a differential receiver/driver targeted for high
frequency applications. The device is functionally equivalent to the
EP16 and LVEP16 devices with much higher bandwidth and lower
EMI capabilities.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL,
LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing
ECL), 400 mV.
DIAGRAM*
SG
16
LYW
FCBGA-16
BA SUFFIX
CASE 489
The V and V
pins are internally generated voltage supplies
BB
MM
available to this device only. The V is used as a reference voltage
BB
for single-ended NECL or PECL inputs and the V
pin is used as a
MM
reference voltage for LVCMOS inputs. For all single-ended input
conditions, the unused complementary differential input is connected
SG16
ALYW
QFN-16
to V or V
as a switching reference voltage. V or V
may
MN SUFFIX
CASE 485G
BB
MM
BB
MM
also rebias AC coupled inputs. When used, decouple V and V
BB
MM
via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V and V outputs should be left open.
A = Assembly Location
L = Wafer Lot
Y = Year
BB
MM
• Maximum Input Clock Frequency > 12 GHz Typical
• Maximum Input Data Rate > 12 Gb/s Typical
• 120 ps Typical Propagation Delay
W = Work Week
*For further details, refer to Application Note
AND8002/D
• 40 ps Typical Rise and Fall Times
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V
CC
with V = 0 V
EE
ORDERING INFORMATION
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V = 0 V with V = -2.375 V to -3.465 V
Device
Package
Shipping
CC
EE
• RSECL Output Level (400 mV Peak-to-Peak Output), Differential
NBSG16BA
4x4 mm
FCBGA-16
100 Units/Tray
Output Only
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
NBSG16BAR2
4x4 mm
FCBGA-16
500/Tape & Reel
NBSG16MN
3x3 mm
QFN-16
123 Units/Rail
• V and V
Reference Voltage Output
BB
MM
NBSG16MNR2
3x3 mm
QFN-16
3000/Tape & Reel
Board
Description
NBSG16BAEVB
NBSG16BA Evaluation Board
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
May, 2003 - Rev. 12
NBSG16/D
NBSG16
V
EE
V
BB
V
MM
V
EE
1
2
3
4
Exposed Pad (EP)
16
15
14
13
A
V
EE
NC
NC
V
EE
VTD
D
V
CC
1
2
3
4
12
11
10
9
D
D
VTD
VTD
V
Q
Q
CC
B
C
Q
Q
V
NBSG16
D
V
CC
VTD
CC
V
EE
V
BB
V
MM
V
EE
D
5
6
7
8
V
EE
NC NC
V
EE
Figure 1. BGA-16 Pinout (Top View)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
C2
QFN
Name
VTD
D
I/O
Description
1
2
-
Internal 50 W Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V and 36.5 kW to V
C1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
.
CC
EE
B1
B2
3
4
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Internal 75 kW to V
.
EE
VTD
-
-
Internal 50 W Termination Pin. See Table 2.
A1,D1,A4, 5,8,13,16
D4
V
EE
Negative Supply Voltage
A2,A3
B3,C3
B4
6,7
9,12
10
NC
-
No Connect
V
CC
-
Positive Supply Voltage
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50 W to
= V - 2 V
V
TT
CC
C4
D3
11
14
15
-
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W to V = V
- 2 V
TT
CC
V
MM
-
-
-
LVCMOS Reference Voltage Output. (V
ECL Reference Voltage Output
Exposed Pad. (Note 2)
- V )/2
CC EE
D2
V
BB
N/A
EP
1. The NC pins are electrically connected to the die and MUST be left open.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
CC
EE
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
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2
NBSG16
V
CC
VTD
V
MM
36.5 KW
50 W
D
D
Q
Q
75 kW
75 kW
50 W
VTD
V
BB
V
EE
Figure 3. Logic Diagram
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
LVDS
Connect VTD and VTD to V
CC
Connect VTD and VTD together
AC-COUPLED
Bias VTD and VTD Inputs within (V
Common Mode Range
)
IHCMR
RSECL, PECL, NECL
LVTTL
Standard ECL Termination Techniques
The external voltage should be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL.
LVCMOS
V
MM
should be connected to the unused
complementary differential input.
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3
NBSG16
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
36.5 kW
Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 1)
FCBGA-16
QFN-16
Level 3
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
3.6
Units
V
CC
V
EE
V
I
V
V
V
V
EE
Negative Power Supply
= 0 V
-3.6
CC
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V ꢀ V
3.6
V
V
EE
I
CC
V ꢁ V
-3.6
CC
I
EE
V
INPP
Differential Input Voltage
|D - D|
V
CC
V
CC
- V
- V
w
2.8 V
2.8 V
2.8
V
V
EE
EE
<
|V
- V
|
CC
EE
I
Output Current
Continuous
Surge
25
mA
mA
out
50
I
I
V
V
Sink/Source
Sink/Source
1
mA
mA
°C
BB
BB
1
MM
MM
T
Operating Temperature Range
Storage Temperature Range
-40 to +85
A
T
-65 to +150
°C
stg
q
Thermal Resistance (Junction-to-Ambient) 0 LFPM
16 FCBGA
16 FCBGA
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JA
(Note 3)
500 LFPM
0 LFPM
500 LFPM
16 QFN
q
Thermal Resistance (Junction-to-Case)
Wave Solder
1S2P (Note 3)
2S2P (Note 4)
16 FCBGA
16 QFN
5
4.0
°C/W
°C/W
JC
T
sol
< 15 sec.
225
°C
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power)
4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NBSG16
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 2.5 V; V = 0 V (Note 5)
CC
EE
-40 °C
Typ
25°C
Typ
23
85°C
Typ
23
Min
17
Max
29
Min
17
Max
29
Min
17
Max
29
Symbol
Characteristic
Unit
mA
mV
mV
V
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 6)
Output Voltage Amplitude
23
V
V
V
1450
350
1530
410
1575
525
1525
350
1565
410
1600
525
1550
350
1590
410
1625
525
OH
OUTPP
IH
Input HIGH Voltage
V
+
V
CC
-
V
CC
V
+
V
CC
-
V
CC
V
+
V
CC
-
V
CC
THR
THR
THR
(Single-Ended) (Note 7)
75 mV
1.0*
75 mV
1.0*
75 mV
1.0*
V
Input LOW Voltage
(Single-Ended) (Note 7)
V
V
1.4*
-
V
-
V
V
1.4*
-
V
-
V
V
1.4*
-
V -
THR
V
IL
EE
CC
THR
EE
CC
THR
EE
CC
75 mV
1200
2.5
75 mV
1200
2.5
75 mV
1200
2.5
V
V
PECL Output Voltage Reference
1080
1.2
1140
1080
1.2
1140
1080
1.2
1140
mV
V
BB
Input HIGH Voltage Common
Mode Range (Note 8)
(Differential Configuration)
IHCMR
V
CMOS Output Voltage Reference
1100
45
1250
1400
1100
45
1250
1400
1100
45
1250
1400
mV
MM
V
CC
/2
R
Internal Input Termination Resistor
Input HIGH Current (@ V
50
30
25
55
100
50
50
30
25
55
100
50
50
30
25
55
100
50
W
TIN
I
IH
I
IL
)
IH
mA
mA
Input LOW Current (@ V )
IL
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with V . V can vary +0.125 V to -0.965 V.
CC
EE
6. All loading with 50 W to V -2.0 volts.
CC
7. V
8. V
is the voltage applied to the complementary input, typically V or V
.
THR
BB
MM
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
*Typicals used for testing purposes.
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 3.3 V; V = 0 V (Note 9)
CC
EE
-40 °C
Typ
25°C
Typ
23
85°C
Typ
23
Min
17
Max
29
Min
17
Max
29
Min
17
Max
29
Symbol
Characteristic
Unit
mA
mV
mV
V
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 10)
Output Voltage Amplitude
23
V
V
V
2250
350
2330
410
2375
525
2325
350
2365
410
2400
525
2350
350
2390
410
2425
525
OH
OUTPP
IH
Input HIGH Voltage
V
+
V
CC
-
V
CC
V
+
V
CC
-
V
CC
V
+
V
CC
-
V
CC
THR
THR
THR
(Single-Ended) (Note 11)
75 mV
1.0*
75 mV
1.0*
75 mV
1.0*
V
Input LOW Voltage
(Single-Ended) (Note 11)
V
V
1.4*
-
V
-
V
V
1.4*
-
V
-
V
V
1.4*
-
V -
THR
V
IL
EE
CC
THR
EE
CC
THR
EE
CC
75 mV
2000
3.3
75 mV
2000
3.3
75 mV
2000
3.3
V
V
PECL Output Voltage Reference
1880
1.2
1940
1880
1.2
1940
1880
1.2
1940
mV
V
BB
Input HIGH Voltage Common
Mode Range (Note 12)
(Differential Configuration)
IHCMR
V
CMOS Output Voltage Reference
1500
45
1650
1800
1500
45
1650
1800
1500
45
1650
1800
mV
MM
V
CC
/2
R
Internal Input Termination Resistor
Input HIGH Current (@ V
50
30
25
55
100
50
50
30
25
55
100
50
50
30
25
55
100
50
W
TIN
I
IH
I
IL
)
IH
mA
mA
Input LOW Current (@ V )
IL
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V . V can vary +0.925 V to -0.165 V.
CC
EE
10.All loading with 50 W to V - 2.0 V.
CC
11. V
12.V
is the voltage applied to the complementary input, typically V or V
.
THR
BB
MM
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
*Typicals used for testing purposes.
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NBSG16
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = -3.465 V to -2.375 V (Note 13)
EE
-40 °C
Typ
23
25°C
Typ
23
85°C
Typ
23
Min
17
Max
29
Min
17
Max
29
Min
17
Max
29
Symbol
Characteristic
Unit
mA
mV
mV
V
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 14)
Output Voltage Amplitude
VOH
-1050
350
-970
410
-925
525
-975
350
-935
410
-900
525
-950
350
-910
410
-875
525
V
OUTPP
IH
V
Input HIGH Voltage
(Single-Ended) (Note 15)
V
+
V
1.0*
-
-
V
CC
V
+
V
CC
-
V
CC
V
+
V
CC
-
V
CC
THR
75 mV
CC
THR
75 mV
THR
75 mV
1.0*
1.0*
V
IL
Input LOW Voltage
V
EE
V
CC
V
THR
-
V
EE
V
CC
-
V
THR
-
V
EE
V
CC
-
V -
THR
V
(Single-Ended) (Note 15)
1.4*
75 mV
-1300
0.0
1.4*
75 mV
-1300
0.0
1.4*
75 mV
-1300
0.0
V
V
NECL Output Voltage Reference
-1420
-1360
+1.2
-1420
-1360
+1.2
-1420
-1360
+1.2
mV
V
BB
Input HIGH Voltage Common
Mode Range (Note 16)
V
EE
V
EE
V
EE
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
(Note 17)
V
-150
V
MMT
V
+ 150
V
-150
V
MMT
V
+ 150
V
-150
V
MMT
V
MMT
+ 150
mV
MMT
MMT
MMT
MMT
MMT
R
TIN
Internal Input Termination Resis-
tor
45
50
55
45
50
55
45
50
55
W
I
I
Input HIGH Current (@ V
)
30
25
100
50
30
25
100
50
30
25
100
50
mA
mA
IH
IH
Input LOW Current (@ V )
IL
IL
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13.Input and output parameters vary 1:1 with V
.
CC
14.All loading with 50 W to V -2.0 volts.
CC
15.V
16.V
is the voltage applied to the complementary input, typically V or V
.
THR
BB
MM
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
17.V typical = |V
- V |/2 + V = V
MMT
MM
CC
EE
EE
*Typicals used for testing purposes.
Table 8. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V = -3.465 V to -2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
-40 °C
25°C
Typ
12
85°C
Typ
12
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.7
12
10.7
10.7
GHz
max
(See Figure 4. F /JITTER) (Note 18)
max
t
t
,
Propagation Delay to
Output Differential
90
110
3
130
15
1
100
120
3
140
15
1
105
125
3
145
15
1
ps
PLH
PHL
t
t
Duty Cycle Skew (Note 19)
RMS Random Clock Jitter
ps
ps
SKEW
JITTER
f
in
< 10 GHz
0.2
0.2
0.2
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
75
30
2600
75
75
20
2600
65
75
20
2600 mV
INPP
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% - 80%)
Q, Q
45
40
40
65
ps
18.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
- 2.0 V. Input edge rates 40 ps (20% - 80%).
CC
19.See Figure 6. t
= |t
- t
| for a nominal 50% differential clock input waveform.
skew
PLH
PHL
20.V
cannot exceed V - V
CC EE
INPP(max)
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NBSG16
Table 9. AC CHARACTERISTICS for QFN-16
V
CC
= 0 V; V = -3.465 V to -2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
-40 °C
25°C
Typ
12
85°C
Typ
12
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
(See Figure 4. F /JITTER) (Note 21)
Unit
f
10.7
12
10.7
10.7
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
90
110
3
130
100
120
3
140
95
125
3
145
ps
PLH
PHL
t
t
Duty Cycle Skew (Note 22)
RMS Random Clock Jitter
15
2
15
2
15
2
ps
ps
SKEW
JITTER
f
in
< 10 GHz
0.2
0.2
0.2
Peak-to-Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 23)
75
20
2600
50
75
20
2600
50
75
20
2600 mV
INPP
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% - 80%)
Q, Q
30
30
30
50
ps
21.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
- 2.0 V. Input edge rates 40 ps (20% - 80%).
CC
22.See Figure 6. t
= |t
- t
| for a nominal 50% differential clock input waveform.
skew
PLH
PHL
23.V
cannot exceed V - V
CC EE
INPP(max)
700
600
500
400
300
200
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
OUTPUT AMP
Q
Q
100
0
RMS JITTER
0.5
-0.5
1
2
3
4
5
6
7
8
9
10 11 12 13 14
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
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NBSG16
X = 17ps/Div Y = 70 mV/Div
Figure 5. 10.709 Gb/s Diagram (3.0 V, 255C)
D
V
INPP
= V (D) - V (D)
IH IL
D
Q
V
= V (Q) - V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 6. AC Reference Measurement
Q
D
Receiver
Device
Driver
Device
Q
D
50 W
50 W
V
TT
V
TT
= V
- 2.0 V
CC
Figure 7. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
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NBSG16
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
-X-
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
M
-Y-
K
E
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M-M
5
0.15
Z
A2
A
-Z-
16 X
A1
0.10
Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
http://onsemi.com
9
NBSG16
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-X-
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
M
-Y-
MILLIMETERS
DIM MIN MAX
3.00 BSC
3.00 BSC
0.80
INCHES
MIN MAX
A
B
C
D
E
F
0.118 BSC
0.118 BSC
B
1.00 0.031
0.039
0.011
0.073
0.073
0.23
1.75
1.75
0.28 0.009
1.85 0.069
1.85 0.069
N
G
H
J
0.50 BSC
0.875 0.925
0.20 REF
0.020 BSC
0.034
0.036
0.25 (0.010) T
0.25 (0.010) T
0.008 REF
K
L
0.00
0.35
0.05 0.000
0.45 0.014
0.002
0.018
M
N
P
R
1.50 BSC
1.50 BSC
0.875 0.925
0.60 0.80 0.024
0.059 BSC
0.059 BSC
0.034
0.036
0.031
J
R
C
SEATING
PLANE
-T-
0.08 (0.003) T
K
E
H
G
L
5
8
4
9
F
12
1
16
13
P
D NOTE 3
M
0.10 (0.004)
T
X Y
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