NCID9210R2 [ONSEMI]
High Speed Dual-Channel, Bi-Directional Ceramic Digital Isolator;
| 型号： | NCID9210R2 |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Dual-Channel, Bi-Directional Ceramic Digital Isolator |
| 文件： | 总12页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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High Speed Dual-Channel,
Bi-Directional Ceramic
Digital Isolator
NCID9210 / NCID9216
SOIC16 W
CASE 751EN
Description
The NCID9210 and NCID9216 are galvanically isolated full
duplex, bi−directional, high−speed dual−channel digital isolators.
These devices support isolated communications thereby allowing
digital signals to communicate between systems without conducting
ground loops or hazardous voltages.
MARKING DIAGRAM
They utilize onsemi’s patented galvanic off−chip capacitor isolation
technology and optimized IC design to achieve high insulation and
high noise immunity, characterized by high common mode rejection
and power supply rejection specifications. The thick ceramic substrate
yields capacitors with ~25 times the thickness of thin film on−chip
capacitors and coreless transformers. The result is a combination of
the electrical performance benefits that digital isolators offer with the
safety reliability of a >0.5 mm insulator barrier similar to what has
historically been offered by optocouplers.
AWLYWW
9210
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
9210/9216 = Specific Device Code
Y
The device is housed in a 16−pin wide body small outline package.
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
• Off−Chip Capacitive Isolation to Achieve Reliable High Voltage
Insulation
♦ DTI (Distance Through Insulation): ≥ 0.5 mm
♦ Maximum Working Insulation Voltage: 2000 V
• Full Duplex, Bi−directional Communication
• 100 KV/ms Minimum Common Mode Rejection
peak
• High Speed:
♦ 50 Mbit/s Data Rate (NRZ)
♦ 25 ns Maximum Propagation Delay
♦ 10 ns Maximum Pulse Width Distortion
• 8 mm Creepage and Clearance Distance to Achieve Reliable High
Voltage Insulation.
• Specifications Guaranteed Over 2.5 V to 5.5 V Supply Voltage and
−40°C to 125°C Extended Temperature Range
• Over Temperature Detection
• NCIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable (Pending)
• Safety and Regulatory Approvals
♦ UL1577, 5000 V
for 1 Minute
RMS
♦ DIN EN/IEC 60747−17 (Pending)
Typical Applications
• Isolated PWM Control
• Programmable Logic Control
• Isolated Data Acquisition System
• Voltage Level Translator
• Industrial Fieldbus Communications
2
• Microprocessor System Interface (SPI, I C, etc.)
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
NCID9210/D
September, 2021 − Rev. 1
NCID9210 / NCID9216
PIN CONFIGURATION
NCID9210
NCID9216
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
16
15
GND 1
NC
GND 2
NC
GND 1
NC
GND 2
NC
VDD1
VINA
VOB
14 VDD2
13 VOA
VDD1
VOA
14 VDD2
13 VINA
12
VINB
12
VINB
NC
VOB
11
NC
NC
11
NC
GND 1
NC
10
9
NC
GND 1
NC
10
9
NC
GND 2
GND 2
Figure 1. Pin and Channel Configuration
BLOCK DIAGRAM
GND1
NC
GND2
NC
TX
RX
VDD1
IOA
VDD2
IOA
IO
SWITCH
IO
SWITCH
IOB
IOB
NC
NC
RX
TX
GND1
NC
NC
GND2
Figure 2. Functional Block Diagram
PIN DEFINITIONS
Name
GND1
NC
Pin No. NCID9210 Pin No. NCID9216
Description
1
2
1
2
Ground, Primary Side
No Connect
V
3
3
Power Supply, Primary Side
Output, Channel A
Input, Channel B
No Connect
DD1
V
4
13
12
6
OA
V
5
INB
NC
GND1
NC
6
7
7
Ground, Primary Side
No Connect
8
8
GND2
NC
9
9
Ground, Secondary Side
No Connect
10
11
12
13
14
15
16
10
11
5
NC
No Connect
V
Output, Channel B
Input, Channel A
Power Supply, Secondary Side
No Connect
OB
INA
DD2
V
4
V
14
15
16
NC
GND2
Ground, Secondary Side
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2
NCID9210 / NCID9216
TRUTH TABLE (Note 1)
V
INX
V
DDI
V
DDO
V
OX
Comment
H
Power Up
Power Up
Power Up
Power Up
H
Normal Operation
Normal Operation
L
X
X
L
L
Power Down
Power Up
Power Up
Default low; V return to normal operation when V
change to Power Up
OX
DDI
Power Down
Undetermined
(Note 2)
V
OX
return to normal operation when V
change to Power Up
DDO
1. V
V
= Input signal of a given channel (A or B). V = Output signal of a given channel (A or B). V
= Input−side V . V
= Output−side
INX
DD
OX
DDI
DD DDO
. X = Irrelevant. H = High level. L = Low level.
2. The outputs are in undetermined state when V
< V
.
DDO
UVLO
SAFETY AND INSULATION RATINGS
As per DIN EN/IEC 60747−17, this digital isolator is suitable for “safe electrical insulation” only within the safety limit data. Compliance with
the safety ratings must be ensured by means of protective circuits.
Symbol
Parameter
Min
Typ
I–IV
Max
Units
Installation Classifications per DIN VDE 0110/1.89 Table 1
Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
I–IV
I–IV
I–IV
< 1000 V
I–III
RMS
Climatic Classification
40/125/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
CTI
600
V
PR
Input−to−Output Test Voltage, Method b, V
x 1.875 = V , 100% Production
3750
V
V
IORM
PR
peak
Test with t = 1 s, Partial Discharge < 5 pC
m
Input−to−Output Test Voltage, Method a, V
x 1.6 = V , Type and Sample
3200
IORM
PR
peak
Test with t = 10 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
2000
8000
8.0
V
V
IORM
peak
V
IOTM
peak
E
mm
mm
mm
°C
CR
E
External Clearance
8.0
CL
DTI
Insulation Thickness
0.50
150
100
600
T
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
Case
P
mW
mW
Ω
S,INPUT
P
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
IO
IO
10
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Value
Units
T
Storage Temperature
Operating Temperature
Junction Temperature
−55 to +150
−40 to +125
−40 to +150
260 for 10sec
−0.5 to 6
−0.5 to 6
15
°C
°C
°C
°C
V
STG
OPR
T
T
J
T
Lead Solder Temperature (Refer to Reflow Temperature Profile)
Supply Voltage (V
SOL
V
)
DDx
DD
V
Voltage (V , V
)
V
INx
Ox
I
O
Average Output Current
Power Dissipation
mA
mW
PD
210
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCID9210 / NCID9216
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Ambient Operating Temperature
Min
−40
2.5
0.7 x V
0
Max
+125
5.5
Unit
°C
V
T
A
V
V
Supply Voltage (Notes 3, 4)
High Level Input Voltage
DD1 DD2
V
INH
V
DDI
V
DDI
V
INL
Low Level Input Voltage
0.1 x V
V
DDI
V
V
Supply Voltage UVLO Rising Threshold
Supply Voltage UVLO Falling Threshold
Supply Voltage UVLO Hysteresis
High Level Output Current
Low Level Output Current
2.2
2.0
0.1
−2
V
UVLO+
V
UVLO−
UVLO
V
HYS
I
−
mA
mA
Mbps
OH
I
OL
−
2
DR
Signaling Rate
0
50
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. During power up or down, ensure that both the input and output supply voltages reach the proper recommended operating voltages to avoid
any momentary instability at the output state.
4. For reliable operation at recommended operating conditions, V supply pins require at least a pair of external bypass capacitors, placed
DD
within 2 mm from V pins 3 and 14 and GND pins 1 and 16. Recommended values are 0.1 mF and 1 mF.
DD
ISOLATION CHARACTERISTICS
Apply over all recommended conditions. All typical values are measured at T = 25°C.
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
Input−Output Isolation Voltage
T = 25°C, Relative Humidity < 50%,
5000
V
RMS
ISO
A
t = 1.0 minute, I
v 10 mA, 50 Hz (Notes 5, 6, 7)
I−O
11
R
C
Isolation Resistance
Isolation Capacitance
V
I−O
V
I−O
= 500 V (Note 5)
10
ISO
ISO
= 0 V, Frequency = 1.0 MHz (Note 5)
1
pF
5. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
6. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
7. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN EN/IEC 60747−17 Safety and Insulation
Ratings Table on page 3.
ELECTRICAL CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C, V
= V
= 2.5 V to 5.5 V, unless otherwise specified. All typical values
A
DD1
DD2
are measured at T = 25°C.
A
Symbol
Parameter
Conditions
= –4 mA
Min Typ
– 0.4 V – 0.1
DDO
Max
Units Figure
V
OH
High Level Output Voltage
Low Level Output Voltage
Rising Input Voltage Threshold
Falling Input Voltage Threshold
Input Threshold Voltage Hysteresis
High Level Input Current
I
I
V
DDO
V
V
7
8
OH
V
OL
= 4 mA
0.11
0.4
OL
V
INT+
0.7 x V
V
DDI
V
INT−
0.1 x V
0.1 x V
V
DDI
V
0.2 x V
V
INT(HYS)
DDI
DDI
I
V
V
= V
DDI
1
mA
mA
kV/ms
pF
INH
IH
I
Low Level Input Current
= 0 V
−1
INL
IL
CMTI
Common Mode Transient Immunity V = V
or 0 V, V = 1500 V
100
150
2
10
I
DDI
CM
C
Input Capacitance
V
= V /2 + 0.4 x sin (2pft),
IN
IN DDI
f = 1 MHz, V = 5 V
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NCID9210 / NCID9216
SUPPLY CURRENT CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C unless otherwise specified. All typical values are measured at T = 25°C.
A
A
Symbol
Parameter
Conditions
= 5 V, V = 0 V
Min
Typ
4.5
Max
Units Figure
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DC Supply Current
Input Low
V
6.3
mA
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD
DD
DD
DD
DD
DD
DD
IN
5.0
V
V
V
V
V
= 3.3 V, V = 0 V
4.4
6.1
6
IN
4.9
= 2.5 V, V = 0 V
4.3
IN
4.8
DC Supply Current
Input High
= 5 V, V = 5 V
11.8
12.1
11.7
11.9
11.6
11.8
8.3
14.5
14.3
14.3
10.5
10.3
10.1
12
mA
IN
= 3.3 V, V = 3.3 V
IN
= 2.5 V, V = 2.5 V
IN
AC Supply Current
1 Mbps
V
V
= 5 V, C = 15 pF
mA
mA
mA
3,4
L
= 5 V Square Wave
IN
8.7
V
V
= 3.3 V, C = 15 pF
8.1
DD
L
= 3.3 V Square Wave
IN
8.5
V
V
= 2.5 V, C = 15 pF
8.0
DD
L
= 2.5 V Square Wave
IN
8.4
AC Supply Current
10 Mbps
V
V
= 5 V, C = 15 pF
9.9
DD
L
= 5 V Square Wave
IN
10.2
8.9
V
V
= 3.3 V, C = 15 pF
11
DD
L
= 3.3 V Square Wave
IN
9.3
V
V
= 2.5 V, C = 15 pF
8.6
10.5
17.5
14.3
13
DD
L
= 2.5 V Square Wave
IN
9.0
AC Supply Current
50 Mbps
V
V
= 5 V, C = 15 pF
14.8
15.2
12.1
12.6
11.1
11.6
DD
L
= 5 V Square Wave
IN
V
V
= 3.3 V, C = 15 pF
L
= 3.3 V Square Wave
DD
IN
V
V
= 2.5 V, C = 15 pF
L
= 2.5 V Square Wave
DD
IN
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5
NCID9210 / NCID9216
SWITCHING CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C unless otherwise specified. All typical values are measured at T = 25°C.
A
A
Symbol
Parameter
Conditions
= 5 V, V Square Wave, C = 15 pF
Min
Typ
17.0
18.3
20.0
13.0
14.5
16.0
3.6
Max
Units Figure
t
Propagation Delay
to Logic Low Output
(Note 8)
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
25
ns
ns
ns
ns
ns
ns
6,9
PHL
IN
L
= 3.3 V, V Square Wave, C = 15 pF
IN
L
= 2.5 V, V Square Wave, C = 15 pF
IN
L
t
Propagation Delay
to Logic High Output
(Note 9)
= 5 V, V Square Wave, C = 15 pF
25
10
10
PLH
IN
L
= 3.3 V, V Square Wave, C = 15 pF
IN
L
= 2.5 V, V Square Wave, C = 15 pF
IN
L
PWD
Pulse Width Distor-
= 5 V, V Square Wave, C = 15 pF
IN L
tion | t
– t
PLH
|
PHL
= 3.3 V, V Square Wave, C = 15 pF
3.8
IN
L
(Note 10)
= 2.5 V, V Square Wave, C = 15 pF
3.8
IN
L
t
Propagation Delay
Skew (Part to Part)
(Note 11)
= 5 V, V Square Wave, C = 15 pF
−10
PSK(PP)
IN
L
= 3.3 V, V Square Wave, C = 15 pF
IN
L
= 2.5 V, V Square Wave, C = 15 pF
IN
L
t
R
Output Rise Time
(10% to 90%)
= 5 V, V Square Wave, C = 15 pF
1.1
1.5
2.2
1.1
1.4
3.0
IN
L
= 3.3 V, V Square Wave, C = 15 pF
IN
L
= 2.5 V, V Square Wave, C = 15 pF
IN
L
t
F
Output Fall Time
(90% to 10%)
= 5 V, V Square Wave, C = 15 pF
IN L
= 3.3 V, V Square Wave, C = 15 pF
IN
L
= 2.5 V, V Square Wave, C = 15 pF
IN
L
8. Propagation delay t
9. Propagation delay t
is measured from the 50% level of the falling edge of the input pulse to the 50% level of the falling edge of the V signal.
O
PHL
PLH
is measured from the 50% level of the rising edge of the input pulse to the 50% level of the rising edge of the V signal.
O
10.PWD is defined as | t
– t
PLH
| for any given device.
PHL
11. Part−to−part propagation delay skew is the difference between the measured propagation delay times of a specified channel of any two parts
at identical operating conditions and equal load.
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NCID9210 / NCID9216
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
20
TA = 25°C
LOAD = No Load
TA = 25°C
LOAD = 15 pF
IDD1
IDD2
IDD1
IDD2
15
10
5
= 3.3 V
V DD
VDD = 3.3 V
= 5 V
VDD
V
DD = 5 V
= 2.5 V
VDD
= 2.5 V
VDD
0
0
0
10
20
30
40
50
0
10
20
30
40
50
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 3. Supply Current vs. Data Rate (No Load)
Figure 4. Supply Current vs. Data Rate
(Load = 15 pF)
3.0
25
20
15
10
5
= 2.5 V
VDD
tPHL
= 3.3 V
VDD
t PHL
= 5 V
VDD
t PHL
2.5
V UVLO+
V UVLO−
= 5 V
VDD
tPLH
= 3.3 V
VDD
tPLH
2.0
= 2.5 V
VDD
tPLH
1.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
− AMBIENT TEMPERATURE (°C)
TA
20
40
60
80
100 120
− AMBIENT TEMPERATURE (°C)
TA
Figure 5. Supply Voltage UVLO Threshold vs.
Ambient Temperature
Figure 6. Propagation Delay vs. Ambient
Temperature
1.0
0.8
0.6
0.4
0.2
0.0
6
TA = 25°C
TA = 25 °C
= 5 V
VDD
5
4
3
2
1
0
= 3.3 V
= 2.5 V
VDD
VDD
VDD = 2.5 V
VDD = 3.3 V
V
DD = 5 V
0
2
4
6
8
10
−10
−8
−6
−4
−2
0
− LOW LEVEL OUTPUT CURRENT (mA)
IOL
IOH − HIGH LEVEL OUTPUT CURRENT (mA)
Figure 7. High Level Output Voltage vs. Current
Figure 8. Low Level Output Voltage vs. Current
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7
NCID9210 / NCID9216
TEST CIRCUITS
50%
VI
VDDI
VDDO
t PLH
t PHL
VI
VO
CL
+
−
+
−
90%
VIN
50%
VO
10%
tR
tF
Figure 9. VIN to VO Propagation Delay Test Circuit and Waveform
1
0
VDDI
VDDO
VIN
VO
S at 0, V remain consistently low
O
2
S
S at 1, V remain consistently high
O
S at 2, V data same as V data
O
IN
SCOPE
VCM
Figure 10. Common Mode Transient Immunity Test Circuit
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NCID9210 / NCID9216
APPLICATIONS INFORMATION
Theory of Operation
signal lines and power fill on top, and signal lines and ground
fill at the bottom. The alternating polarities of the layers
creates interplane capacitances that aids the bypass
capacitors required for reliable operation at digital
switching rates.
In the layout with digital isolators, it is required that the
isolated circuits have separate ground and power planes. The
section below the device should be clear with no power,
ground or signal traces. Maintain a gap equal to or greater
than the specified minimum creepage clearance of the
device package.
NCID9210 and NCID9216 are dual−channel digital
isolators that enable bi−directional communication between
two isolated circuits. They use off−chip ceramic capacitors
that serve both as the isolation barrier and as the medium of
transmission for signal switching using On−Off keying
(OOK) technique, illustrated in the single channel
operational block diagram in Figure 11.
At the transmitter side, the V input logic state is
IN
modulated with a high frequency carrier signal. The
resulting signal is amplified and transmitted to the isolation
barrier. The receiver side detects the barrier signal and
demodulates it using an envelope detection technique. The
Signal Lines / V
Fill
Signal Lines / V
Fill
DD2
DD1
output signal determines the V output logic state. V is at
default state low when the power supply at the transmitter
O
O
GND1 Plane
Plane
GND2 Plane
Plane
No Trace
V
V
DD2
side is turned off or the input V is disconnected.
DD1
IN
Signal Lines / GND1 Fill
Signal Lines / GND2 Fill
ISOLATION
BARRIER
TRANSMITTER
RECEIVER
Figure 14. 4−Layer PCB for Digital Isolator
TX
OOK
Modulator
RX
Amplifier
Envelope
Detector
IO
VIN
VO
For NCID9210 and NCID9216, it is highly advised to
connect at least a pair of low ESR supply bypass capacitors,
placed within 2 mm from the power supply pins 3 and 14 and
ground pins 1 and 16. Recommended values are 1 mF and
Amplifier
OFF−CHIP
CAPACITORS
OSC
Figure 11. Operational Block Diagram of Single
Channel
0.1 mF, respectively. Place them between the V pins of the
DD
device and the via to the power planes, with the higher
frequency, lower value capacitor closer to the device pins.
Directly connect the device ground pins 1, 7, 9 and 16 by via
to their corresponding ground planes.
VIN
ISOLATION
BARRIER
SIGNAL
1mF 0.1mF
0.1mF 1mF
GND1
GND2
VO
V
DD1
V
DD2
Figure 12. On−Off Keying Modulation Signals
OFF−CHIP CAPACITIVE
ISOLATION BARRIER
GND1
GND2
VINA
VOB
IO
+
VTX
VOA
IO
IO
RX
TX
TX
RX
−
Figure 15. Placement of Bypass Capacitors
OSC
VINB
+
VTX
−
Over Temperature Detection
IO
NCID9210 and NCID9216 have built−in Over
Temperature Detection (OTD) feature that protects the IC
from thermal damage. The output pins will automatically
switch to default state when the ambient temperature
exceeds the maximum junction temperature at threshold of
approximately 160°C. The device will return to normal
operation when the temperature decreases approximately
20°C below the OTD threshold.
OSC
Figure 13. NCID9210 Operational Block Diagram
Layout Recommendation
Layout of the digital circuits relies on good suppression of
unwanted noise and electromagnetic interference. It is
recommended to use 4−layer FR4 PCB, with ground plane
below the components, power plane below the ground plane,
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9
NCID9210 / NCID9216
ORDERING INFORMATION
Part Number
†
Grade
Package
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
Shipping
NCID9210
Industrial
Industrial
50 Units / Tube
750 Units / Tape & Reel
50 Units / Tube
NCID9210R2
NCID9216 (pending)
NCID9216R2 (pending)
NCIV9210* (pending)
NCIV9210R2* (pending)
NCIV9216* (pending)
NCIV9216R2* (pending)
Industrial
Industrial
750 Units / Tape & Reel
50 Units / Tube
Automotive
Automotive
Automotive
Automotive
750 Units / Tape & Reel
50 Units / Tube
750 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC*Q100 Qualified and PPAP
Capable.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC16 W
CASE 751EN
ISSUE A
DATE 24 AUG 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AWLYWW
XXXXXXXXXX
XXXXXXXXXX
Y
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13751G
SOIC16 W
PAGE 1 OF 1
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