NCL30386B1DR2G_技术文档

NCL30386

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Dimmable Power Factor

Corrected LED Driver

Featuring Primary Side CC /

CV Control

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The NCL30386 is a power factor corrected controller targeting

isolated and non−isolated “smart−dimmable” constant−current LED

drivers. Designed to support flyback, buck−boost and SEPIC

topologies, the controller operates in a quasi−resonant mode to

provide high efficiency. Thanks to a novel control method, the device

is able to tightly regulate a constant LED current and voltage from the

primary side. This removes the need for secondary−side feedback

circuitry, its biasing and for an optocoupler. The device also provides

near−unity power factor correction.

MARKING

DIAGRAM

9

1

9

L30386x

ALYWX

G

1

SOIC−9

CASE 751BP

The device is highly integrated with a minimum number of external

components. A robust suite of safety protection is built in to simplify

the design. This device is specifically intended for very compact space

efficient designs and supports analog and digital dimming with two

dedicated dimming inputs control ideal for Smart LED Lighting

applications.

L30386

x

= Specific Device Code

= Version

= Assembly Location

= Wafer Lot

= Year

= Work Week

A

L

Y

W

G

= Pb−Free Package

Features

• High Voltage Startup

PIN CONNECTIONS

• Quasi−resonant Peak Current−mode Control Operation

• Primary Side Feedback

ADIM

COMP

ZCD

HV

1

2

3

4

5

10

• CC / CV Control

• Tight LED Constant Current Regulation of 2% Typical

• Digital Power Factor Correction

• Analog and Digital Dimming

• Cycle by Cycle Peak Current Limit

PDIM

8

7

6

CS

VCC

DRV

GND

• Wide Operating V Range

CC

• −40 to + 125°C

• Robust Protection Features

ORDERING INFORMATION

See detailed ordering and shipping information on page 18 of

this data sheet.

♦ Brown−Out

♦ OVP on V

CC

♦ Constant Voltage / LED Open Circuit Protection

♦ Winding Short Circuit Protection

♦ Secondary Diode Short Protection

♦ Output Short Circuit Protection

♦ Thermal Shutdown

Typical Applications

• Integral LED Bulbs

• LED Power Driver Supplies

• LED Light Engines

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

1

Publication Order Number:

April, 2018 − Rev. P2

NCL30386/D

NCL30386

.

Aux

.

V_ADIM

NCL30386

1

2

3

4

5

10

9

8

7

6

PWM signal

Figure 1. Typical Application Schematic for NCL30386

PIN FUNCTION DESCRIPTION NCL30386

Pin N5

1

Pin Name

Function

Pin Description

ADIM

Analog dimming

This pin is used for analog control of the output current. Applying a voltage varying

between V and V will dim the output current from 0.5% to 100%.

DIM(EN)

DIM100

2

ZCD

Zero crossing

This pin connects to the auxiliary winding and is used to detect the core reset event.

This pin also senses the auxiliary winding voltage for accurate output voltage control

Detection V

sensing

aux

OTA output for CV loop

Current sense

−

3

4

5

6

7

8

COMP

CS

This pin receives a compensation network to stabilize the CV loop

This pin monitors the primary peak current.

The controller ground

GND

DRV

VCC

PDIM

Driver output

The driver’s output to an external MOSFET

This pin is connected to an external auxiliary voltage.

Supplies the controller

PWM dimming

This pin is used PWM dimming control. An optocoupler can be connected directly to

the pin if the PWM control signal is from the secondary side

9

NC

HV

creepage

10

High Voltage sensing

This pin connects after the diode bridge to provide the startup current and internal

high voltage sensing function.

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2

NCL30386

INTERNAL CIRCUIT ARCHITECTURE

CS_shorted

Enable

V

REF

STOP

DD

OFF

f_OVP

UVP

VCC

Internal

UVLO

Latch

Fault

Management

Thermal

Shutdown

VCC Management

COMP

VCC_max

VCC Over Voltage

Protection

Ipkmax

HV

STUP

WOD_SCP

BO_NOK

Constant Voltage Control

V

CV

V

HVdiv

FF_mode

Qdrv

V

HVdiv

REFX

HV

BO_NOK

Brown−Out

FF_mode

Zero Crossing Detection Logic

(ZCD Blanking, Time−Out, ...)

f_OVP

UVP

ZCD

Valley Selection

Frequency Foldback

VCC

S

Under Voltage Protection

Qdrv

Q

Clamp

Circuit

V

HVdiv

DRV

R

Line

feed−forward

STOP

V

REF(PFC)

CS

Leading

Edge

Blanking

CS_reset

Ipkmax

ADIM

Constant−Current Control

Analog

Dimming

V

DIMA

STOP

Enable

V

dc_DIM

V

CV

DIMA

PDIM

Max. Peak

Current

Limit

PWM

Dimming

dc_DIM

Ipkmax

VREFX

setpoint

CS Short

Protection

V

CS_shorted

REFX

Generation of the

Reference Voltage

for Power Factor Corr.

Winding and

Output diode

Short Circuit

Protection

V

HVdiv

REF(PFC)

WOD_SCP

GND

Figure 2. Internal Circuit Architecture NCL30386

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3

NCL30386

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

Maximum Power Supply voltage, VCC pin, continuous voltage

Maximum current for VCC pin

−0.3 to 30

Internally limited

V

mA

CC(MAX)

I

V

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3, V

(Note 1)

V

mA

DRV(MAX)

DRV

I

−300, +500

V

Maximum voltage on HV pin

Maximum current for HV pin (dc current self−limited if operated within the allowed range)

−0.3, +700

V

mA

HV(MAX)

I

20

V

Maximum voltage on low power pins (except pins HV, DRV and VCC)

Current range for low power pins (except pins HV, DRV and VCC)

−0.3, 5.5 (Note 2)

−2, +5

V

mA

MAX

I

R

Thermal Resistance Junction−to−Air

Maximum Junction Temperature

180

°C/W

°C

kV

V

θ

J−A

T

150

J(MAX)

Operating Temperature Range

−40 to +125

Storage Temperature Range

−60 to +150

ESD Capability, HBM model except HV pin (Note 3)

ESD Capability, HBM model HV pin

ESD Capability, MM model (Note 3)

ESD Capability, CDM model (Note 3)

4

700

200

1

V

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. V

is the DRV clamp voltage V

when V is higher than V

. V

is V otherwise.

DRV

DRV(high)

CC

DRV(high) DRV CC

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages

can be applied if the pin current stays within the −2 mA / 5 mA range.

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.

Charged Device Model 2000 V per JEDEC Standard JESD22−C101D.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, , V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Description

Test Condition

Symbol

Min

Typ

Max

Unit

HIGH VOLTAGE SECTION

High voltage current source

V

CC

= V

– 200 mV

I

3.3

4.7

6.1

mA

V

CC(on)

HV(start2)

V

= 0 V

300

2

CC

HV(start1)

V

CC

level for I

to I

HV(start2)

transition

V

CC(TH)

HV(start1)

Minimum startup voltage

HV source leakage current

V

= 0 V

V

−

17

4.5

−

V

CC

HV(MIN)

HV(leak)

V

HV

= 450 V

I

10

mA

Vrms

Maximum rms input voltage for correct constant−current operation

(T = −20°C to 125°C)

J

V

265

HV(OL)

SUPPLY SECTION

Supply Voltage

V

Startup Threshold

V

increasing

decreasing

V

16

9.77

8.2

7.8

4

18

10.80

8.6

−

20

11.24

9.4

−

CC

CC(on)

Threshold for turning off DSS (Note 5)

Minimum Operating Voltage

V

CC(on2)

V

CC

V

CC

V

CC(off)

CC(HYS)

CC(reset)

Hysteresis V

– V

V

CC(on)

CC(off)

Internal logic reset

5

6

Over Voltage Protection

VCC OVP threshold

V

25

26.5

28

V

CC(OVP)

V

noise filter (Note 6)

CC(reset)

t

−

5

20

−

ms

CC(off)

VCC(off)

noise filter (Note 6)

t

VCC(reset)

Supply Current

mA

Device Disabled/Fault

V

> V

I

1.2

–

1.5

3.0

3.3

2.9

1.8

3.5

4.0

3.4

CC

sw

CC(off)

CC1

CC2

CC3

CC4

Device Enabled/No output load on pin 5

F

= 65 kHz

Device Switching (F = 65 kHz)

C

= 470 pF, F = 65 kHz

−

sw

DRV

sw

Device switching (F = 15 kHz)

V

= 10%of max value

−

REFX

5. Refer to ordering table option at the end of the document.

6. Guaranteed by design.

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4

NCL30386

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, , V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Description

Test Condition

Symbol

Min

Typ

Max

Unit

CURRENT SENSE

Maximum Internal current limit

V

1.31

270

−

1.38

1.45

390

150

49

V

ns

ms

V

ILIM

LEB

ILIM

Leading Edge Blanking Duration for V

t

330

100

39

ILIM

Propagation delay from current detection to gate off−state

Maximum on−time (option B)

t

29

on(MAX)

Maximum on−time (option A)

t

16

20

24

on(MAX2)

Threshold for immediate fault protection activation (140% of V

)

V

1.91

−

1.99

170

500

60

2.07

−

ILIM

CS(stop)

Leading Edge Blanking Duration for V

t

ns

mA

mV

CS(stop)

BCS

CS(short)

Current source for CS to GND short detection

Current sense threshold for CS to GND short detection

GATE DRIVE

I

400

20

600

100

V

CS

rising

V

CS(low)

Drive Resistance

DRV Sink

DRV Source

W

R

−

13

30

−

SNK

SRC

Drive current capability

DRV Sink (Note GBD)

DRV Source (Note GBD)

mA

I

−

500

300

−

SNK

I

SRC

Rise Time (10 % to 90 %)

Fall Time (90 % to 10 %)

DRV Low Voltage

C

= 470 pF

t

–

8

30

20

–

−

ns

V

DRV

r

t

DRV

f

V

= V

+0.2 V

V

CC

C

CC(off)

DRV(low)

= 470 pF,

DRV

R

=33 kW

DRV

DRV High Voltage

V

= V

V

10

12

14

V

CC

CC(MAX)

DRV(high)

C

= 470 pF,

DRV

R

=33 kW

DRV

ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD threshold voltage

V

rising

falling

V

−

35

90

55

150

−

mV

ns

ZCD

ZCD(rising)

V

ZCD(falling)

Lower ZCD threshold voltage

V

ZCD

ZCD hysteresis

V

15

−

ZCD(HYS)

ZCD(DEM)

Propagation Delay from valley detection to DRV high

Blanking delay after on−time (ZCD blank option B)

Blanking Delay at light load (ZCD blank option B)

Blanking delay after on−time (ZCD blank option A)

Blanking Delay at light load (ZCD blank option A)

Timeout after last DEMAG transition

Pulling−down resistor

V

decreasing

t

−

150

1.9

1.0

1.25

0.75

8

ZCD

V

> 0.35 V

< 0.25 V

> 0.35 V

< 0.25 V

t

1.1

0.6

0.75

0.45

5

1.5

0.8

1.0

0.6

6.5

200

ms

REFX

ZCD(blank1)B

ZCD(blank2)B

ZCD(blank1)A

ZCD(blank2)A

V

ms

V

ms

t

ms

TIMO

V

= V

R

ZCD(pd)

kW

ZCD

ZCD(falling)

CONSTANT CURRENT CONTROL

Reference Voltage at T = 25°C to 100°C

V

326

323

333

340

343

mV

J

REF

Reference Voltage T = −40°C to 125°C

J

REF

10% reference Voltage (T = 25°C to 85°C)

V

23.45

21.77

20

33.50

50

43.55

45.23

100

J

REF10

10% reference Voltage (T = −40°C to 125°C)

V

J

Current sense lower threshold for detection of the leakage induc-

tance reset time

V

CS

falling

V

CS(low)

Blanking time for leakage inductance reset detection

CONSTANT VOLTAGE SECTION

t

−

120

−

ns

V

CS(low)

Internal voltage reference for constant voltage regulation

V

2.42

2.48

2.54

REF(CV)

T

J

= 25°C

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5

NCL30386

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, , V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Description

Test Condition

Symbol

Min

Typ

Max

Unit

CONSTANT VOLTAGE SECTION

Internal voltage reference for constant voltage regulation

J

V

2.38

40

2.48

2.58

60

V

REF(CV)

T = −40°C to 125°C

CV Error amplifier Gain

G

EA

50

60

mS

mA

V

Error amplifier current capability

V

REFX

=V

I

EA

REF

COMP pin lower clamp voltage

V

0.6

CV(clampL)

CV(clampH)

COMP pin higher clamp voltage

V

4.1

V

ZCD pin voltage below which the CV OTA is boosted

Error amplifier current capability during boost phase

V

* 80%

V

1.88

2.69

2

2.12

3.04

V

REF(CV)

boost(CV)

I

140

2.87

1.5

mA

V

EAboost

ZCD slow OVP threshold (V

*115%)

V

OVP1

ref(CV)

Switching period during slow OVP

ZCD voltage at which slow OVP is exit (V

T

ms

V

sw(OVP1)

*105%)

V

2.625

3.43

ref(CV)

OVP1rst

ZCD fast OVP threshold (V

*130%)

V

OVP2

3.29

3.57

V

ref(CV)

LINE FEED FORWARD

V

to I

conversion ratio

K

0.153

76

0.185

95

0.217

114

42

mA/V

mA

VS

CS(offset)

LFF

Offset current maximum value

V

> (450 V or 500 V)

I

offset(MAX)

HV

Line feed−forward current

DRV high, V = 200 V

I

32

37

mA

HV

FF

VALLEY LOCKOUT SECTION

Threshold for line range detection V increasing

V

increases

decreases

V

HL

252

241

15

264

253

25

276

265

35

V

HV

Threshold for line range detection V decreasing

HV

V

HV

V

LL

Blanking time for line range detection

t

ms

%

HL(blank)

Valley thresholds (expressed as a percentage of V

)

REF

st

nd

rd

1

to 2 valley transition at LL and 2 to 3 valley HL, V

decr.

incr.

decr.

incr.

decr.

incr.

decr.

incr.

V

decreases

V

80

90

65

75

50

60

35

45

REF

VLY1−2/2−3

VLY2−1/3−2

VLY2−3/3−4

VLY3−2/4−3

VLY3−4/4−5

VLY4−3/5−4

VLY4−5/5−6

VLY5−4/6−5

nd

st

rd

nd

th

rd

th

nd

th

rd

th

2

to 1 valley transition at LL and 3 to 2 valley HL, V

V

increases

decreases

increases

decreases

increases

decreases

increases

REF

2

to 3 valley transition at LL and 3 to 4 valley HL, V

V

rd

3

to 2 valley transition at LL and 4 to 3 valley HL, V

V

REF

rd

3

to 4 valley transition at LL and 4 to 5 valley HL, V

V

th

4

to 3 valley transition at LL and 5 to 4 valley HL, V

V

REF

th

4

to 5 valley transition at LL and 5 to 6 valley HL, V

V

th

5

to 4 valley transition at LL and 6 to 5 valley HL, V

V

REF

V

REF

V

REF

value at which the FF mode is activated

value at which the FF mode is removed

V

decreases

increases

V

25

35

%

REF

FFstart

V

REF

FFstop

FREQUENCY FOLDBACK

Added dead time

V

= 25%V

t

1.4

2.0

40

2.6

−

ms

REFX

REF

FF1LL

Added dead time

V

= 8% V

t

−

REFX

REF

FFchg

FFend

Dead−time clamp (Maximum dead−time option C)

Dead−time clamp (Maximum dead−time option B)

Dead−time clamp (Maximum dead−time option A)

DIMMING SECTION

V

< 1 mV

< 3 mV

t

1.4

687

250

−

REFX

t

−

FFend2

FFend3

V

< 11.2 mV

−

REFX

DIM pin voltage for zero output current (OFF voltage)

ADIM pin voltage for 0.5% reference voltage

V

0.475

0.67

0.5

0.7

0.5

3.0

2.3

6.8

10

0.525

0.73

V

ADIM(EN)

V

ADIM(MIN)

Minimum dimming level (dimming lower clamp option Y)

K

%

V

DIM(MIN)

ADIM pin voltage for maximum output current (V

Dimming range

= 1 V)

V

−

3.1

REFX

ADIM100

V

ADIM(range)

Clamping voltage for DIM pin

V

ADIM(CLP)

Dimming pin pull−up current source

Current Comparator threshold for PDIM

I

8

12

80

mA

ADIM(pullup)

I

rising

falling

I

60

86

70

PDIM

PDIM(THR)

I

100

114

PDIM

PDIM(THD)

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NCL30386

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, , V = 0 V)

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Description

Test Condition

Symbol

Min

Typ

Max

Unit

DIMMING SECTION

Cascode current limit for PDIM

PDIM pin voltage

I

510

600

690

mA

PDIM(LIM)

V

PDIM

−

3

V

FAULT PROTECTION

Thermal Shutdown

Device switching

SW

T

SHDN

130

150

170

°C

(F

around 65 kHz)

Thermal Shutdown Hysteresis

T

−

50

–

°C

SHDN(HYS)

Threshold voltage for output short circuit or aux. winding short

circuit detection

V

0.8

1.0

1.2

V

ZCD(short)

Short circuit detection Timer

V

ZCD

< V

t

OVLD

70

3

90

4

110

5

ms

s

ZCD(short)

Auto−recovery Timer

t

recovery

BROWN−OUT AND LINE SENSING

Brown−Out ON level (IC start pulsing)

Brown−Out OFF level (IC stops pulsing)

BO comparators delay

V

increasing

decreasing

V

104

93

110

99

30

25

61

4

116

105

V

HV

HVBO(on)

HVBO(off)

BO(delay)

BO(blank)

V

HV

V

t

ms

V

Brown−Out blanking time

15

35

HV pin voltage above which the sampling of ZCD is enabled

Sampling Enable comparator hysteresis

V

HV

decreasing

increasing

V

sampEN

V

HV

V

sampHYS

TYPICAL CHARACTERISTICS

18.30

18.25

18.20

18.15

18.10

8.90

8.88

8.86

8.84

8.82

8.80

18.05

18.00

8.78

8.76

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 3. V_CC(on)vs. Junction Temperature

Figure 4. V_CC(off)vs. Junction Temperature

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NCL30386

TYPICAL CHARACTERISTICS

28.0

27.5

27.0

26.5

26.0

1.45

1.43

1.41

1.39

1.37

1.35

25.5

25.0

1.33

1.31

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 5. V_CC(OVP)vs. Junction Temperature

Figure 6. V_ILIMvs. Junction Temperature

100

90

80

70

60

50

40

2.07

2.05

2.03

2.01

1.99

1.97

1.95

30

20

1.93

1.91

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 7. V_CS(low)Fvs. Junction Temperature

Figure 8. V_CS(stop)vs. Junction Temperature

144

134

124

114

104

94

335.5

334.5

333.5

332.5

84

331.5

330.5

74

64

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 9. t_ILIMvs. Junction Temperature

Figure 10. V_REFvs. Junction Temperature

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NCL30386

TYPICAL CHARACTERISTICS

60

58

56

54

52

50

48

46

44

2.511

2.506

2.501

2.496

2.491

2.486

2.481

2.476

2.471

2.466

42

40

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 11. V_REF(CV)vs. Junction Temperature

Figure 12. G_EAvs. Junction Temperature

3.46

2.883

2.878

2.873

2.868

2.863

2.858

2.853

2.848

3.45

3.44

3.43

3.42

3.41

3.40

2.843

2.838

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 13. V_OVP1vs. Junction Temperature

Figure 14. V_OVP2vs. Junction Temperature

0.190

0.188

0.186

37.8

37.6

37.4

37.2

37.0

36.8

36.6

0.184

36.4

36.2

36.0

0.182

0.180

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 15. K_LFFvs. Junction Temperature

Figure 16. I_FFvs. Junction Temperature

www.onsemi.com

9

NCL30386

TYPICAL CHARACTERISTICS

100.2

99.7

99.2

111.2

110.7

110.2

98.7

98.2

109.7

109.2

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 17. V_HVBO(on)vs. Junction Temperature

Figure 18. V_HVbo(off)vs. Junction Temperature

75

74

73

72

71

70

69

68

67

0.504

0.502

0.500

0.498

0.496

0.494

66

65

−50

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 19. V_ADIM(EN)vs. Junction Temperature

Figure 20. I_PDIM(THR)vs. Junction Temperature

105

104

103

102

101

100

99

621

616

611

606

98

97

601

596

96

95

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 21. I_PDIM(THD)vs. Junction Temperature

Figure 22. I_PDIM(LIM)vs. Junction Temperature

www.onsemi.com

10

NCL30386

APPLICATION INFORMATION

The NCL30386 implements a current−mode architecture

• Fast Over Voltage Protection: If the voltage of ZCD pin

exceeds 130% of its regulation level, the controller

shuts dwon and waits 4 s before trying to restart.

• Brown−Out: the controller includes a brown−out circuit

which safely stops the controller in case the input

voltage is too low. The device will automatically restart

if the line recovers.

operating in quasi−resonant mode. Thanks to proprietary

circuitry, the controller is able to accurately regulate the

secondary side current and voltage of the fly−back converter

without using any opto−coupler or measuring directly the

secondary side current or voltage. The controller provides

near unity power factor correction

• Quasi−Resonance Current−Mode Operation:

implementing quasi−resonance operation in peak

current−mode control, the NCL30386 optimizes the

efficiency by switching in the valley of the MOSFET

drain−source voltage. Thanks to an internal algorithm

control, the controller locks−out in a selected valley and

remains locked until the input voltage or the output

current set point significantly changes.

• Primary Side Constant Current Control: thanks to a

proprietary circuit, the controller is able to take into

account the effect of the leakage inductance of the

transformer and allows an accurate control of the

secondary side current regardless of the input voltage

and output load variation

• Primary Side Constant Voltage Regulation: By

monitoring the auxiliary winding voltage, it is possible

to regulate accurately the output voltage. The output

voltage regulation is typically within 2%.

• Load Transient Compensation: Since PFC has low loop

bandwidth, abrupt changes in the load may cause

excessive over or under−shoot. The slow Over Voltage

Protection contains the output voltage when it tends to

become excessive. In addition, the NCL30386 speeds

up the constant voltage regulation loop when the output

voltage goes below 80% of its regulation level.

• Cycle−by−cycle peak current limit: when the current

sense voltage exceeds the internal threshold V

, the

ILIM

MOSFET is turned off for the rest of the switching

cycle.

• Winding Short−Circuit Protection: an additional

comparator senses the CS signal and stops the

controller if V reaches 1.5 x V

(after a reduced

CS

ILIM

LEB of t ). This additional comparator is enabled

BCS

only during the main LEB duration t , for noise

LEB

immunity reason.

• Output Under Voltage Protection: If a too low voltage is

applied on ZCD pin for 90−ms time interval, the

controllers assume that the output or the ZCD pin is

shorted to ground and shutdown. After waiting 4

seconds, the IC restarts switching.

• Analog Dimming: the ADIM pin is dedicated to analog

dimming. The minimum dimming level is fixed 0.5%

of the maximum output current. If a voltage lower than

V

is applied on the pin, the controller is

ADIM(EN)

disabled.

• PWM dimming: the PDIM pin is dedicated to PWM

dimming. The controller measures the duty ratio of a

signal applied to the pin and reduces the output current

accordingly. The PWM dimming signal is transform

into an analog signal internally, and the LED current is

controlled in an analog way.

• Thermal Shutdown: an internal circuitry disables the

gate drive when the junction temperature exceeds

150°C (typically). The circuit resumes operation once

the temperature drops below approximately 100°C.

• Dynamic Self Supply option: the dynamic self−supply

keeps the controller alive in case of low dimming. If

• Power Factor Correction: A proprietary concept allows

achieving high power factor correction and low THD

while keeping accurate constant current and constant

voltage control.

• Line Feed−forward: allows compensating the variation

of the output current caused by the propagation delay.

• V Over Voltage Protection: if the V pin voltage

CC

exceeds an internal limit, the controller shuts down and

waits 4 seconds before restarting pulsing.

V

CC

reaches V , the HV current source is turned

CC(off)

on to charge V capacitor until the voltage reaches

CC

V

CC(on2)

without interrupting the DRV pulses.

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11

NCL30386

POWER FACTOR AND CONSTANT CURRENT

CONTROL

♦ R

♦ V

is the current sense resistor

sense

is the output current reference: V

=

REFX

The NCL30386 embeds an analog/digital block to control

the power factor and regulate the output current by

monitoring the ZCD, CS and HV pin voltages (signals

V

if no dimming

REF

The output current reference (V

constant voltage mode is activated or ADIM pin voltage is

below V or a PWM signal with a duty−cycle below

) is V

unless the

REFX

REF

V

ZCD

, V

, V ). This circuit generates the current

HV_DIV

CS

ADIM(100)

setpoint V

and compares it to the current sense

95% is applied on PDIM.

CTRL_DIV

signal to turn the MOSFET off. The HV pin provides the

sinusoidal reference necessary for shaping the input current.

The obtained current reference is further modulated so that

when averaged over a half line period, it is equal to the

CONSTANT VOLTAGE CONTROL

The auxiliary winding voltage is sampled internally

through the ZCD pin.

A precise internal voltage reference V

voltage target for the CV loop.

sets the

REF(CV)

output current reference (V

). The modulation and

REFX

averaging process is made internally by a digital circuit. If

the HV pin properly conveys the sinusoidal shape, power

factor will be close to 1. Also, the Total Harmonic Distortion

(THD) will be low especially if the output voltage ripple is

small.

The sampled voltage is applied to the negative input of the

CV OTA and compared to V

.

REFCV

A type 2 compensator is needed at the CV OTA output to

stabilize the loop. The COMP pin voltage modify the the

output current internal reference in order to regulate the

output voltage.

The output current will be well regulated, following the

equation below:

When V

≥ 4 V, V

< 0.6 V, V

= V

.

COMP

REFX

REF

V_REFX

2N_spR_sense

(eq. 1)

I_OUT

+

= 0 V

REFX

Where:

♦ N is the secondary to primary transformer turns

sp

ratio: N = N / N .

sp

S

P

G_m

R_ZCDU

ZCD

V_ZCDsamp

ZCD & signal

sampling

COMP

.

R₁

C₁

R_ZCDL

OTA

V_REF(CV)

C₂

Aux.

Figure 23. Constant Voltage Feedback Circuit

STARTUP PHASE (HV STARTUP)

controller against short−circuit between V and GND. At

CC

It is generally requested that the LED driver starts to emit

light in less than 1 s and possibly within 300 ms. It is

challenging since the start−up consists of the time to charge

power−up, as long as V is below V

, the source

CC

CC(TH)

delivers I

(around 300 mA typical). Then, when

HV(start1)

V

CC

reaches V , the source smoothly transitions to

CC(TH)

the V capacitor and that necessary to charge the output

I

and delivers its nominal value. As a result, in case

CC

HV(start2)

capacitor until sufficient current flows into the LED string.

This second phase can be particularly long in dimming cases

where the secondary current is a portion of the nominal one.

The NCL30386/88 features a high voltage startup circuit

that allows charging VCC capacitor very fast.

of short−circuit between V and GND occurring at high

CC

line (V = 265 Vrms), the power dissipation will be 375 x

in

300u = 112 mW instead of 1.5 W if there was only one

startup current level.

To speed−up the output voltage rise, the following is

implemented:

When the power supply is first connected to the mains

outlet, the internal current source is biased and charges up

• The digital OTA output is increased until V

REF(PFC)

. Again, this is to speed−up the

the V capacitor. When the voltage on this V capacitor

CC

signal reaches V

REFX

reaches the V

level, the current source turns off. At this

CC(on)

control signal rise to their steady state value.

time, the controller is only supplied by the V capacitor,

CC

• At the beginning of each operating phase of a V

CC

and the auxiliary supply should take over before V

CC

cycle, the digital OTA output is set to 0. Actually, the

digital OTA output is set to 0 in the case of a cold

start−up or in the case of a start−up sequence following

collapses below V

.

CC(off)

The HV startup circuitry is made of two startup current

levels, I and I . This helps to protect the

HV(start1)

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12

NCL30386

an operation interruption due to a fault. On the other

hand, if the V hiccups just because the system fails to

threshold of (V

to detect a winding or an output diode short circuit. The

controller shuts down if it detects 4 consecutives pulses

= 140% *V

) monitors the CS pin

CS(stop)

ILIM

CC

start−up in one V cycle (DSS option not activated),

CC

during which the CS pin voltage exceeds V

The controller goes into auto−recovery mode.

the digital OTA output is not reset to ease the second

(or more) attempt.

CS(stop).

• If the load is shorted, the circuit will operate in hiccup

PWM DIMMING

mode with VCC oscillating between V

and

CC(off)

The NCL30386 has a dedicated pin for PWM dimming.

The controller directly measures the duty ratio of a PWM

signal applied to PDIM.

Two counters with a high frequency clock are used for this

purpose. A first counter measure the high state duration of

V

until the output under voltage protection (UVP)

CC(on)

trips. UVP is triggered if the ZCD pin voltage does not

exceed 1 V within a 90 ms operation of time. This

indicates that the ZCD pin is shorted to ground or that

an excessive load prevents the output voltage from

rising.

the PWM signal (t ) and the second counter measures

on_PDIM

its period (T

). A divider computes (t

/

sw_PDIM

on_PDIM

T

) and the result is directly the output current

sw_PDIM

CYCLE−BY−CYCLE CURRENT LIMIT

When the current sense voltage exceeds the internal

setpoint (V

set point). A filter is added after the digital

REFX

divider to remove the ripple of the signal. A cascode

configuration on PDIM pin allows decreasing the fall time

of the signal.

threshold V , the MOSFET is turned off for the rest of the

ILIM

switching cycle.

Due to this circuit, the LED current is controlled in an

analog way, even if a PWM signal is used for dimming. This

allows having a good PF during dimming.

WINDING AND OUTPUT DIODE SHORT−CIRCUIT

PROTECTION

In parallel to the cycle−by−cycle sensing of the CS pin,

another comparator with a reduced LEB (t ) and a

BCS

V_{DIM_sec}

T_{on_P}

I_PDIM

I_PDIM(THD)

I_PDIM(THR)

V_{PDIM_int}

T

sw_P

Figure 24. PDIM Internal Waveforms

Practically, the controller extracts the duty−cycle by

measuring the current inside PDIM pin which is directly the

opto coupler collector current.

If PDIM pin is left open, the controller delivers 100% of

I . If the pin is pulled down for longer than 25 ms, the

out

controller is disabled.

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13

NCL30386

ANALOG DIMMING

The pin ADIM pin allows dimming the LED light using

an analog signal as the control input.

The DIM pin voltage is sampled by an analog to digital

converter and sets the output current value accordingly.

If the power supply designer applies an analog signal

If a voltage lower than V

pin, the DRV pulses are disabled.

The DIM pin is pulled up internally by a small current

source or resistor. Thus, if the pin is left open, the controller

is able to start.

is applied to the DIM

ADIM(EN)

Note:

varying from V

to V

to the DIM pin, the

DIM(EN)

DIM100

• Interaction between ADIM and PDIM: if ADIM and

output current will increase or decrease proportionally to the

voltage applied. For V = V , the power supply

delivers the maximum output current (V

If a voltage lower than V

pin, the output current is clamped to 0.5% of the maximum

output current depending on the controller option

PDIM are both used at the same time, the resulting

DIM

DIM100

dimming set point if a multiplication of V

duty−ratio of PDIM signal.

and the

ADIM

= V ).

REFX

REF

is applied to ADIM

ADIM(MIN)

• If the dimming curve option S is selected, a square

relationship is implemented between the dimming

signal and the output current setpoint.

V_REF

100% V_REF

L option

S option

0.5% V_REF

V_ADIM(EN)

V_ADIM100

V_ADIM

V_ADIM(MIN)

Figure 25. ADIM Pin Dimming Curves

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14

NCL30386

VALLEY LOCKOUT

The NCL30386 changes valley as V

decreases and as

REFX

Quasi−Square wave resonant systems have a wide

switching frequency excursion. The switching frequency

increases when the output load decreases or when the input

voltage increases. The switching frequency of such systems

must be limited.

the input voltage increases and as the output current setpoint

is varied during dimming. This limits the frequency

excursion.

By default, when the output current is not dimmed, the

controller operates in the first valley at low line and in the

second valley at high line.

HV pin voltage for valley change

_REFXvalue at which the

controller changes valley

(I_outdecreasing)

V_REFXvalue at which the

controller changes valley

(I_outincreasing)

0

−−LL −− 230 V −−HL −− 400 V

100%

80%

100%

85%

1^st

2^nd

3^rd

4^th

65%

50%

35%

70%

55%

40%

4^th

5^th

6^th

25%

0%

30%

0%

FF mode

0

−−LL −− 240 V −−HL −− 400 V

HV pin voltage for valley change

Figure 26. TABLE II: Valley Selection

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15

NCL30386

ZERO CROSSING DETECTION BLOCK

the valleys. To avoid such a situation, the NCL30386 a

Time−Out circuit that generates pulses if the voltage on ZCD

pin stays below the 55 mV threshold for 6.5 ms.

The Time−out also acts as a substitute clock for the valley

detection and simulates a missing valley in case of too

damped free oscillations.

The ZCD pin allows detecting when the drain−source

voltage of the power MOSFET reaches a valley.

A valley is detected when the ZCD pin voltage crosses

below the 55 mV internal threshold.

At startup or in case of extremely damped free

oscillations, the ZCD comparator may not be able to detect

V_ZCD

3

4

V_ZCD(THD)

The 3^rdvalley is

validated

high

14

12

^nd, 3^rd

2

low

The 2^ndvalley is detected

By the ZCD comparator

The 3^rdvalley is not detected by the

ZCD comp

high

ZCD comp

15

16

low

high

low

Time−out circuit adds a pulse to

TimeOut

Clk

account for the missing 3^rdvalley

high

low

17

Figure 27. ZCD Time−out Chronograms

If the ZCD pin or the auxiliary winding happen to be

shorted the time−out function would normally make the

controller keep switching and hence lead to improper

regulation of the LED current.

The Under Voltage Protection (UVP) is implemented to

avoid these scenarios: a secondary timer starts counting

features a slow over voltage protection (slow OVP) and a

fast over voltage protection (fast OVP) on ZCD pin.

Slow OVP

If ZCD voltage exceed V

for 4 consecutive

ZCD(OVP1)

switching cycles, the controller stops switching during

1.4 ms. After 1.4 ms, the controller initiates a new DRV

when the ZCD voltage is below the V

threshold. If

ZCD(short)

pulse to refresh ZCD sampling voltage. If V

is still too

ZCD

this timer reaches 90 ms, the controller detects a fault and

enters the auto−recovery fault mode.

high (V

> 110%V

), the controller continues to

ZCD

REF(CV)

switch with a 1.4 ms period. The controller resumes its

normal operation when V

< 110%V

.

ZCD PIN OVER VOLTAGE PROTECTION.

ZCD

REF(CV)

Because of the power factor correction, it is necessary to

set the crossover frequency of the CV loop very low (target

10 Hz, depending on power stage phase shift). Because the

loop is slow, the output voltage can reach high value during

startup or during an output load step. It is necessary to limit

the output voltage excursion. For this, the NCL30388

Fast OVP

If ZCD voltage exceeds V

for 4 consecutive switching cycles (slow OVP not triggered)

or for 2 switching cycles if the slow OVP has already been

triggered, the controller detects a fault and starts the

auto−recovery fault mode (cf: Protections Section)

(130% of V

)

ZCD(OVP2)

REF(CV)

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16

NCL30386

LINE FEEDFORWARD

HV

v_DD

v_VS

CS

R_LFF

I_CS(offset)

K_LFF

R_sense

Q_drv

+

25 ms

Blanking

BO_NOK

−

1 V / 0.9 V

Figure 28. Line Feed−Forward and Brown−out Schematic

The line voltage is sensed by the HV pin and converted

into a current. By adding an external resistor in series

between the sense resistor and the CS pin, a voltage offset

proportional to the line voltage is added to the CS signal. The

offset is applied only during the MOSFET on−time in order

to not influence the detection of the leakage inductance

reset.

CS pin is monitored. If such a fault is detected for

200 ms, the circuit stops generating DRV pin.

• Output short circuit situation (Output Under Voltage

Protection)

Overload is detected by monitoring the ZCD pin

voltage: if it remains below V

for 90 ms, an

ZCD(short)

output short circuit is detected and the circuit stops

generating pulses for 4 s. When this 4 s delay has

elapsed, the circuit attempts to restart.

The offset is always applied even at light load in order to

improve the current regulation at low output load.

• ZCD pin incorrect connection:

BROWN−OUT

♦ If the ZCD pin grounded, the circuit will detect an

output short circuit situation when 90−ms delay has

elapsed.

In order to protect the supply against a very low input

voltage, the NCL30386 features a brown−out circuit with a

fixed ON/OFF threshold. The controller is allowed to start

if a voltage higher than 100 V is applied to the HV pin and

shuts−down if the HV pin voltage decreases and stays below

9 0 V for 25 ms typical. Exiting a brown−out condition

♦ A 200 kW resistor pulls down the ZCD pin so that

the output short circuit detection trips if the ZCD pin

is not connected (floating).

• Winding or Output Diode Short Circuit protection

The circuit detects this failure when 4 consecutive DRV

pulses occur within which the CS pin voltage exceeds

overrides the hiccup on V (V does not wait to reach

CC

V ) and the IC immediately goes into startup mode.

CC(off)

PROTECTIONS

(V =140% *V ). In this case, the controller

CS(stop) ILIM

The circuit incorporates a large variety of protections to

make the LED driver very rugged.

Among them, we can list:

enters auto−recovery mode (4−s operation interruption

between active bursts).

• V Over Voltage Protection

CC

• Fault of the GND connection

The circuit stops generating pulses if the V exceeds

CC

If the GND pin is properly connected, the supply

V

and enters auto−recovery mode. This feature

CC(OVP)

current drawn from the positive terminal of the V

CC

protects the circuit if output LEDs happen to be

disconnected.

capacitor, flows out of the GND pin to return to the

negative terminal of the V capacitor. If the GND pin

CC

• ZCD fast OVP

is not connected, the circuit ESD diodes offer another

return path. The accidental non connection of the GND

pin can hence be detected by detecting that one of this

ESD diode is conducting. Practically, the ESD diode of

If ZCD voltage exceeds V

for 4 consecutive

ZCD(OVP2)

switching cycles (slow OVP not triggered) or for 2

switching cycles if the slow OVP has already been

www.onsemi.com

17

NCL30386

triggered, the controller detects a fault and enters

auto−recovery mode (4 s operation interruption

between active bursts).

a brown−out event). A current source (I

) is

cs(short)

applied to the pin and no DRV pulse is generated until

the CS pin exceeds V . I and V are

cs(low) cs(short)

cs(low)

500 mA and 60 mV typically (V rising). The typical

• Die Over Temperature (TSD)

CS

minimum impedance to be placed on the CS pin for

operation is then 120 W. In practice, it is recommended

to place more than 250 W to take into account possible

parametric deviations

The circuit stops operating if the junction temperature

(T ) exceeds 150°C typically. The controller remains

J

off until T goes below nearly 100°C.

J

• Brown−Out Protection (BO)

Also, along the circuit operation, the CS pin could happen

to be grounded. If it is grounded, the MOSFET conduction

time is limited by the maximum on−time. If such an event

occurs, a new pin impedance test is made.

The circuit prevents operation when the line voltage is

too low to avoid an excessive stress of the LED driver.

Operation resumes as soon as the line voltage is high

enough and V is higher than V

.

CC

CC(on)

• CS pin short to ground

The CS pin is checked at start−up (cold start−up or after

ORDERING TABLE OPTION

Max. On−

time

Line Range

Detector

Dimming

Clamp

DSS

Maximum dead−time

V

ZCD blanking

Dimming Curve

REF

Y

On

x

N

A

B

C

U

V

A

B

A

B

1.5 ms

x

L

S

Y

N

Off

x

Y

N

Off

250 ms 687 ms 1.4 ms 250 mV 333 mV 20 ms 33 ms

1 ms

Linear

Square

On

Off

OPN #

NCL30386A1

NCL30386B1

x

ORDERING INFORMATION2

Device

†

Marking

L30386A1

L30386B1

Package type

Shipping

NCL30386A1DR2G

NCL30386B1DR2G

SOIC9 COMP EPX 0.5P PBF

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

18

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−9 NB

CASE 751BP

ISSUE A

9

1

DATE 21 NOV 2011

SCALE 1:1

2X

NOTES:

0.10

C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

0.20

C

4 TIPS

0.10 C A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

L

SEATING

PLANE

C

0.20

C

9X b

DETAIL A

B

5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

D

E

1.25

0.10

0.17

0.31

4.80

3.80

9X

h

X 45

_

0.10

C

0.10

C

M

e

1.00 BSC

H

h

L

L2

M

5.80

0.37 REF

6.20

1.27

A

0.40

0

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

0.25 BSC

C

8

_

END VIEW

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT*

9

1.00

PITCH

9X

0.58

XXXXX

ALYWX

G

1

XXXXX = Specific Device Code

6.50

A

L

= Assembly Location

= Wafer Lot

Y

W

G

= Year

= Work Week

= Pb−Free Package

1

9X

1.18

DIMENSION: MILLIMETERS

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

98AON52301E

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

ON SEMICONDUCTOR STANDARD

NEW STANDARD:

©

Semiconductor Components Industries, LLC, 2002

Case Outline Number:

http://onsemi.com

October, 2002 − Rev. 0

DESCRIPTION: SOIC−9 NB

PAGE 1 OFX2XX

1

DOCUMENT NUMBER:

98AON52301E

PAGE 2 OF 2

ISSUE

REVISION

DATE

O

A

RELEASED FOR PRODUCTION. REQ. BY M. RAMOS.

06 JUL 2010

21 NOV 2011

CHANGED DIMENSION A MINIMUM FROM 1.35 TO 1.25. REQ. BY I. CAMBALIZA.

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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

©

Semiconductor Components Industries, LLC, 2011

Case Outline Number:

November, 2011 − Rev. A

751BP

ON Semiconductor and

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

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◊


型号：	NCL30386B1DR2G
厂家：	ONSEMI
描述：	Dimmable Power Factor Corrected LED Driver Featuring Primary Side CC
文件：	总21页 (文件大小：317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL30386B1DR2G [ONSEMI]

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