NCN5130MNTWG_技术文档

NCN5130

Transceiver for KNX

Twisted Pair Networks

Introduction

NCN5130 is a receiver−transmitter IC suitable for use in KNX

twisted pair networks (KNX TP1−256). It supports the connection of

actuators, sensors, microcontrollers, switches or other applications in

a building network.

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NCN5130 handles the transmission and reception of data on the bus.

It generates from the unregulated bus voltage stabilized voltages for its

own power needs as well as to power external devices, for example, a

microcontroller.

NCN5130 assures safe coupling to and decoupling from the bus.

Bus monitoring warns the external microcontroller in case of loss of

power so that critical data can be stored in time.

QFN40

MN SUFFIX

CASE 485AU

1

40

MARKING DIAGRAM

Key Features

• 9600 baud KNX Communication Speed

• Supervision of KNX Bus Voltage and Current

• Supports Bus Current Consumption up to 40 mA

NCN5130

21420−004

AWLYYWWG

• High Efficient DC−DC Converters

♦ 3.3 V Fixed

♦ 1.2 V to 21 V Selectable

A

= Assembly Location

• Control and Monitoring of Power Regulators

• Linear 20 V Regulator

WL = Wafer Lot

YY = Year

WW = Work Week

• Buffering of Sent Data Frames (Extended Frames Supported)

• Selectable UART or SPI Interface to Host Controller

• Selectable UART and SPI baud Rate to Host Controller

• Optional CRC on UART to the Host

• Optional Received Frame−end with MARKER Service

• Optional Direct Analog Signaling to Host

• Operates with Industry Standard Low Cost 16 MHz Quartz

• Generates Clock of 8 or 16 MHz for External Devices

• Auto Acknowledge (optional)

• Auto Polling (optional)

• Temperature Monitoring

• Extended Operating Temperature Range −40°C to +105°C

• These Devices are Pb−Free and are RoHS Compliant

G

= Pb−Free Package

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 57 of this data sheet.

1

Publication Order Number:

September, 2016 − Rev. 3

NCN5130/D

NCN5130

BLOCK DIAGRAM

CEQ1

CEQ2

VFILT

TRIG

VDDA VSSA

VDDD VSSD

Bus Coupler

CAV

SCK/UC2

SDI/RXD

SDO/TXD

CSB/UC1

TREQ

UART

SPI

Impedance

Control

VBUS1

KNX

DLL

Receiver

CCP

MODE1

MODE2

Mode

Transmitter

TXO

VBUS2

VIN

NCN5130

VSW1

VDD1M

VDD1

VSS1

Fan−In

Control

FANIN

V20V

DC/DC

Converter 1

20V LDO

OSC

RC

OSC

POR

XTAL1

XTAL2

VSW2

VDD2MC

VDD2MV

VDD2

TW

TSD

DC/DC

Converter 2

UVD

XSEL

ANALOG

BUFFER

VSS2

Diagnostics

XCLKC

XCLK

ANAOUT

SAVEB RESETB

Figure 1. Block Diagram NCN5130

PIN OUT

VSSA

VDDD

1

2

30

29

28

27

26

25

24

23

22

21

VBUS2

TXO

SCK/UC2

SDO/TXD

SDI/RXD

CSB/UC1

TREQ

3

CCP

4

CAV

5

NCN5130

VBUS1

CEQ1

CEQ2

VFILT

V20V

6

MODE2

MODE1

TRIG

7

8

9

XCLKC

10

Figure 2. Pin Out NCN5130 (Top View)

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2

NCN5130

PIN DESCRIPTION

Table 1. PIN LIST AND DESCRIPTION

Equivalent

Schematic

Name

VSSA

VBUS2

TX0

1

Description

Type

Supply

Analog Supply Voltage Ground

2

Ground for KNX Transmitter

Supply

3

KNX Transmitter Output

Analog Output

Analog I/O

Supply

Type 1

Type 2

Type 3

Type 5

Type 4

Type 5

Type 8

Type 9

Type 8

CCP

4

AC coupling external capacitor connection

Capacitor connection to average bus DC voltage

KNX power supply input

CAV

5

VBUS1

CEQ1

CEQ2

VFILT

6

7

Capacitor connection 1 for defining equalization pulse

Capacitor connection 2 for defining equalization pulse

Filtered bus voltage

Analog I/O

Supply

8

9

V20V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

20V supply output

Supply

VDD2MV

VDD2MC

VDD2

VSS2

Voltage monitor of Voltage Regulator 2

Current monitor input 1 of Voltage Regulator 2

Current monitor input 2 of Voltage Regulator 2

Voltage Regulator 2 Ground

Analog Input

Supply

VSW2

VIN

Switch output of Voltage Regulator 2

Voltage Regulator 1 and 2 Power Supply Input

Switch output of Voltage Regulator 1

Voltage Regulator 1 Ground

Analog Output

Supply

Type 6

Type 5

Type 6

VSW1

VSS1

Analog Output

Supply

VDD1

VDD1M

XCLKC

TRIG

Current Input 2 and Voltage Monitor Input of Voltage Regulator 1

Current Monitor Input 1 of Voltage Monitor 1

Clock Frequency Configure

Analog Input

Digital Input

Digital Output

Digital Input

Type 8

Type 9

Type 12

Transmission Trigger Output

Type 13

MODE1

MODE2

TREQ

CSB/UC1

Mode Selection Input 1

Type 12

Mode Selection Input 2

Type 12

Transmit Request Input

Type 12

Chip Select Output (SPI) or Configuration Input (UART)

or 20 V LDO Disable (Analog Mode)

Digital Output or

Digital Input

Type 13 or 14

SDI/RXD

SDO/TXD

SCK/UC2

27

28

29

Serial Data Input (SPI) or Receive Input (UART)

Serial Data Output (SPI) or Transmit Output (UART)

Digital Input

Type 14

Type 13

Digital Output

Serial Clock Output (SPI) or Configuration Input (UART)

or Voltage Regulator 2 Disable (Analog Mode)

Digital Output or

Digital Input

Type 13 or 14

VDDD

VSSD

XCLK

XSEL

XTAL2

30

31

32

33

34

Digital Supply Voltage Input

Supply

Type 7

Digital Supply Voltage Ground

Oscillator Clock Output

Digital Output

Digital Input

Type 13

Type 12

Clock Selection (Quartz or Digital Clock)

Clock Generator Output (Quartz) or Input (Digital Clock)

Analog Output or

Digital Input

Type 10 or 14

XTAL1

SAVEB

RESETB

FANIN

35

36

37

38

39

40

Clock Generator Input (Quartz)

Save Signal (open drain with pull−up)

Reset Signal (open drain with pull−up)

Fan−In Input

Analog Input

Digital Output

Analog Input

Analog Output

Supply

Type 10

Type 15

Type 11

Type 16

Type 7

ANAOUT

VDDA

Analog Signal Output

Analog Supply Voltage Input

NOTE: Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin

Type of XTAL1 and XTAL2 pin is depending on status XSEL pin.

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3

NCN5130

EQUIVALENT SCHEMATICS

Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified

representations of the circuits used.

CCP

60V

CAV

TXO

CEQx

60V

7V

60V

Type 1: TXO−pin

Type 2: CCP−pin

Type 3: CAV−pin

Type 4: CEQ1 and CEQ2−pin

VIN

VDDD

VDDA

VBUS1

60V

VFILT

60V

V20V

60V

VIN

60V

VDDD

VDDA

VBUS1

VFILT

V20V

VIN

VSWx

7V

60V

Type 7: VDDD− and VDDA−pin

Type 5: VBUS1−, VFILT−, V20V and VIN−pin

Type 6: VSW1 and VSW2−pin

VDD1

VDD2

7V

VDD1

VDD2

VDD2MV

VDD1M

VDD2MC

7V

60V

7V

60V

Type 8: VDD1−, VDD2− and VDD2MV−pin

Type 9: VDD1M− and VDD2MC−pin

VDDD

VAUX

VDDD

XTAL2

XTAL1

FANIN

IN

7V

R_DOWN

Type 12: MODE1−, MODE2−,

TREQ−, XCLKC− and XSEL−pin

Type 10: XTAL1− and XTAL2−pin

Type 11: FANIN−pin

VDDA

VDDD

R_UP

ANAOUT

OUT

IN

OUT

Type 13: CSB/UC1−,

SDO/TXD−, SCK/UC2−,

TRIG− and XCLK−pin

Type 14: CSB/UC1−,

SDI/RXD−, SCK/UC2

and XTAL2−pin

Type 15: RESETB− and

SAVEB−pin

Type 16: ANAOUT

NOTE: Type of CSB/UC1 and SCK/UC2 is depending on status MODE1 − MODE2 pin

Type of XTAL1 and XTAL2 pin is depending on status XSEL pin.

Figure 3. In− and Output Equivalent Diagrams

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4

NCN5130

ELECTRICAL SPECIFICATION

Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)

Symbol Parameter

Min

Max

+45

250

Unit

V

KNX Transmitter Output Voltage

−0.3

TXO

I

KNX Transmitter Output Current (Note 3)

Voltage on CCP−pin

mA

V

CCP

−10.5

−0.3

0

+14.5

+3.6

+45

+3.6

120

V

CAV

Voltage on CAV−pin

V

BUS1

Voltage on VBUS1−pin

V

Voltage on ANAOUT pin

Current Consumption VBUS1−pin

Voltage on pins CEQ1 and CEQ2

Voltage on VFILT−pin

V

ANAOUT

I

mA

V

BUS1

V

CEQ

−0.3

+45

+25

+3.6

+45

+3.6

V

FILT

V

20V

Voltage on V20V−pin

V

Voltage on VDD2MV−pin

Voltage on VDD2MC−pin

Voltage on VDD2−pin

V

DD2MV

DD2MC

V

DD2

V

Voltage on VSW1− and VSW2−pin

Voltage on VIN−pin

V

SW

V

IN

V

DD1

Voltage on VDD1−pin

V

DD1M

Voltage on VDD1M−pin

V

DIG

Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/TXD, SDO/RXD, SCK/

UC2, XCLK, XSEL, SAVEB, RESETB, XCLKC, TRIG, and FANIN

V

Voltage on VDDD− and VDDA−pin

Voltage on XTAL1− and XTAL2−pin

Storage temperature

−0.3

−55

−40

−2

+3.6

+150

+155

+2

V

DD

V

XTAL

T

°C

kV

ST

T

Junction Temperature (Note 4)

J

V

HBM

Human Body Model electronic discharge immunity (Note 5)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Convention: currents flowing in the circuit are defined as positive.

2. VBUS2, VSS1, VSS2, VSSA and VSSD form the common ground. They are hard connected to the PCB ground layer.

3. Room temperature, 27 W shunt resistor for transmitter, 250 mA over temperature range.

4. Normal performance within the limitations is guaranteed up to the Thermal Warning level. Between Thermal Warning and Thermal Shutdown

temporary loss of function or degradation of performance (which ceases after the disturbance ceases) is possible.

5. According to JEDEC JESD22−A114.

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5

NCN5130

Recommend Operation Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the

functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges

for extended periods of time may affect device reliability.

Table 3. OPERATING RANGES

Symbol

Parameter

Min

+20

Max

+33

Unit

V

V_BUS1

VBUS1 Voltage (Note 6)

V

Digital and Analog Supply Voltage (VDDD− and VDDA−pin)

Input Voltage DC−DC Converter 1 and 2

Input Voltage at CCP−pin

+3.13

(Note 7)

−10.5

0

+3.47

+33

V

DD

V

IN

V

CCP

+14.5

+3.3

V

Input Voltage at CAV−pin

V

CAV

Input Voltage on VDD1−pin

+3.13

+1.2

0

+3.47

+3.57

+21

V

DD1

V

DD1M

Input Voltage on VDD1M−pin

V

DD2

Input Voltage on VDD2−pin

V

Input Voltage on VDD2MC−pin

Input Voltage on VDD2MV−pin

+21.1

VDD

V

DD2MC

DD2MV

V

DIG

Input Voltage on pins MODE1, MODE2, TREQ, CSB/UC1, SDI/RXD, SCK/UC2,

XCLKC, and XSEL

V

Input Voltage on FANIN−pin

Clock Frequency External Quartz

Ambient Temperature

0

3.6

V

MHz

°C

FANIN

f

clk

16

T

A

−40

+105

+125

T_J

Junction Temperature (Note 8)

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

6. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V.

7. Minimum operating voltage on VIN−pin should be at least 1 V larger than the highest value of VDD1 and VDD2.

8. Higher junction temperature can result in reduced lifetime.

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6

NCN5130

Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

POWER SUPPLY

Excluding active and equalization

pulse

V

BUS1

Bus DC voltage

20

33

V

VBUS = 30 V, IBUS = 10 mA, DC2,

V20V disabled, no crystal or clock

2.00

2.70

I

Bus Current Consumption

mA

BUS1_Int

VBUS1

VBUS = 20 V, IBUS = 40 mA

3.50

18.0

16.8

4.40

18.9

17.7

V

Undervoltage release level

Undervoltage trigger level

Undervoltage hysteresis

Digital Power Supply

Analog Power Supply

Auxiliary Supply

V

rising, see Figure 4

falling, see Figure 4

17.1

15.9

0.6

V

BUSH

BUS1

V

BUSL

V

BUS_Hyst

V

VDDD

VDDA

3.13

2.8

3.3

3.47

3.6

DDD

DDA

V

Internal supply, for info only

AUX

KNX BUS COUPLER

FANIN floating, V

> V

0.40

0.80

1.51

1.17

0.78

0.37

0.17

25.0

50.0

72.2

70.7

48.5

23.4

11.3

11.4

22.3

43.9

33.0

22.1

10.7

5.1

0.50

1.00

1.95

1.47

0.98

0.48

0.23

30.0

60.0

114.0

86.0

57.5

27.8

13.1

12

FILT

FILTH

FANIN = GND, V

> V

FILT

FILTH

Resistor R6 = 10k, V

> V

FILTH

FILT

Bus Coupler Current Slope

Limitation

Resistor R6 = 13.3k, V

> V

FILTH

DI

/Dt

VBUS1

A/s

FILT

coupler

Resistor R6 = 20k, V

> V

FILTH

FILT

Resistor R6 = 42.2k, V

Resistor R6 = 93.1k, V

> V

FILT

FILTH

> V

FANIN floating, V

> V

20.0

40.0

45.0

40.0

19.5

9.4

FILT

FILTH

FANIN = GND, V

> V

Resistor R6 = 10k, V

> V

FILTH

FILT

I

Bus Coupler Startup Current

Limitation

coupler_lim,

startup

Resistor R6 = 13.3k, V

> V

FILTH

mA

FILT

Resistor R6 = 20k, V

> V

FILTH

FILT

Resistor R6 = 42.2k, V

Resistor R6 = 93.1k, V

> V

FILT

FILTH

> V

FANIN floating, V

> V

10.6

20.5

39.6

30.0

20.3

9.4

FILT

FILTH

FANIN = GND, V

> V

24

Resistor R6 = 10k, V

> V

47.0

35.2

23.6

11.9

6.0

FILT

FILTH

Bus Coupler Current

Limitation

Resistor R6 = 13.3k, V

> V

FILTH

I

mA

FILT

coupler_lim

Resistor R6 = 20k, V

> V

FILTH

FILT

Resistor R6 = 42.2k, V

Resistor R6 = 93.1k, V

> V

FILT

FILTH

> V

4.2

I

= 10 mA

= 20 mA

= 30 mA

= 40 mA

1.72

2.34

2.94

3.57

10.6

8.9

2.32

2.80

3.40

4.25

11.2

9.4

BUS1

VBUS1,

VFILT

Coupler Voltage Drop

V

coupler_drop

(V

= V

− V

)

coupler_drop

BUS1

FILT

V

FILTH

Undervoltage release level

Undervoltage trigger level

V

rising, see Figure 5

falling, see Figure 5

10.1

8.4

V

FILT

VFILT

V

FILTL

V

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NCN5130

Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

FIXED DC−DC CONVERTER

V

VIN

Input Voltage

4.47

3.13

33

V

IN

V

DD1

VDD1

Output Voltage

3.3

40

3.47

V

= 25 V, I

= 40 mA,

IN

DD1

V

Output Voltage Ripple

Overcurrent Threshold

mV

mA

DD1_rip

DD1_lim

L1 = 220 mH

I

R = 1 W, see Figure 13

−100

−200

2

V

= 25 V, I

= 35 mA,

in

DD1

Power Efficiency

(DC Converter Only)

L = 220 mH (1.26 W ESR),

h

90

%

1

VDD1

see Figure 12

See Figure 18

R

of power switch

of flyback switch

8

4

W

V

DS(on)_p1

DS(on)_n1

DS(on)

V

DD1M

VDD1M

Input voltage VDD1M−pin

3.57

ADJUSTABLE DC−DC CONVERTER

V

VIN

Input Voltage

V

+1

33

21

V

IN

DD2

V

DD2

Output Voltage

V

≥ V

DD2

1.2

IN

V

Undervoltage release level

Undervoltage trigger level

rising, see Figure 6

falling, see Figure 6

0.9xV

VDD2

DD2H

DD2

V

DD2L

0.8xV

DD2

= 25 V, V

= 40 mA, L2 = 220 mH

= 3.3 V,

IN

DD2

V

Output Voltage Ripple

Overcurrent Threshold

40

90

mV

mA

DD2_rip

DD2_lim

I

DD2

I

R = 1 W, see Figure 13

−100

−250

3

V

I

= 25 V, V

= 35 mA, L = 220 mH

= 3.3 V,

in

DD2

Power Efficiency

(DC Converter Only)

h

%

DD2

2

VDD2

(1.26 W ESR), see Figure 13

R

of power switch

of flyback switch

See Figure 18

8

4

W

DS(on)_p2

DS(on)_n2

DS(on)

See Figure 18

V

VDD2MC Input voltage VDD2MC−pin

VDD2MV Input Resistance VDD2MV−pin

Half−bridge leakage

21.1

V

DD2M

R

VDD2M

1

MW

mA

I

20

22

leak,vsw2

V20V REGULATOR

V

V20V Output Voltage

I

< I

, V ≥ 21 V

FILT

18

20

1.04

V

mA

A

20V

20V_lim

R > 250 kW

6

V20V Output Current

Limitation Step

10 kW < R < 93.1 kW

50.8/R

2.29

DI

6

20V, STEP

R < 2 kW

mA

A

6

R > 250 kW

4.34

5.68

8.00

6

V20V

V20V Output Current Limitation

(for V20VCLIMIT[2:0] = 100)

10 kW < R < 93.1 kW

132.0/R 273.4/R 392.0/R

6 6 6

I

6

20V_lim

R < 2 kW

9.52

14.2

13.2

12.37

15.0

14.0

1.0

16.00

15.8

14.8

mA

V

6

V

V20V Undervoltage release level

V20V Undervoltage trigger level

V20V Undervoltage hysteresis

V

rising, see Figure 7

falling, see Figure 7

20VH

20V

V

20VL

20V

V

= V

– V

20VL

V

20V_hyst

20VH

XTAL OSCILLATOR

XTAL1,

V

Voltage on XTAL−pin

V

DDD

V

XTAL

XTAL2

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NCN5130

Table 4. DC PARAMETERS The DC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified. Convention: currents flowing in the circuit are defined as positive.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

FAN−IN CONTROL

FANIN shorted to GND,

I

FANIN

Pull−Up Current FANIN−pin

10

20

40

mA

pu,fanin

Pull−up connected to V

AUX

DIGITAL INPUTS

SCK/UC2,

V

Logic Low Threshold

Logic High Threshold

0

0.7

V

IL

SDI/RXD,

CSB/UC1,

TREQ,

2.65

V

DDD

IH

MODE1,

MODE2,

XSEL,

XCLKC,

XTAL2

SCK/UC2−, SDI/RXD− and

CSB/UC1 pin excluded. Only valid

in Normal State.

R

Internal Pull−Down Resistor

5

10

28

kW

DOWN

DIGITAL OUTPUTS

V

Logic low output level

Logic high output level

0

0.4

V

SCK/UC2,

SDO/TXD,

CSB/UC1,

XCLK,TRIG

OL

V

−

DDD

0.45

V

OH

V

DDD

SCK/UC2,

XCLK,TRIG

8

mA

I

L

Load Current

SDO/TXD,

CSB/UC1

4

V

Logic low level open drain

Internal Pull−up Resistor

I

OL

= 4 mA

0.4

80

V

OL

SAVEB,

RESETB

R

20

40

kW

up

ANALOG OUTPUT

PV

Analog output division ratio for V

0.067

0.071

0.086

0.438

0.950

14.0

0.071

0.075

0.091

0.462

1.000

20.9

0.075

0.079

0.096

0.485

1.050

28.8

BUS

FILT

BUS

FILT

20V

PV

20V

DDA

DD2

BUS

PV

DDA

DD2MV

ANAOUT

PI

Analog output conversion ratio for I

V/A

mV/K

V

BUS

PT

Analog output conversion ratio for T

−4

J

junction

VTJ

Analog output offset for T

at 300K

1.309

OFF

junction

V

OFF

Analog output offset voltage

−12

12

mV

Time between writing Analog Control Register 1 and stable ANAOUT

voltage (<1 nF capacitive load)

t

33

ms

SW,ANA

TEMPERATURE MONITOR

Thermal Warning

T

TW

Rising temperature (See Figure 8)

See Figure 8

105

130

5

115

140

11

125

150

15

°C

T

Thermal shutdown

Thermal Hysteresis

TSD

Hyst

T

DT

Delta T

and T

See Figure 8

21.7

TSD

TW

PACKAGE THERMAL RESISTANCE VALUE

Simulated Conform

JEDEC JESD−51, (2S2P)

30

60

K/W

Thermal Resistance

R ,

q

ja

Junction−to−Ambient

Simulated Conform

JEDEC JESD−51, (1S0P)

Thermal Resistance

Junction−to−Exposed Pad

R ,

0.95

q

jp

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9

NCN5130

Table 5. AC PARAMETERS The AC parameters are given for a device operating within the Recommended Operating Conditions

unless otherwise specified.

Symbol

Pin(s)

Parameter

Remark/Test Conditions

Min

Typ

Max

Unit

POWER SUPPLY

t

VBUS1

VBUS1 filter time

See Figure 4

2

ms

BUS_FILTER

FIXED DC−DC CONVERTER

t

Rising slope at VSW1−pin

Falling slope at VSW1−pin

0.45

0.6

V/ns

VSW1_rise

VSW1

t

VSW1_fall

ADJUSTABLE DC−DC CONVERTER

t

Rising slope at VSW2−pin

Falling slope at VSW2−pin

0.45

0.6

V/ns

VSW2_rise

VSW2

t

VSW2_fall

XTAL OSCILLATOR

f

XTAL1, XTAL2 XTAL Oscillator Frequency

16

MHz

XTAL

WATCHDOG

Prohibited Watchdog

Acknowledge Delay

t

See Watchdog, p22

2

33

ms

WDPR

WDTO

t

Watchdog Timeout Interval

Selectable over UART or SPI

33

524

Watchdog Timeout Interval

Accuracy

t

=Xtal accuracy

WDTO_acc

t

Watchdog Reset Delay

Reset Duration

0

8

ns

WDRD

t

ms

RESET

MASTER SERIAL PERIPHERAL INTERFACE (MASTER SPI)

2

8

ms

t

SPI Clock period

sck

SPI Baudrate depending on

configuration input bits (see

Interface Mode, p26). Tolerance

is equal to Xtal oscillator

tolerance.

SCK

t

SPI Clock high time

t

/ 2

SCK_HIGH

SCK

t

SPI Clock low time

SCK_LOW

See also Figure 10

t

SPI Data Input setup time

SPI Data Input hold time

SPI Data Output valid time

125

ns

SDI_SET

SDI_HOLD

SDI

t

SDO

C = 20 pF, See Figure 10

L

100

SDO_VALID

0.5 x

t

SPI Chip Select high time

SPI Chip Select setup time

SPI Chip Select hold time

CS_HIGH

t

SCK

0.5 x

t

CSB

See Figure 10

See Figure 11

CS_SET

t

SCK

0.5 x

t

CS_HOLD

t

SCK

t

TREQ low time

TREQ high time

TREQ setup time

TREQ hold time

125

ns

TREQ_LOW

t

TREQ_HIGH

TREQ

t

TREQ_SET

t

TREQ_HOLD

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

Baudrate depending on

configuration input pins (see

Interface Mode, p26).

Tolerance is equal to tolerance

of Xtal oscillator tolerance.

19200

38400

Baud

f

TXD, RXD

UART Interface Baudrate

UART

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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10

NCN5130

V_BUS

V_BUSH

V_BUSL

t_{BUS_FILTER}

t

<VBUS>

Comments:

<VBUS> is an internal signal which can be verified with the Internal State Service.

Figure 4. Bus Voltage Undervoltage Threshold

V_FILT

V_FILTH

V_FILTL

t

<VFILT>

Comments:

<VFILT> is an internal signal which can be verified with the System State Service

Figure 5. VFILT Undervoltage Threshold

V_DD2

V_DD2H

V_DD2L

t

<VDD2>

Comments:

<VDD2> is an internal signal which can be verified with the System State Service

Figure 6. VDD2 Undervoltage Thresholds

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11

NCN5130

V_20V

V_20VH

V_20VL

t

<V20V>

Comments:

<V20V> is an internal signal which can be verified with the System State Service.

Figure 7. V20V Undervoltage Threshold levels

T

T_TSD

nT

T_TW

t

<TW>

SAVEB

RESETB

Analog State

Comments:

- <TW> is an internal signal which can be verified with the System State Service.

- No SPI/UART communication possible when RESETB is low!

- It's assumed all voltage supplies are within their operating condition.

Figure 8. Temperature Monitoring Levels

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12

NCN5130

RESETB

<WDEN>

t

t_reset

Re−enable

Watchdog

Enable

Watchdog

t_WDRD

>t_WDPRand <t_WDTO

vt_WDPRand wt _WDTO

WD Timer

t _WDTO

t _WDPR

Remarks:

− WD Timer is an internal timer

− t_WDTO= <WDT[3:0]>

− <WDEN> and <WDT[3:0]> are Watchdog Register bits

Figure 9. Watchdog Timing Diagram

CS

CLK

DI

DO

t_{SDI_SET}

t_{CS _SET}

t_{SDI _HOLD}

t_{SCK _HIGH}

t_{CS _HIGH}

t_{SDO_VALID}

t_{SCK _LOW}

t_SCK

t_{CS_HOLD}

Figure 10. SPI Bus Timing Diagram

CS

CLK

DI

LSB

1

2

7

DO

Dummy

TREQ

t_{TREQ_HOLD}

t_{TREQ _SET}

t_{TREQ _LOW}

t_{TREQ_HIGH}

Figure 11. TREQ Timing Diagram

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13

NCN5130

TYPICAL APPLICATION SCHEMATICS

RESETb

SAVEb

uC CLK

R

6

C

9

8

3.3

X

1

C

5

VCC

GND

3.3

C

6

VSSA

VBUS2

TXO

VDDD

1

30

29

28

27

26

25

24

23

22

21

SCK/UC2

SDO/TXD

SDI/RXD

CSB/UC1

TREQ

D

2

1

R

1

TxD

RxD

3

A

CCP

4

C

CAV

1

5

NCN5130

VBUS1

CEQ1

6

MODE2

MODE1

TRIG

7

D

C

CEQ2

VFILT

V20V

2

8

9

XCLKC

10

C

7

3

4

3.3

B

C

10

R

L

1

2

Figure 12. Typical Application Schematic, 9−bit UART Mode (19200bps), Single Supply, External FANIN Configuration

and 8 MHz Microcontroller Clock Signal

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14

NCN5130

TYPICAL APPLICATION SCHEMATICS

RESETb

SAVEb

uC CLK

C

8

9

3.3

X

1

V2

C

5

VCC

VCC2

GND

3.3

C

6

VSSA

VBUS2

TXO

VDDD

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

SCK

SDO

SDI

SCK/UC2

SDO/TXD

SDI/RXD

CSB/UC1

TREQ

D

R

1

A

CCP

C

CAV

1

NCN5130

VBUS1

CEQ1

CEQ2

VFILT

V20V

SCB

TREQ

MODE2

MODE1

TRIG

C

D

2

XCLKC

C

7

3

4

3.3

B

C

10

L

2

L

1

R

2

R

4

5

R

V2

3

C

11

Figure 13. Typical Application Schematic, SPI (500 kbps), Dual Supply, 10 mA Bus Current Limit and 0.5 mA/ms

Bus Current Slopes, 16 MHz Clock for Microcontroller

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15

NCN5130

TYPICAL APPLICATION SCHEMATICS

RESETb

SAVEb

3.3

VCC

GND

C₅

3.3

C₆

VSSA

VBUS2

TXO

VDDD

SCK/UC2

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

D₁

R₁

TxD

RxD

SDO/TXD

SDI/RXD

CSB/UC1

TREQ

A

CCP

C₁

CAV

NCN5130

VBUS1

CEQ1

CEQ2

VFILT

V20V

MODE2

MODE1

TRIG

C₂

D₂

XCLKC

C₃

C₄

C₇

3.3

B

C₁₀

L₁

R₂

Figure 14. Typical Application Schematic, Analog Mode, Single Supply, 20 mA Bus Current Limit and 1.0 mA/ms

Bus Current Slopes

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16

NCN5130

Table 6. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Comp.

Function

Min

42.3

198

80

Typ

47

Max

51.7

242

Unit

nF

mF

nF

mF

Remarks

50 V, Ceramic

35 V

Notes

C

AC coupling capacitor

9

1

2

3

4

5

6

7

Equalization capacitor

220

100

1

Capacitor to average bus DC voltage

Storage and filter capacitor VFILT

VDDA HF rejection capacitor

VDDD HF rejection capacitor

Load Capacitor V20V

120

9

12.5

80

4000

9, 17

6.3 V, Ceramic

35 V, Ceramic, ESR < 2 W

80

14,

15, 17

C , C

Parallel capacitor X−tal

Load capacitor VDD1

8

10

27

1

12

pF

mF

W

6.3 V, Ceramic

6.3 V, Ceramic, ESR < 0.1 W

Ceramic, ESR < 0.1 W

1 W

10

8

9

C

10

C

11

Load capacitor VDD2

8

11

9

R

Shunt resistor for transmitting

DC1 sensing resistor

24.3

0.47

0

29.7

10

1

2

3

4

5

R

W

1/16 W

R

DC2 sensing resistor

1

10

W

1/16 W

Voltage divider to specify VDD2

1/16 W, see p19 for

calculating the exact value

W

0

1000

kW

mH

L , L

DC1/DC2 inductor

220

SS16

1

2

D

Reverse polarity protection diode

Voltage suppressor

12

1

2

1

1SMA40CA

FA-238

X

Crystal oscillator

13

16

R

Fan-In Programming Resistor

10

93.1

kW

1% precision

6

9. Component must be between minimum and maximum value to fulfill the KNX requirement.

10.Actual capacitor value depends on X1. If a crystal oscillator is chosen, the capacitors need to be chosen in such a way that the frequency

equals 16 MHz. Capacitors are not required if external clock signal is supplied.

11. Voltage of capacitor depends on VDD2 value defined by R4 and R5. See p16 for more details on defining VDD2 voltage value.

12.Reverse polarity diode is mandatory to fulfill the KNX requirement.

13.A clock signal of 16 MHz (50 ppm or less) is mandatory to fulfill the KNX requirements. Or a crystal oscillator of 16 MHz, 50 ppm is used

(C8 and C9 need to be of the correct value based on the crystal datasheet), or an external 16 MHz clock is used.

14.It’s allowed to short this pin to VFILT-pin

15.High capacitor value might affect the start up time

16.If no resistor connected or pulled up to 3.3 V the KNX device should be certified as a bus load of 10 mA. If shorted to ground the KNX device

should be certified as a bus load of 20 mA. If a resistor to ground is connected between 10 kW and 93.1 kW the device should be certified

as a bus load of 10 mA (42.2 k), 20 mA (20 k), 30 mA (13.3 k) or 40 mA (10 k).

17.Total charge of C4 and C7 may not be higher than 121 mC to fulfill the KNX requirement.

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17

NCN5130

ANALOG FUNCTIONAL DESCRIPTION

Because NCN5130 follows the KNX standard only a brief

The active pulse is produced by the transmitter and is

description of the KNX related blocks is given in this

datasheet. Detailed information on the KNX Bus can be

found on the KNX website (www.knx.org) and in the KNX

standards.

ideally rectangular. It has a duration of 35 ms and a depth

between 6 and 9 V (V ). Each active pulse is followed by

act

an equalization pulse with a duration of 69 ms. The latter is

an abrupt jump of the bus voltage above the DC level

followed by an exponential decay down to the DC level. The

KNX Bus Interfacing

equalization pulse is characterized by its height V and the

eq

Each bit period is 104 ms. Logic 1 is simply the DC level

of the bus voltage which is between 20 V and 33 V. Logic 0

is encoded as a drop in the bus voltage with respect to the DC

level. Logic 0 is known as the active pulse.

voltage V reached at the end of the equalization pulse.

end

See the KNX Twisted Pair Standard (KNX TP1−256) for

more detailed KNX information.

V_BUS

DC Level

Active Pulse

Equalization Pulse

t

35ms

69ms

104ms

1

0

Figure 15. KNX Bus Voltage versus Digital Value

KNX Bus Transmitter

this a large filter capacitor is used on the VFILT−pin. Abrupt

load current steps are absorbed by the filter capacitor.

Long−term stability requires that the average bus coupler

input current is equal to the average (bus coupler) load

The purpose of the transmitter is to produce an active

pulse (see Figure 15) between 6 V and 9 V regardless of the

bus impedance (Note 1). In order to do this the transmitter

will sink as much current as necessary until the bus voltage

drops by the desired amount.

current. This is shown by the parameter DI

/Dt, which

coupler

indicates the bus current slope limit. The bus coupler will

also limit the current to a maximum of I

. At

to

coupler_lim

KNX Bus Receiver

startup, this current limit is increased to I

coupler_lim,startup

The receiver detects the beginning and the end of the

active pulse. The detection threshold for the start of the

active pulse is −0.45 V (typ.) below the average bus voltage.

The detection threshold for the end of the active pulse is

−0.2 V (typ.) below the average bus voltage giving a

hysteresis of 0.25 V (typ.).

allow for fast charging of the VFILT bulk capacitance.

There are 4 conditions that determine the dimensioning of

the VFILT capacitor. First, the capacitor value should be

between 12.5 mF and 4000 mF to garantuee proper operation

of the part. The next requirement on the VFILT capacitor is

determined by the startup time of the system. According to

the KNX specification, the total startup time must be below

10 s. This time is comprised of the time to charge the VFILT

capacitor to 12 V (where the DCDC convertor becomes

operatonal) and the startup time of the rest of the system

Bus Coupler

The role of the bus coupler is to extract the DC voltage

from the bus and provide a stable voltage supply for the

purpose of powering the NCN5130. This stable voltage

supplied by the bus coupler is called VFILT, and will follow

the average bus voltage. The bus coupler also makes sure

that the current drawn from the bus changes very slowly. For

t . This gives the following formula:

startup,system

I_{coupler_Ilim,startup}

ǒ

Ǔ

C t 10 s * t_{startup,system}

V_FILTH

1. Maximum bus impedance is specified in the KNX Twisted Pair Standard

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18

NCN5130

The third limit on VFILT capacitor value is the required

and DC2 correctly, the voltage on the VIN−pin should be

capacitor value to filter out current steps DI

of the system

higher than the highest value of DC1 and DC2.

step

without going into reset.

Although both DC−DC converters are capable of

delivering 100 mA, the maximum current capability will not

always be usable. One always needs to make sure that the

KNX bus power consumption stays within the KNX

specification. The maximum allowed current for the DC−DC

converters and V20V regulator can be estimated as next:

2

DI_step

C u

ǒ

Ǔ

2 @ (V_BUS1* V_{coupler_drop}* V_FILTL) @ I_slope

The last condition on the size of VFILT is the desired

warning time t

between SAVEB and RESETB in case

warning

the bus voltage drops away. This is determined by the current

ǒ

Ǔ

V_BUS I_BUS* I_20V

ƪǒ

Ǔ

ǒ

Ǔƫ ^w 1

consumption of the system I

.

ǒ_t^system

Ǔ

(eq. 2)

2 V_DD1 I_DD1) V_DD2 I_DD2

_warning) t_busfilter

C u I_system

I

will be limited by the KNX standard and should be

BUS

ǒ_V

Ǔ

_BUS1* V_{coupler_drop}* V_FILTL

lower or equal to I

(see Table 4). Minimum V

is

coupler

BUS

20 V (see KNX standard). V

and V

can be found back

The bus coupler is implemented as a linear voltage

regulator. For efficiency purpose, the voltage drop over the

bus coupler is kept minimal (see Table 4).

DD1

DD2

in Table 4. I

, I

and I

must be chosen in a correct

DD1 DD2

20V

way to be in line with the KNX specification (Note 2).

Although DC2 can operate up to 21 V, it will not be

possible to generate this 21 V under all operating conditions.

See application note AND9135 for defining the optimum

inductor and capacitor of the DC−DC converters. When

using low series resistance output capacitors on DC2, it is

advised to split the current sense resistor as shown in

Figure 18 to reduce ripple current for low load conditions.

KNX Impedance Control

The impedance control circuit defines the impedance of

the bus device during the active and equalization pulses. The

impedance can be divided into a static and a dynamic

component, the latter being a function of time. The static

impedance defines the load for the active pulse current and

the equalization pulse current. The dynamic impedance is

produced by a block, called an equalization pulse generator,

that reduces the device current consumption (i.e. increases

the device impedance) as a function of time during the

equalization phase so as to return energy to the bus.

V20V Regulator

This is the 20 V low drop linear voltage regulator used to

supply external devices. As it draws current from VFILT,

this current is seen without any power conversion directly at

the VBUS1 pin.

The V20V regulator starts up by default but can be

disabled by a command from the host controller

(<V20VEN>, see Analog Control Register 0, p54). When

the V20V regulator is not used, no load capacitor needs to

be connected (see C7 of Figures 12, 13 and 14). Connect

V20V−pin with VFILT−pin in this case.

V20V regulator will only be enabled when VFILT−bit is

set (<VFILT>, see System Status Service, p37). The host

controller can also monitor the status of the regulator

(<V20V>, see System Status Service, p37). The 20 V

regulator has a current limit that depends on the FANIN

resistor value, and the value of bits 0−3

(V20VCLIMIT[0:2]) of the analog control register. In Table

4, the typical value of the current limit at startup is given as

Fixed and Adjustable DC−DC Converter

The device contains two DC−DC buck converters, both

supplied from VFILT.

DC1 provides a fixed voltage of 3.3 V. This voltage is used

as an internal low voltage supply (V

and V

) but can

DDA

DDD

also be used to power external devices (VDD1−pin). DC1 is

automatically enabled during the power−up procedure (see

Analog State Diagram, p23).

DC2 provides a programmable voltage by means of an

external resistor divider. It is not used as an internal voltage

supply making it not mandatory to use this DC−DC

converter (if not needed, tie the VDD2MV pin to VDD1, see

also Figure 12).

DC2 can be monitored (<VDD2>, see System Status

Service, p37), and/or disabled by a command from the host

controller (<DC2EN>, see Analog Control Register 0, p54).

DC2 will only be enabled when VFILT−bit is set (<VFILT>,

see System Status Service, p37). The status of DC2 can be

monitored (<VDD2>, see System Status Service, p37).

I

(V20VCLIMIT[0:2] initializes at 100). For each bit

20V_lim

difference, the current limit is adjusted up or down by DI

20

.

V,STEP

Xtal Oscillator

An analog oscillator cell generates the main clock of

16 MHz. This clock is directly provided to the digital block

to generate all necessary clock domains.

An input pin XSEL is foreseen to enable the use of a quartz

crystal (see Figure 16) or an external clock generator (see

Figure 17) to generate the main clock.

The voltage divider can be calculated as follows:

V_DD2* 1.2

R₄+ R₅

(eq. 1)

1.2

Both DC−DC converters make use of slope control to

improve EMC performance (see Table 5). To operate DC1

2. The formula is for a typical KNX application. It‘s only given as guidance and does not guarantee compliance with the KNX standard.

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19

NCN5130

XTAL2 34

XTAL1

XTAL2 34

XTAL1 35

OSC

Microcontroller

35

33

XSEL

32

21

VDD

33

21

32

XCLK

XCLKC

XCLK

XSEL

XCLKC

8 MHz @ XCLC = VSS

16 MHz @ XCLC = VDD

VDD

8 MHz @ XCLC = VSS

16 MHz @ XCLC = VDD

Figure 16. XTAL Oscillator

Figure 17. External Clock Generator

Transmit Trigger

The XCLK−pin can be used to supply a clock signal to the

host controller. This clock signal can be switched off by a

command from the host controller (<XCLKEN>, see

Analog Control Register 0, p54).

After power−up, a 4 MHz (Note 3) clock signal will be

present on the XCLK−pin during Stand−By. When Normal

State is entered, a 8 or 16 MHz clock signal will be present

on the XCLK−pin. See also Figure 20. To output an 8 MHz

clock on the XCLK pin, the XCLKC pin must be pulled to

ground. When the XCLKC pin is pulled up to VDDD, the

XCLK pin will output a 16 MHz clock signal.

When Normal State is left and Stand−By State is re−entered

due to an issue different than an Xtal issue, the 8 or 16 MHz

clock signal will still be present on the XCLK−pin during the

Stand−By State. If however Stand−By is entered from

Normal State due to an Xtal issue, the 4 MHz clock signal

will be present on the XCLK−pin. See also Table 7.

When bit 3 of analog control register 0 is set, the TRIG−pin

will output a signal that goes high 1 bit time before the start

of a scheduled transmission, and goes low when the

transmission is complete or a collision is detected. This can

be used during development as verification of transmission.

Note that a scheduled transmission is a frame that is sent less

than t

(TODO s) after previous communication on

BUS,IDLE

the bus. When a frame is transmitted on a bus which has been

idle for a longer time, or an ACK/NACK/BUSY response is

sent, the transmission will start immediately after the trigger

goes high, and the time between trigger high and frame

transmission start will not be consistent.

RESETB− and SAVEB−pin

The RESETB signal can be used to keep the host

controller in a reset state. When RESETB is low this

indicates that the bus voltage is too low for normal operation

and that the fixed DC−DC converter has not started up. It

could also indicate a Thermal Shutdown (TSD). The

RESETB signal also indicates if communication between

host and NCN5130 is possible.

FANIN−pin

The FANIN−pin defines the maximum allowed bus

current and bus current slopes. If the FANIN−pin is kept

floating, pulled up to V , or pulled down with a resistance

DD

The SAVEB signal indicates correct operation. When SAVEB

goes low, this indicates a possible issue (loss of bus power or

too high temperature) which could trigger the host controller

to save critical data or go to a save state. SAVEB goes low

immediately when VFILT goes below 14 V (due to sudden

large current usage) or after 2 ms when VBUS goes below

20 V. RESETB goes low when VFILT goes below 12 V.

RESETB− and SAVEB−pin are open−drain pins with an

higher than 250 kW, NCN5130 will limit the KNX bus

current slopes to 0.5 mA/ms at all times. NCN5130 will also

limit the KNX bus current to 30 mA during start−up. During

normal operation, NCN5130 is capable of taking 10.6 mA

(= I

) from the KNX bus for supplying external loads

coupler

(DC1, DC2 and V20V).

If the FANIN−pin is pulled to ground with a resistance

smaller than 2 kW the operation is similar as above with the

exception that the KNX bus current slopes will be limited to

1 mA/ms at all times, the KNX bus current will be limited

internal pull−up resistor to V

.

DDD

Voltage Supervisors

to 60 mA during start−up and up to 20.5 mA (I

) can be

NCN5130 has different voltage supervisors monitoring

VBUS, VFILT, VDD2 and V20V. The general function of a

voltage supervisor is to detect when a voltage is above or

below a certain level. The levels for the different voltages

monitored can be found back in Table 4 (see also Figures 4,

5, 6 and 7).

The status of the voltage supervisors can be monitored by

the host controller (see System Status Service, p37).

Depending on the voltage supervisor outputs, the device

can enter different states (see Analog State Diagram, p23).

coupler

taken from the KNX bus during normal operation. When the

FANIN−pin is pulled to ground with a resistance between

10 kW and 93.1 kW, the current slope and current limit are

defined by the values from Table 4. For different resistor

values, the typical current limit can be approximated by the

formula Ibus = 0.0004 + 434/R6 A. Using different resistor

values is, however, not recommended.

Definitions for Start−Up and Normal Operation (as given

above) can be found in the KNX Specification.

3. The 4 MHz clock signal is internally generated and will be less accurate as the crystal generated clock signal of 8 or 16 MHz.

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20

NCN5130

VIN

From VFILT

P₁

N₁

L₁

1Ω

VSW1

Switch

Controller

VDD1 = 3.3V

F

10μ

VSS1

VDD1M

VDD1

COMP

P₂

L₂

0.47Ω

VSW2

VSS2

Switch

Controller

VDD2 = 1.2V – 20V

10μF

N₂

R₄

VDD2MV

VDD2MC

VDD2

COMP

R₅

NCN5130

Figure 18. Fixed (VDD1) and Adjustable (VDD2) DC−DC Converter

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21

NCN5130

Table 7. STATUS OF SEVERAL BLOCKS DURING THE DIFFERENT (ANALOG) STATES

State

Reset

Osc

Off

XCLK

Off

VDD1

Off

VDD2/V20V

Off

SPI/UART

Inactive

Active

KNX

Inactive

Start−Up

Off

Start−up

On

Off

Stand−By (Note 18)

Off

4 MHz

Start−Up

Inactive

(Note 23)

Stand−By (Note 19)

Normal

On

(Note 21)

On

(Note 21)

On

On (Note 22)

On

Active

Inactive

(Note 23)

On

(Note 20)

Active

18.Only valid when entering Stand−By from Start−Up State.

19.Only valid when entering Stand−By from Normal State.

20.8 MHz or 16 MHz depending on XCLKC.

21.4 MHz signal if Stand−By state was entered due to oscillator issue. Otherwise 8 MHz or 16 MHz clock signal.

22.Only operational if Stand−By state was not entered due to VDD2 or V20V issue.

23.Under certain conditions KNX bus is (partly) active. See Digital State Diagram for more details.

Temperature Monitor

Once this bit is set to ‘1’, the host controller needs to re−write

this bit to clear the internal timer before the Watchdog

Timeout Interval expires (Watchdog Timeout Interval =

<WDT>, see Watchdog Register, p54).

The device produces an over−temperature warning (TW)

and a thermal shutdown warning (TSD). Whenever the

junction temperature rises above the Thermal Warning level

(T ), the SAVEB−pin will go low to signal the issue to the

TW

In case the Watchdog is acknowledged too early (before

host controller. Because the SAVEB−pin will not only go

low on a Thermal Warning (TW), the host controller needs

to verify the issue by requesting the status (<TW>, see

System Status Service, p37). When the junction temperature

is above TW, the host controller should undertake actions to

reduce the junction temperature and/or store critical data.

When the junction temperature reaches Thermal

t

(t

) or not within the Watchdog Timeout Interval

WDPR

), the RESETB−pin will be made low (= reset host

WDTO

controller).

Table 8 gives the Watchdog timings t

and t

.

WDPR

WDTO

Details on <WDT> can be found in the Watchdog Register,

p54.

Table 8. WATCHDOG TIMINGS

Shutdown (T ), the device will go to the Reset State. The

TSD

Thermal Shutdown will be stored (<TSD>, see Analog

Status Register, p56) and the analog and digital power

supply will be stopped (to protect the device). The device

will stay in the Reset State as long as the temperature stays

WDT[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

t

[ms]

t

[ms]

WDPR

WDTO

33

2

66

4

6

8

98

above T

.

TSD

If the temperature drops below T , Start−Up State will

TSD

131

164

197

229

262

295

328

360

393

426

459

492

524

be entered (see also Figure 19). At the moment VDD1 is

back up and the OTP memory is read, Stand−By State will

be entered and RESETB will go high. The Xtal oscillator

will be started. Once the temperature has dropped below

10

12

14

16

18

20

23

25

27

29

30

31

T

and all voltages are high enough, Normal State will be

TW

entered. SAVEB will go high and KNX communication is

again possible.

The TW−bit will be reset at the moment the junction

1000

1001

1010

1011

1100

1101

1110

temperature drops below T . The TSD−bit will only be

TW

reset when the junction temperature is below T

and the

TSD

<TSD> bit is read (see Analog Status Register, p56).

Figure 8 gives a better view on the temperature monitor.

Watchdog

NCN5130 provides a Watchdog function to the host

controller. The Watchdog function can be enabled by means

of the WDEN−bit (<WDEN>, see Watchdog Register, p54).

1111

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22

NCN5130

Analog State Diagram

oscillator has started, no Thermal Warning (TW) or Thermal

Shutdown (TSD) was detected and the VBUS−, VFILT−,

VDD2− and V20V−bits are set, the Normal State will be

entered and SAVEB−pin will go high.

The analog state diagram of NCN5130 is given in

Figure 19. The status of the oscillator, XCLK−pin, DC−DC

converters, V20V regulator, serial and KNX

communication during the different (analog) states is given

in Table 7.

Figure 21 gives a detailed view on the shut−down

behavior. If the KNX bus voltage drops below V

for

BUSL

Figure 20 gives a detailed view on the start−up behavior

of NCN5130. After applying the bus voltage, the filter

capacitor starts to charge. During this Reset State, the

more than t

, the VBUS−bit will be reset (<VBUS>,

bus_filter

see System Status Service, p37) and the Standy−By State is

entered. SAVEB will go low to signal this. When VFILT

current drawn from the bus is limited to I

(for details

drops below V , DC2 and the V20V regulator will be

FILTL

coupler

see the KNX Standards). Once the voltage on the filter

capacitor reaches 10 V (typ.), the fixed DC−DC converter

(powering VDDA) will be enabled and the device enters the

switched off. When VFILT drops below 6.5 V (typ), DC1

will be switched off and V drops below 2.8 V (typ.) the

device goes to Reset State (RESETB low).

DD1

Start−Up State. When V

gets above 2.8 V (typ.), the

DD1

Analog Output

OTP memory is read out to trim some analog parameters

(OTP memory is not accessible by the user). When done, the

Stand−By State is entered and the RESETB−pin is made

A multiplexed analog signal is available on the

ANAOUT−pin for monitoring signal levels. The signal read

out on this pin can be configured through the Analog Output

Control bits (<ANAOUTCTRL>, see Analog Control

Register 1, p 52).

high. If at this moment V

is above V

, the VBUS−bit

BUS

BUSH

will be set (<VBUS>, see System Status Service, p37). After

aprox. 2 ms the Xtal oscillator will start. When V is

FILT

above V

DC2 and V20V will be started. When the Xtal

FILTH

Reset

RESETB = ‘0’

SAVEB = ‘0’

V_FILT> 12V

and

Temp < TSD

Enable DC1

Disable DC1

V_FILT< 6.5V

Start−Up

RESETB = ‘0’

SAVEB = ‘0’

Disable DC1, DC2 and V20V

V_DDAOK

and

OTP read done

and clock present

Disable DC2 and V20V

V_FILT< V_FILTL

Enable DC2 and V20V

V_FILT> V_FILTH

V_FILT< 6.5V

Stand−By

RESETB = ‘1’

SAVEB = ‘0’

<TSD> = ‘1’

or

V_DDAnOK

Disable DC1

<TSD> = ‘1’

or

V_DDAnOK

<TW> = ‘0’ and <XTAL> = ‘1’ and

<VBUS> = ‘1’ and <VFILT> = ‘1’ and

<VDD2> = ‘1’ and <V20V> = ‘1’

<TW> = ‘1’ or <XTAL> = ‘0’ or

<VBUS> = ‘0’ or <VFILT> = ‘0’ or

<VDD2> = ‘0’ or <V20V> = ‘0’

Normal

RESETB = ‘1’

SAVEB = ‘1’

Remarks:

− <TW>, <XTAL>, <VBUS>, <VFILT>, <VDD2> and <V20V> are internal status bits which can be verified with the System State Service.

− <TSD> is an internal signal indicating a Thermal Shutdown. This internal signal cannot be read out.

− Although Reset State could be entered from Normal State on a TSD, Stand−By State will be entered first due to a TW.

Figure 19. Analog State Diagram

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23

NCN5130

V_BUS

V_FILT

V_BUSH

V_FILTH

12V

I_BUS

I_{coupler_lim,startup}

V_DD1

2.8V

V_XTAL

Xtal Oscillator

2ms

<VBUS>

<VFILT>

V_DD2

0.9 x V_DD2

<VDD2>

V_20V

V_20VH

<V20V>

RESETB

SAVEB

XCLK

t

Reset

Start−Up

Stand−By

Normal

Remarks:

VDD1 directly connected to VDDA.

Figure 20. Start−Up Behavior

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24

NCN5130

V_BUS

V_FILT

V_BUSH

V_BUSL

V_FILTL

6.5V

I_BUS

V_DD1

2.8V

V_XTAL

Xtal Oscillator

t_{bus_filter}

<VBUS>

<VFILT>

V_DD2

0.9 x V_DD2

<VDD2>

V_20V

<V20V>

RESETB

SAVEB

XCLK

t

Normal

Stand-By

Normal

Stand-By

Reset

Remarks:

VDD1 directly connected to VDDA.

Figure 21. Shut−Down Behavior

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25

NCN5130

Interface Mode

The device can communicate with the host controller by

means of a UART interface or an SPI interface. The

selection of the interface is done by the pins MODE1,

MODE2, TREQ, SCK/UC2 and CSB/UC1.

Table 9. INTERFACE SELECTION

TREQ

MODE2

MODE1

SCK/UC2

CSB/UC1

SDI/RXD

SDO/TXD

Description

9−bit UART−Mode, 19200 bps

9−bit UART−Mode, 38400 bps

8−bit UART−Mode, 19200 bps

8−bit UART−Mode, 38400 bps

Analog Mode

0

1

0

1

0

1

RXD

TXD

0

1

0

1

DC2EN

V20VEN

Driver

SDI

Receiver

SDO

TREQ

SPI Master, 125 kbps

SCK (out)

CSB (out)

SPI Master, 500 kbps

NOTE: X = Don‘t Care

UART Interface

The UART interface is selected by pulling pins TREQ,

MODE1 and MODE2 to ground. Pin UC2 is used to select

the UART Mode (‘0’ = 9−bit, ‘1’ = 8−bit) and pin UC1 is

used to select the baudrate (‘0’ = 19200 bps, ‘1’ =

38400 bps). The UART interface allows full duplex,

asynchronous communication.

The difference between 8−bit mode and 9−bit mode is that

in 9−bit an additional parity bit is transmitted. This parity bit

is used as an even parity bit (with exception of the internal

register read and write services where the parity bit is

meaningless and should be ignored). However, when the

NCN5130 detects an acceptance window error or pulse

duration error on the KNX bus, the parity bit is also encoded

to indicate an error in the byte. In 8−bit mode one extra

service is available (U_FrameState.ind). The SDI/RXD−pin

is the NCN5130 UART receive pin and is used to send data

from the host controller to the device. Pin SDO/TXD is the

NCN5130 UART transmit pin and is used to transmit data

between the device and the host controller. Figure 12 gives

an UART application example (9−bit, 19200 bps). Data is

transmitted LSB first.

Start

(= 0)

Stop

(= 1)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 22. 8−bit UART Mode

Start

(= 0)

Stop

(= 1)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Parity

Figure 23. 9−bit UART Mode

One special UART Mode is foreseen called Analog Mode.

When this mode is selected (TREQ = ‘1’, MODEx = ‘0’) an

immediate connection is made with the KNX transmitter

receiver (see Figure 24). Bit level coding/decoding has to be

done by the host controller. Keep in mind that the signals on

the SDI/RXD− and SDO/TXD−pin are inverted. Figure 14

gives an Analog Mode application example. In Analog

Mode, the UC1 and UC2 pins are used to enable or disable

the 20 V regulator and DC2 controller. When pulled low,

these blocks are enabled. When one of these pins is pulled

to VDDD, the respective block is disabled. When using the

device in Analog Mode, no clock needs to be provided to the

device.

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26

NCN5130

CEQ1

CEQ2

VFILT

VDDA VSSA

VDDD VSSD

Bus Coupler

CAV

SCK/UC2

Impedance

Control

VBUS1

SDI/RXD

SDO/TXD

Receiver

CSB/UC1

CCP

TREQ (TREQ = 1)

NCN5130

MODE1

MODE2

TXO

VBUS2

Transmitter

VIN

VSW1

VDD1M

VDD1

VSS1

Fan−In

Control

FANIN

V20V

DC/DC

Converter 1

20V LDO

OSC

RC

Osc

POR

OSC

XTAL1

XTAL2

VSW2

VDD2MC

VDD2MV

VDD2

TW/

TSD

DC/DC

Converter 2

UVD

XSEL

VSS2

Diagnostics

XCLKC

XCLK

ANAOUT

SAVEB RESETB

Figure 24. Analog UART Mode

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27

NCN5130

SPI Interface

The SPI interface allows full duplex synchronous

communication between the device and the host controller.

The interface operates in Mode 0 (CPOL and CPHA = ‘0’)

meaning that the data is clocked out on the falling edge and

sampled on the rising edge. The LSB is transmitted first.

The SPI interface is selected by MODE1− and

MODE2−pin. The baudrate is determined by which

MODE−pin is pulled high (MODE1 pulled high = 125 kbps,

MODE2 pulled high = 500 kbps).

0

1

2

3

4

5

6

7

CSB

SCK

SDI

LSB

1

2

3

4

5

6

MSB

SDO

Figure 25. SPI Transfer

During SPI transmission, data is transmitted (shifted out

serially) on the SDO/TXD−pin and received (shifted in

serially) on the SDI/RXD−pin simultaneously. SCK/UC2 is

set as output and is used as the serial clock (SCK) to

synchronize shifting and sampling of the data on the SDI−

and SDO−pin. The speed of this clock signal is selectable

(see Table 9). The slave select line (CSB/UC1−pin) will go

low during each transmission allowing to selection the host

controller (CSB−pin is high when SPI is in idle state).

SDO/TXD

MOSI

SDI/RXD

MISO

Shift Register

SCK/UC2

SCLK

CSB/UC1

SS

Control

NCN5130

Host Controller

Figure 26. SPI Master

In an SPI network only one SPI Master is allowed (in this

case NCN5130). To allow the host controller to

communicate with the device the TREQ−pin can be used

(Transmit Request). When NCN5130 detects a negative

edge on TREQ, the device will issue dummy transmission

of 8 bits which will result in a transmission of data byte from

the host controller to the device. See Figure 11 for details on

the timings. See Figure 13 for an SPI application example.

CSB

SCK

SDI

0

1

2

3

4

5

6

7

0

1

2

3

4

Dummy

SDO

D

Start dummy transmission

TREQ

Figure 27. Transmission Request

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28

NCN5130

DIGITAL FUNCTIONAL DESCRIPTION

The implementation of the Data Link Layer as specified in the KNX standard is divided in two parts. All functions related

to communication with the Physical Layer and most of the Data Link Layer services are inside NCN5130, the rest of the

functions and the upper communication layers are implemented into the host controller (see Figure 28).

The host controller is responsible for handling:

• Checksum

• Parity

• Addressing

• Length

The NCN5130 is responsible for handling:

• Checksum

• Parity

• Acknowledge

• Repetition

• Timing

Digital State Diagram

The digital state diagram is given in Figure 29.

The current mode of operation can be retrieved by the host controller at any time (when RESETB−pin is high) by issuing

the U_SystemStat.req service and parsing back U_SystemStat.ind service (see System Status Service, p37).

Table 10. NCN5130 DIGITAL STATES

State

Explanation

RESET

Entered after Power On Reset (POR) or in response to a U_Reset.req service issued by the host controller. In this

state NCN5130 gets initialized, all features disabled and services are ignored and not executed.

POWER−UP /

POWER−UP

STOP

Entered after Reset State or when VBUS, VFILT or Xtal are not operating correctly (operation of VBUS, VFILT and

XTAL can be verified by means of the System Status Service, p37). Communication with KNX bus is not allowed.

U_SystemStat.ind can be used to verify this state (code 00).

SYNC

NCN5130 remains in this state until it detects silence on the KNX bus for at least 40 Tbits. Although the receiver of

NCN5130 is on, no frames are transmitted to the host controller.

U_SystemStat.ind can be used to verify this state (code 01).

STOP

This state is useful for setting−up NCN5130 safely or temporarily interrupting reception from the KNX bus.

U_SystemStat.ind can be used to verify this state (code 10).

NORMAL

In this state the device is fully functional. Communication with the KNX bus is allowed.

U_SystemStat.ind can be used to verify this state (code 11).

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29

NCN5130

7

6

5

4

3

Application Layer

Presentation Layer

Session Layer

Transport Layer

Network Layer

Logic Link Control

2

1

Data Link Layer

Media Access Control

Physical Layer

Figure 28. OSI Model Reference

Reset

POR or U_Reset.req

Initialize device

Deactivate all features

Send U_StopMode.ind

to host

U_StopMode .req

Power−Up

Power−Up Stop

U_ExitStopMode .req

Code: 00

KNX Rx

KNX Tx

=

off

KNX Rx = off

KNX Tx = off

< XTAL > = ‘1’

<XTAL> = ‘0’

or

<VBUS> = ‘0’

or

<XTAL > = ‘1’

and

<VBUS> = ‘1’

and

<XTAL> = ‘0’

or

<VBUS> = ‘0’

or

and

<VBUS> = ‘1’

and

<VFILT> = ‘1’

<VFILT> = ‘0’

<VFILT> = ‘1’

<VFILT> = ‘0’

<XTAL> = ‘0’

or

<VBUS> = ‘0’

Sync

Stop

U_ExitStopMode.req

Code: 01

Code: 10

KNX Rx

KNX Tx

=

on

off

KNX Rx

= off

or

KNX Tx = off

<VFILT> = ‘0’

U_StopMode.req

KNX bus idle for w40 Tbits

Send U _Reset.ind

to host

Send U_StopMode.ind

to host

U_StopMode.req and

no activity for w30 Tbits

Normal

Code: 11

KNX Rx

KNX Tx

=

on

Figure 29. Digital State Diagram

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30

NCN5130

Services

Execution of services depends on the digital state (Figure 29). Certain services are rejected if received outside the Normal

State. The following table gives a view of all services and there acceptance during the different digital states.

Table 11. ACCEPTANCE OF SERVICES

State

Normal

Stop

E

Sync

E

Power−Up

Bus Monitor

Service

U_Reset.req

U_State.req

U_SetBusy.req

E

I

E

I

E

I

E

I

U_QuitBusy.req

E

I

U_Busmon.req

E

I

U_SetAddress.req

U_SetRepetition.req

U_L_DataOffset.req

U_SystemStat.req

U_StopMode.req

U_ExitStopMode.req

U_Ackn.req

E

I

E

I

E

I

E

I

E

I

E

I

E

R

E

R

E

R

E

R

E

U_Configure.req

U_IntRegWr.req

U_IntRegRd.req

U_L_DataStart.req

U_L_DataCont.req

U_L_DataEnd.req

U_PollingState.req

I

E

I

E

R

E

R

E

I

NOTE:

Bus Monitor state is not a separate state. It is applied on top of Normal, Stop, Sync or Power−Up State.

Legend: E = service is executed

I = service is ignored (not executed and no feedback sent to the host controller)

R = service is rejected (not executed, protocol error is sent back to the host controller through U_State.ind)

See Internal Register Read Service (p39) for limitations of U_IntRegRd.req

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31

NCN5130

Table 12. SERVICES FROM HOST CONTROLLER

Control Field

Extra Following

Bytes

Total

Bytes

7

6

5

4

3

2

1

0

Service Name

Hex

Remark

INTERNAL COMMANDS – DEVICE SPECIFIC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

U_Reset.req

01

02

03

04

05

F1

1

4

U_State.req

U_SetBusy.req

U_QuitBusy.req

U_Busmon.req

U_SetAddress.req

AddrHigh

AddrLow

X (don’t care)

1

0

1

0

1

0

1

0

1

0

i

1

i

0

i

U_SetRepetition.req

U_L_DataOffset.req

F2

RepCntrs

X (don’t care)

4

1

08−0C

iii = MSB byte

index (0…4)

0

1

0

1

n

0

1

b

1

0

1

a

U_SystemState.req

U_StopMode.req

U_ExitStopMode.req

U_Ackn.req

0D

0E

1

0F

10−17

n = nack

b = busy

a = addressed

0

1

p

c

m

U_Configure.req

18−1F

p = auto−polling

c = CRC−CCITT

m = frame end

with MARKER

1

0

1

0

1

0

1

0

1

s

0

s

a

s

a

s

U_IntRegWr.req

U_IntRegRd.req

U_PollingState.req

28−2B

38−3B

E0−EE

aa = address of

internal register

Data to be written

2

1

4

s = slot number

(0 … 14)

PollAddrHigh

PollAddrLow

PollState

KNX TRANSMIT DATA COMMANDS

1

0

i

0

i

0

i

0

i

0

i

0

i

U_L_DataStart.req

U_L_DataCont.req

80

Control Octet (CTRL)

2

81−BF

i = index (1…63)

Data octet (CTRLE,

SA, DA, AT, NPCI, LG,

TPDU)

0

1

l

U_L_DataEnd.req

47−7F

l = last index + 1

(7 … 63)

Check Octet (FCS)

2

With respect to command length, there are two types of services from the host controller:

• Single−byte commands: the control byte is the only data sent from the host controller to NCN5130.

• Multiple−byte commands: the following data byte(s) need to be handled according to the already received control byte.

With respect to command purpose there are two types of services from the host controller:

• Internal command: does not initiate any communication on the KNX bus.

• KNX transmit data command: initiates KNX communication

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32

NCN5130

Table 13. SERVICES TO HOST CONTROLLER

Control Field

Extra

Following

Bytes

Total

Bytes

7

6

5

4

3

2

1

0

Service Name

Remark

DLL (LAYER 2) SERVICES (DEVICE IS TRANSPARENT)

1

0

1

0

1

r

1

p1

0

p0

0

L_Data_Standard.ind

r = not repeated (‘1’) or

repeated L_Data frame (‘0’)

p1, p0 = priority

n

L_Data_Extended.ind

L_Poll_Data.ind

1

ACKNOWLEDGE SERVICES (DEVICE IS TRANSPARENT IN BUS MONITOR MODE)

x

z

x

0

x

0

1

0

1

L_Ackn.ind

L_Data.con

x = acknowledge frame

1

0

1

0

z = positive (‘1’) or negative

(‘0’) confirmation

CONTROL SERVICES – DEVICE SPECIFIC

0

1

U_Reset..ind

1

sc

re

te

pe

tw

U_State.ind

sc = slave collision

re = receive error

te = transmit error

pe = protocol error

tw = temperature warning

re

0

ce

b

te

1

res

c

0

1

0

1

U_FrameState.ind

U_Configure.ind

re = parity or bit error

ce = checksum or length

error

te = timing error

res = reserved

1

aa

ap

m

b = reserved

aa = auto−acknowledge

ap = auto−polling

c = CRC−CCITT

m = frame end with

MARKER

1

0

1

0

1

0

1

0

1

0

1

U_FrameEnd.ind

U_StopMode.ind

U_SystemStat.ind

1

2

V20V, VDD2,

VBUS, VFILT,

XTAL, TW,

Mode

Each data byte received from the KNX bus is transparently transmitted to the host controller. An exception is the

Acknowledge byte which is transmitted to the host controller only in bus monitoring mode. Other useful information can be

transmitted to the host controller by request using internal control services.

A detailed description of the services is given on the next pages. For all figures, the MSB bit is always given on the left side

no matter how the arrow is drawn.

Host Ctrl

NCN5130

KNX Bus

Figure 30. Bit Order of Services

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33

NCN5130

Reset Service

Reset the device to the initial state.

Host Ctrl

NCN5130

KNX Bus

U_Reset.req

0

1

U_Reset.ind

0

1

Figure 31. Reset Service

Remark: U_Reset.Ind will be send when entering Normal State (see Digital State Diagram, p29).

State Service

Get internal communication state of the device.

Host Ctrl

NCN5130

KNX Bus

U_State.req

0

1

0

1

U_State.ind

sc re te pe tw

1

Figure 32. State Service

sc (slave collision):

re (receive error):

‘1’ if collision is detected during transmission of polling state

‘1’ if corrupted bytes were sent by the host controller. Corruption involves incorrect parity (9−bit

UART only) and stop bit of every byte as well as incorrect control octet, length or checksum of frame

for transmission.

te (transceiver error): ‘1’ if error detected during frame transmission (sending ‘0’ but receiving ‘1’).

pe (protocol error): ‘1’ if an incorrect sequence of commands sent by the host controller is detected.

tw (thermal warning): ‘1’ if thermal warning condition is detected.

Set Busy Service

Activate BUSY mode.

During this time and when autoacknowledge is active (see Set Address Service p35), NCN5130 rejects the frames whose

destination address corresponds to the stored physical address by sending the BUSY acknowledge. This service has no effect

if autoacknowledge is not active.

Host Ctrl

NCN5130

KNX Bus

U_SetBusy.req

0

1

Figure 33. Set Busy Service

Remark: BUSY mode is deactivated immediately if the host controller confirms a frame by sending U_Ackn.req service.

Quit Busy Service

Deactivate the BUSY mode.

Restores back to the normal autoacknowledge behavior with ACK sent on the bus in response to addressing frame (only if

autoacknowledge is active). This service has no effect if autoacknowledge is not active or BUSY mode was not set.

Host Ctrl

NCN5130

KNX Bus

U_QuitBusy.req

0

1

0

Figure 34. Quit Busy Service

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34

NCN5130

Bus Monitor Service

Activate bus monitoring state.

In this mode all data received from the KNX bus is sent to the host controller without performing any filtering on Data Link

Layer. Acknowledge Frames are also transmitted transparently. This state can only be exited by the Reset Service (see p34).

Host Ctrl

NCN5130

KNX Bus

U_Busmon.req

0

x

0

1

0

x

1

x

KNX Message

x

KNX Message

x

KNX Message

x

KNX Message

x

0

x

0

x

0

x

0

1

Acknowledge

0

x

0

Acknowledge

0

x

U_Reset.req

0

U_Reset.ind

0

1

Figure 35. Bus Monitor Service

Remark:

x = don‘t care

Set Address Service

Sets the physical address of the device and activates the auto−acknowledge function.

NCN5130 starts accepting all frames whose destination address corresponds to the stored physical address or whose

destination address is the group address by sending IACK on the bus. In case of an error detected during such frame reception,

NCN5130 sends NACK instead of IACK.

When issued several times after each other, the first call will set the physical address and activate the auto−acknowledge.

Following calls will only set the physical address because auto−acknowledge is already activated.

NCN5130 confirms activation of auto−acknowledge function by sending the U_Configure.ind service to the host controller.

Host Ctrl

NCN5130

KNX Bus

U_SetAddress.req

1

x

0

1

0

1

x

1

Address High Byte

x

Address Low Byte

x

Dummy

x

U_Configure.ind

b

aa ap

c

m

0

Figure 36. Set Address Service

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35

NCN5130

b (busy mode):

‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34) and

disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req service

(see Receive Frame Service, p47).

aa (auto−acknowledge):‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service

(see Set Address Service, p35).

ap (auto−polling):

c (CRC−CCITT):

‘1’ if auto−polling feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

‘1’ if CRC−CCITT feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service

(see Configure Service, p38).

Remarks:

• Set Address Service can be issued any time but the new physical address and the autoacknowledge function will only

get active after the KNX bus becomes idle.

• Autoacknowledge can only be deactivated by a Reset Service (p34)

• x = don’t care

• Dummy byte can be anything. NCN5130 completely disregards this information.

Set Repetition Service

Specifies the maximum repetition count for transmitted frames when not acknowledged with IACK.

Separate counters can be set for NACK and BUSY frames. Initial value of both counters is 3.

If the acknowledge from remote Data Link Layer is BUSY during frame transmission, NCN5130 tries to repeat after at least

150 bit times KNX bus idle. The BUSY counter determines the maximum amount of times the frame is repeated. If the BUSY

acknowledge is still received after the last try, an L_Data.con with a negative conformation is sent back to the host controller.

For all other cases (NACK acknowledgment received, invalid/corrupted acknowledge received or time−out after 30 bit

times) NCN5130 will repeat after 50 bit times of KNX bus idle. The NACK counter determines the maximum retries.

L_Data.con with a negative confirmation is send back to the host controller when the maximum retries were reached.

In worst case, the same request is transmitted (NACK + BUSY + 1) times before NCN5130 stops retransmission.

Host Ctrl

NCN5130

KNX Bus

U_SetRepetition.req

1

0

x

1

0

1

0

n

x

Maximum Repetitions

b

x

b

x

b

0

n

x

n

x

Dummy

x

Dummy

x

Figure 37. Set Repetition Service

bbb: BUSY counter (a frame will be retransmitted bbb−times if acknowledge with BUSY).

nnn: NACK counter (a frame will be retransmitted nnn−times if acknowledge with NACK).

Remark: Bit 3 and 7 of the second byte need to be zero (‘0’)!

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36

NCN5130

System Status Service

Request the internal system state of the device.

Host Ctrl

NCN5130

KNX Bus

U_SystemStat.req

0

1

0

1

U_SystemStat.ind

1

0

1

0

1

2^ndbyte

Figure 38. System State Service

V20V:

VDD2:

VBUS:

VFILT:

XTAL:

TW:

‘1’ if V20V linear voltage regulator is within normal operating range

‘1’ if DC2 regulator is within normal operating range

‘1’ if KNX bus voltage is within normal operating range

‘1’ if voltage on tank capacitor is within normal operating range State Service

‘1’ if crystal oscillator frequency is within normal operating range

‘1’ if thermal warning condition is present (can also be verified with U_State.ind service (see State Service,

p34)

Mode:

Operation mode (see also Digital State Diagram, p29).

Bit

1

0

1

0

1

0

1

Mode

Power−Up

Sync

Stop

Normal

Note: SAVEB−pin is low if any of bits 3 to 7 is ‘0’ (zero) or bit 2 is ‘1’.

Stop Mode Service

Go to Stop State. A confirmation is sent to indicate that device has switched to the Stop State. See also Digital State Diagram,

p29

Host Ctrl

NCN5130

KNX Bus

U_StopMode.req

0

1

0

1

U_StopMode.ind

0

1

0

1

0

1

Figure 39. Stop Mode Service

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37

NCN5130

Exit Stop Mode Service

Request transition from Stop to Sync State. An acknowledge service is send later to confirm that device has switched from

Sync to Normal State. See also Digital State Diagram, p29.

Host Ctrl

NCN5130

KNX Bus

U_ExitStopMode .req

0

1

U_Reset.ind

0

Figure 40. Exit Stop Mode Service

Configure Service

Activate additional features (which are disabled after reset).

U_Configure.ind service is send back to the host controller at the exact moment when the new features get activated. This

is done during bus idle or outside the Normal State. It confirms the execution of the request service.

Host Ctrl

NCN5130

KNX Bus

U_Configure.req

0

1

p

c

m

1

U_Configure.ind

b

aa ap

c

m

0

Figure 41. Configure Service

p (auto polling):

c (CRC−CCITT):

when active, NCN5130 automatically fills in corresponding poll slot of polling telegrams.

Host controller is responsible to provide appropriate polling information with the

U_PollingState.req service (See Slave Polling Frame Service and Master Polling Frame

Service, p50 and 51).

when active, NCN5130 accompanies every received frame with a 2−byte CRC−CCITT

value. CRC−CCITT is also known as CRC−16−CCITT.

m (frame end with MARKER): End of received frames is normally reported with a silence of 2.6 ms on the Tx line to the host

controller. With this feature active, NCN5130 marks end of frame with U_FrameEnd.ind +

U_FrameState.ind services (See Send Frame Service and Receive Frame Service, p39 and 47).

b:

‘1’ if busy mode is active. Can be enabled with U_SetBusy.req (see Set Busy Service, p34)

and disabled with U_QuitBusy.req service (see Quit Busy Service, p34) or U_Ackn.req

service (see Receive Frame Service, p47).

aa:

‘1’ if auto−acknowledge feature is active. Can be enabled with U_SetAddress.req service

(see Set Address Service, p35).

ap (auto−polling):

c (CRC−CCITT):

‘1’ if auto−polling feature is active. This feature can be enabled with U_Configure.req service.

‘1’ if CRC−CCITT feature is active. See p53 for info on CRC−CCITT.

This feature can be enabled with U_Configure.req service.

m (frame end with MARKER): ‘1’ when feature is active. This feature can be enabled with U_Configure.req service.

Remark:

Activation of the additional features is done by setting the corresponding bit to ‘1’. Setting the bit to ‘0’ (zero) has no effect

(will not deactivate feature). Features can only be deactivated by a reset. Set all bits (m, c and p) to ‘0‘ (zero) to poll the current

configuration status.

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38

NCN5130

Internal Register Write Service

Write a byte to an internal device−specific register (see Internal Device−Specific Registers, p54). The address of the register

is specified in the request. The data to be written is transmitted after the request.

Host Ctrl

NCN5130

KNX Bus

U_IntRegWr.req

0

x

0

x

1

0

1

0

a

x

a

x

Data Byte

x

Figure 42. Internal Register Write Service

aa: address of the internal register

Remarks:

• x = don’t care (in line with Internal Device−Specific Registers, p54).

• Internal Register Write is not synchronized with other services. One should only use this service when all previous

services are ended. When using communication over SPI, it is recommended to go to stop mode when performing a

register write. When communicating over UART, this is not required.

Internal Register Read Service

Read a byte from an internal device−specific register (see Internal Device−Specific Registers, p54). The address of the

register is specified in the request. The next byte returns the data of the addressed register.

Host Ctrl

NCN5130

KNX Bus

U_IntRegRd.req

0

x

0

1

0

a

x

Data Byte

x

Figure 43. Internal Register Read Service

aa: address of the internal register

Remarks:

• x = don’t care (in line with Internal Device−Specific Registers, p54).

• It’s advised to only use this service in Stop, Power−Up Stop or Power−Up State. In the other state erroneous behavior

could occur.

• Internal Register Read is not synchronized with other services. One should only use this service when all previous

services are ended. When using communication over SPI or UART, it is recommended to go to stop mode when

performing a register write.

Send Frame Service

Send data over the KNX bus.

The U_L_DataStart.req is used to start transmission of a new frame. The byte following this request is the control byte of

the KNX telegram.

The different bytes following the control byte are assembled by using U_L_DataCont.req. The byte following

U_L_DataCont.req is the data byte of the KNX telegram. U_L_DataCont.req contains the index which specifies the position

of the data byte inside the KNX telegram. It‘s allowed to transmit bytes in random order and even overwrite bytes (= write

several times into the same index). It‘s up to the host controller to correctly populate all data bytes of the KNX telegram.

U_L_DataEnd.req is used to finalize the frame and start the KNX transfer. The byte following U_L_DataEnd.req is the

checksum of the KNX telegram. If the checksum received by the device corresponds to the calculated checksum, the device

starts the transmission on the KNX bus. If not, the device returns U_State.ind message to the host controller with Receive Error

flag set (see State Service p34 for U_State.ind).

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39

NCN5130

U_L_DataStart/DataCont/DataEnd only provides space for 6 index bits. Because an extended frame can consist out of

263 bytes, an index of 9 bits long is needed. U_DataOffset.req provides the 3 most significant bits of the data byte index. The

value is stored internally until a new offset is provided with another call.

Each transmitted data octet on the KNX bus will also be transmitted back to the host controller.

Each transmission is ended with a L_Data.con service where the MSB indicates if an acknowledgment was received or not.

When operating in SPI or UART 8−bit Mode, L_Data.con is preceded with U_FrameState.ind.

Depending on the activated features, a CRC−CCITT service and/or a MARKER could be included.

Next figures give different examples of send frames.

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

x

i

Control Byte

x

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet.req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

Immediate Ackn

x

w

2.6ms silence

U_FrameState.ind

res

re ce te

1

0

1

L_Data.con

x

0

1

0

1

Figure 44. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT

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40

NCN5130

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

x

i

Control Byte

x

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet.req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

Immediate Ackn

x

w

2.6ms silence

L_Data.con

x

0

1

0

1

Figure 45. Send Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT

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41

NCN5130

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

x

0

x

i

Control Byte

x

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet.req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

CRC−CCITT High Byte

x

CRC−CCITT Low Byte

x

Immediate Ackn

x

w

2.6 ms silence

L_Data.con

x

0

1

0

1

Figure 46. Send Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT

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42

NCN5130

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

x

i

Control Byte

x

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet.req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

CRC−CCITT High Byte

x

CRC−CCITT Low Byte

x

Immediate Ackn

x

w

2.6ms silence

U_FrameState.ind

res

re ce te

1

0

1

L_Data.con

x

0

1

0

1

Figure 47. Send Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT

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43

NCN5130

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

Control Byte

x

i

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet .req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

0

x

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

1

U_FrameEnd.ind

1

0

1

0

1

Immediate Ackn

x

U_FrameState .ind

res

re ce te

1

0

1

L_Data.con

0

x

0

1

0

1

Figure 48. Send Frame, All Modes, Frame End with MARKER, No CRC−CCITT

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44

NCN5130

Host Ctrl

NCN5130

KNX Bus

U_L_DataStart.req

1

x

1

x

0

x

i

Control Byte

x

U_L_DataCont.req

0

i

Data Octet 1

x

U_L_DataOffSet.req

0

1

x

0

1

i

U_L_DataCont.req

0

x

i

Data Octet N

x

U_L_DataEnd.req

0

x

1

x

0

x

l

Checksum

x

0

x

0

x

Control Byte

x

L_Data.ind

r

1

p1 p0

Data Octet 1

x

Data Octet 1

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

U_FrameEnd.ind

1

0

1

0

1

x

1

Immediate Ackn

x

U_FrameState.ind

res

re ce te

1

0

1

CRC−CCITT High Byte

x

1

CRC−CCITT Low Byte

x

L_Data.con

0

1

0

1

Figure 49. Send Frame, All Modes, Frame End with MARKER and with CRC−CCITT

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45

NCN5130

re (receive error):

‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or

incorrect bit timings)

ce (checksum or length error): ‘1’ if newly received frame contained wrong checksum or length which does not correspond

to the number of received bytes

te (timing error):

‘1’ if newly received frame contained bytes whose timings do not comply with the KNX

standard

res (reserved):

Remarks:

Reserved for future use (will be ‘0’).

− If the repeat flag is not set (see Set Repetition Service p36), the device will only perform one attempt to send the KNX

telegram.

− Sending of the KNX telegram over the KNX bus is only started after all data bytes are received and the telegram is

assembled.

− When starting transmission of a new frame with U_L_DataStart.req, the device automatically resets the internal offset of

the data index to zero.

− Data offsets of 5, 6 and 7 are forbidden (U_L_DataOffset.req)!

Remarks on Figures 44 to 49:

− x = don‘t care (in respect with KNX standard)

− See Tables 12 and 13 for more details on all the bits

− Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). When NCN5130 transmits

the data octet (0xCB) on the KNX bus, 2 bytes (2 times 0xCB) will be transmitted back to the host controller to make it

possible for the host controller to distinguish between a data octet (0xCB) and U_FrameEnd.ind. This remark is only

valid if frame end with MARKER is enabled.

− See p53 for info on CRC−CCITT.

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46

NCN5130

Receive Frame Service

Receive data over the KNX bus.

Upon reception from the control byte, the control byte is checked by the device. If correct, the control byte is transmitted

back to the host (L_Data_Standard.ind or L_Data_Extended.ind depending if standard or extended frame type is received).

After the control byte, all data bytes are transparently transmitted back to the host controller. Handling of this data is a task

for the Data Link Layer which should be implemented in the host controller.

The host controller can indicate if the device is addressed by setting the NACK, BUSY or ACK flag (U_Ackn.req).

When working in SPI or 8−bit UART Mode, each frame is ended with an U_FrameState.ind. Depending on the activated

features, a CRC−CCITT or MARKER could be added to the complete frame.

Below figures give different examples of receive frames.

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

Immediate Ackn

x

w

2.6 ms silence

U_FrameState .ind

re ce te

1

0

1

Figure 50. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, No CRC−CCITT

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47

NCN5130

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

Immediate Ackn

x

w

2.6 ms silence

Figure 51. Receive Frame, 9−bit UART Mode, Frame End with Silence, No CRC−CCITT

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

CRC−CCITT High Byte

x

Immediate Ackn

x

CRC−CCITT Low Byte

x

w

2.6ms silence

Figure 52. Receive Frame, 9−bit UART Mode, Frame End with Silence, with CRC−CCITT

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48

NCN5130

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

CRC−CCITT High Byte

x

Immediate Ackn

x

CRC−CCITT Low Byte

x

w

2.6ms silence

U_FrameState.ind

res

re ce te

1

0

1

Figure 53. Receive Frame, SPI or 8−bit UART Mode, Frame End with Silence, with CRC−CCITT

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

1

U_FrameEnd.ind

1

0

1

0

1

Immediate Ackn

x

U_FrameState.ind

res

re ce te

1

0

1

Figure 54. Receive Frame, All Modes, Frame End with MARKER, No CRC−CCITT

www.onsemi.com

49

NCN5130

Host Ctrl

NCN5130

KNX Bus

Control Byte

x

L_Data.ind

x

0

x

r

1

p1 p0

0

x

0

x

Data Octet 1

x

Data Octet 1

x

U_Ackn.req

0

x

0

x

0

1

0

n

b

x

a

x

Data Octet N

x

Data Octet N

x

Checksum

x

Checksum

x

U_FrameEnd.ind

1

0

1

0

1

x

1

Immediate Ackn

x

U_FrameState .ind

res

re ce te

1

0

1

CRC−CCITT High Byte

x

CRC−CCITT Low Byte

x

Figure 55. Receive Frame, All Modes, Frame End with MARKER, with CRC−CCITT

re (receive error):

‘1’ if newly received frame contained corrupted bytes (wrong parity, wrong stop bit or

incorrect bit timings)

ce (checksum or length error): ‘1’ if newly received frame contained wrong checksum or length which does not correspond

to the number of received bytes

te (timing error) :

‘1’ if newly received frame contained bytes whose timings do not comply with the KNX

standard

res (reserved) :

Reserved for future use (will be ‘0’).

Remarks on Figures 50 to 55:

− x = don‘t care (in respect with KNX standard)

− See Tables 12 and 13 for more details on all the bits

− Code of U_FrameEnd.ind (0xCB) can also be part of the KNX frame content (Data Octet). To make a distinguish

between a data octet and U_FrameEnd.ind, NCN5130 duplicates the data content (if 0xCB). This will result in 2 bytes

transmitted to the host controller (two times 0xCB) corresponding to 1 byte received on the KNX bus.

Above is only valid if frame end with MARKER is enabled.

− See p53 for info on CRC−CCITT.

Slave Polling Frame Service

Upon reception and consistency check of the polling control byte, the control byte is send back to the host controller

(L_Poll_Data.ind). The host controller will send the slot number to the device (U_PollingState.req), followed by the polling

address and the polling state. At the same time the source address, polling address, slot count and checksum is received over

the KNX bus. If the polling address received from the KNX bus is equal to the polling address received from the host controller,

NCN5130 will send the polling data in the slot as define by U_PollingState.req (only if the slotcount is higher as the define

slot).

U_PollingState.req can be sent at any time (not only during a transmission of a polling telegram). The information is stored

internally in NCN5130 and can be reused for further polling telegrams if auto−polling function gets activated.

www.onsemi.com

50

NCN5130

Host Ctrl

NCN5130

KNX Bus

Control Byte

1

0

x

L_Poll_Data.ind

1

x

1

0

Source Address

x

U_PollingState.req

1

x

1

0

s

x

s

x

Source Address

x

PollAddrHigh

x

Poll Address

x

PollAddrLow

x

Poll Address

x

PollState

x

Slot Count

x

Checksum

x

Slot 0

x

Slot N

x

Figure 56. Slave Polling Frame Service

Remarks:

x = don’t care (in respect with KNX standard)

ssss = slot number

Master Polling Frame Service

When NCN5130 receives the polling frame from the host controller, the polling frame will be transmitted over the KNX bus.

www.onsemi.com

51

NCN5130

Host Ctrl

NCN5130

KNX Bus

Control Byte

1

x

1

x

1

x

1

0

Source Address

x

Source Address

x

Poll Address

x

Poll Address

x

Slot Count

x

Checksum

x

Control Byte

1

x

1

0

x

L_Poll_Data.ind

1

0

x

s

x

Source Address

x

Source Address

x

U_PollingState.req

1

0

s

x

Source Address

x

Source Address

x

Poll Address

x

PollAddrHigh

x

Poll Address

x

Poll Address

x

PollAddrLow

x

Poll Address

x

Slot Count

x

PollState

x

Slot Count

x

Checksum

x

Checksum

x

Slot 0

x

Slot 0

x

Slot N

x

Slot N

x

Figure 57. Master Polling Frame Service

Remarks:

x = don‘t care (in respect with KNX standard)

ssss = slot number

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52

NCN5130

CRC−CCITT

CRC order - 16 bit

CRC polynom (hex) - 1021

Initial value (hex) − FFFF

Final XOR value (hex) − 0

No reverse on output CRC

Test string „123456789“ is 29B1h

CRC−CCITT value over a buffer of bytes can be calculated with following code fragment in C, where

pBuf is pointer to the start of frame buffer

uLength is the frame length in bytes

unsigned short calc_CRC_CCITT(unsigned char* pBuf, unsigned short uLength)

{

unsigned short u_crc_ccitt;

for (u_crc_ccitt = 0xFFFF; uLength−−; p++)

{

u_crc_ccitt = get_CRC_CCITT(u_crc_ccitt, *p);

}

return u_crc_ccitt;

}

unsigned short get_CRC_CCITT(unsigned short u_crc_val, unsigned char btVal)

{

u_crc_val = ((unsigned char)(u_crc_val >> 8)) | (u_crc_val << 8);

u_crc_val ^= btVal;

u_crc_val ^= ((unsigned char)(u_crc_val & 0xFF)) >> 4;

u_crc_val ^= u_crc_val << 12;

u_crc_val ^= (u_crc_val & 0xFF) << 5;

return u_crc_val;

}

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53

NCN5130

Internal Device−Specific Registers

In total 4 device-specific register are available:

• Watchdog Register (0x00)

• Analog Control Register 0 (0x01)

• Analog Control Register 1 (0x02)

• Analog Status Register 0 (0x03)

• Revision ID Register (0x05)

Watchdog Register

The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time.

Table 14. WATCHDOG REGISTER

ExtWatchdogCtrl (ExtWR)

Address

Bit 7

R/W

0

Bit 6

Bit 5

Bit 4

Bit 3

R/W

1

Bit 2

R/W

1

Bit 1

R/W

1

Bit 0

R/W

1

Access

Reset

Data

R/W

0

-

0

-

0

-

0x00

WDEN

WDT

Table 15. WATCHDOG REGISTER PARAMETERS

Parameter

Value

Disable

Description

Info

0

WDEN

Enables/disables the watchdog

1

Enable

33 ms

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

66 ms

98 ms

131 ms

164 ms

197 ms

229 ms

262 ms

295 ms

328 ms

360 ms

393 ms

426 ms

459 ms

492 ms

524 ms

p22

Defines the watchdog time. The watchdog needs to be re-enabled (WDEN)

within this time or a watchdog event will be triggered.

WDT

Remark: Bit 4 … 6 are reserved.

Analog Control Register 0

The Analog Control Register 0 is located at address 0x01 and can be used to disable the V20V and the DC2 regulator, to

disable the XCLK-pin, to enable the transmit trigger signal and to set the 20 V LDO current limit.

Table 16. ANALOG CONTROL REGISTER 0

Analog Control Register 0 (AnaCtrl0)

Address

Bit 7

R/W

0

Bit 6

R/W

Bit 5

R/W

Bit 4

R/W

Bit 3

R/W

Bit 2

R/W

1

Bit 1

R/W

Bit 0

R/W

0

Access

Reset

Data

1

0

0x01

−

V20VEN

DC2EN

XCLKEN

TRIGEN

V20VCLIMIT

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54

NCN5130

Table 17. ANALOG CONTROL REGISTER 0 PARAMETERS

Parameter

Value

Description

Info

0

1

0

1

0

1

0

1

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

V20VEN

Enables/disables the V20V regulator

Enables/disables the DC2 converter

Enables/disables the XCLK output signal

p 19

DC2EN

p 19

XCLKEN

TRIG/ARXD pin outputs the Tx activity monitor signal when enabled.

When disabled the TRIG/ARXD pin is tri−state.

TRIGEN

p 19

V20VCLIMIT

000 − 111

Adjustment of the V20V current limit as configured by R by DI

per bit

6

20V, STEP

Remark: Bit 7 is reserved.

Analog Control Register 1

The Analog Control Register 1 is located at address 0x02 and can be used to configure the voltage monitors.

Table 18. ANALOG CONTROL REGISTER 1

Analog Control Register 1 (AnaCtrl1)

Address

Bit 7

R/W

0

Bit 6

R/W

Bit 5

R/W

Bit 4

R/W

Bit 3

R/W

0

Bit 2

R/W

Bit 1

R/W

0

Bit 0

Access

Reset

Data

R/W

1

0

-

0x02

V20V_OK_M

VDD2_OK_M

VFILT_OK_M

ANAOUTCTRL

−

Table 19. ANALOG CONTROL REGISTER 1 PARAMETERS

Parameter

Value

Enable

Description

Info

0

1

V20V_OK_M

Enable to include the voltage monitor output in the SAVEB calculation.

p 19

p 18

Disable

Enable

Disable

Enable

Disable

Enable

0

VDD2_OK_M

VFILT_OK_M

1

0

1

000

001

010

011

100

101

110

111

Analog output is disabled

Analog output monitors VBUS1

Analog output monitors VFILT

Analog output monitors V20V

Analog output monitors VDD2

Analog output monitors VDDA

Analog output monitors Bus current

Analog output monitors Temperature

ANAOUTCTRL

p 23

Remark: Bit 0 and bit 7 are reserved.

www.onsemi.com

55

NCN5130

Analog Status Register

The Analog Status Register is located at address 0x03 and can be used to verify the voltage monitors, Xtal and thermal status.

Table 20. ANALOG STATUS REGISTER

Analog Status Register (AnaStat)

Address

Bit 7

Bit 6

R

Bit 5

R

Bit 4

R

Bit 3

R

Bit 2

R

Bit 1

R

Bit 0

R

Access

Reset

Data

R

0

0x03

−

V20V

VDD2

VBUS

VFILT

XTAL

TW

TSD

Table 21. ANALOG STATUS REGISTER PARAMETERS

Parameter

Value

nOK

OK

Description

Info

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V20V

‘1’ if voltage on V20V-pin is above the V20V undervoltage level

‘1’ if voltage on VDD2-pin is above the VDD2 undervoltage level

‘1’ if bus voltage is above the VBUS undervoltage level

‘1’ if voltage on VFILT-pin is above the VFILT undervoltage level

‘1’ if XTAL is up and running

p 19

P 18

p 18

p 19

nOK

OK

VDD2

VBUS

VFILT

XTAL

TW

nOK

OK

nOK

OK

nOK

OK

No TW

TW

‘1’ if Thermal Warning detected

p 22

No TSD

TSD

Contains information about the previous Thermal Shutdown situation

Remark: Bit 7 is reserved.

Revision ID register

The Revision ID register is located at address 0x05 and can be read out to check the revision ID of the silicon and by the

firmwire of the host controller to determine the part number of the transceiver

Table 22. REVISION ID REGISTER

Revision ID Register (RevID)

Address

Bit 7

R

Bit 6

Bit 5

R

Bit 4

R

Bit 3

R

Bit 2

Bit 1

R

Bit 0

R

Access

Reset

Data

R

X

R

X

0

1

0

0x05

Revision

Part Number

Table 23. REVISION ID REGISTER PARAMETERS

Parameter

Revision

Value

Description

Info

Silicon revision ID

Part Number

01100

NCN5130

Transceiver Part Number

www.onsemi.com

56

NCN5130

PACKAGE THERMAL CHARACTERISTICS

The NCN5130 is available in a QFN40 package. For cooling optimizations, the QFN40 has an exposed thermal pad which

has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer.

Figure 58 gives an example of good heat transfer. The exposed thermal pad is soldered directly on the top ground layer (left

picture of Figure 58). It‘s advised to make the top ground layer as large as possible (see arrows Figure 58). To improve the heat

transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of

Figure 58). It‘s advised to make this bottom ground layer as large as possible and with as less as possible interruptions.

For precise thermal cooling calculations the major thermal resistances of the device are given (Table 4). The thermal media

to which the power of the devices has to be given are:

− Static environmental air (via the case)

− PCB board copper area (via the exposed pad)

The major thermal resistances of the device are the Rth from the junction to the ambient (Rth ) and the overall Rth from

ja

the junction to exposed pad (Rth ). In Table 4 one can find the values for the Rth and Rth , simulated according to JESD−51.

jp

ja

jp

The Rth for 2S2P is simulated conform JEDEC JESD−51 as follows:

ja

− A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used

− Board thickness is 1.46 mm (FR4 PCB material)

2

− The 2 signal layers: 70 mm thick copper with an area of 5500 mm copper and 20% conductivity

2

− The 2 power internal planes: 36 mm thick copper with an area of 5500 mm copper and 90% conductivity

The Rth for 1S0P is simulated conform to JEDEC JESD−51 as follows:

ja

− A 1−layer printed circuit board with only 1 layer

− Board thickness is 1.46 mm (FR4 PCB material)

− The layer has a thickness of 70 mm copper with an area of 5500 mm copper and 20% conductivity

2

Figure 58. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays

the bottom ground layer)

ORDERING INFORMATION

†

Device Number

NCN5130MNG

Temperature Range

Package

Shipping

−40°C to 105°C

QFN−40

(Pb−Free)

50 Units / Tube

100 Tubes / Box

NCN5130MNTWG

−40°C to 105°C

QFN−40

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

www.onsemi.com

57

NCN5130

PACKAGE DIMENSIONS

QFN40 6x6, 0.5P

CASE 485AU

ISSUE O

NOTES:

D

A B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

L

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

LOCATION

L1

DETAIL A

OPTIONAL

E

CONSTRUCTIONS

MILLIMETERS

DIM MIN

MAX

1.00

0.05

A

A1

A3

b

0.80

0.00

0.20 REF

0.15

C

EXPOSED Cu

MOLD CMPD

0.18

0.30

TOP VIEW

D

D2

E

E2

e

K

6.00 BSC

0.15

C

3.10

3.30

6.00 BSC

DETAIL B

(A3)

DETAIL B

3.30

0.10

C

OPTIONAL

0.50 BSC

0.20 MIN

0.30 0.50

−−− 0.15

CONSTRUCTIONS

A

L

L1

0.08

A1

NOTE 4

SEATING

PLANE

C

SIDE VIEW

D2

SOLDERING FOOTPRINT*

0.10

C A B

DETAIL A

6.30

3.32

K

40X

0.63

11

10

20

21

30

1

E2

L

0.10

C A B

1

3.32

6.30

40

31

40X b

e

0.10

C

A B

BOTTOM VIEW

0.05

PACKAGE

OUTLINE

40X

0.28

0.50 PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

KNX and the KNX Logos are trademarks of KNX Association.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

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Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

◊

NCN5130/D

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58


型号：	NCN5130MNTWG
厂家：	ONSEMI
描述：	Transceiver for KNX Twisted Pair Networks
文件：	总58页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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