NCP51190MNTAG [ONSEMI]
1.5A DDR Memory Termination Regulator;
| 型号： | NCP51190MNTAG |
| 厂家： | 
ONSEMI |
| 描述： | 1.5A DDR Memory Termination Regulator 双倍数据速率 |
| 文件： | 总9页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP51190, NCV51190
1.5A DDR Memory
Termination Regulator
The NCP/NCV51190 is a simple, cost−effective, high−speed linear
regulator designed to generate the V termination voltage rail for
TT
DDR−I, DDR−II and DDR−III memory. The regulator is capable of
actively sourcing or sinking up to 1.5 A for DDR−I, or up to 0.5 A
for DDR−II /−III while regulating the output voltage to within
30 mV.
http://onsemi.com
MARKING
DIAGRAM
The output termination voltage is tightly regulated to track V
=
TT
(V
/ 2) over the entire current range.
DDQ
1
DFN8
The NCP/NCV51190 incorporates a high−speed differential
amplifier to provide ultra−fast response to line and load transients.
Other features include extremely low initial offset voltage, excellent
load regulation, source/sink soft−start and on−chip thermal shut−down
protection.
XXMG
MN SUFFIX
CASE 506AA
G
1
XX = Specific Device Code
M
= Date Code
The NCP/NCV51190 features the power−saving Suspend To Ram
(STR) function which will tri−state the regulator output and lower the
quiescent current drawn when the /SS pin is pulled low.
The NCP/NCV51190 is available in a DFN8 package.
G
= Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTION
Features
• Generate DDR Memory Termination Voltage (V
)
TT
• For DDR−I, DDR−II, DDR−III Source / Sink Currents
• Supports DDR−I to 1.5 A, DDR−II, DDR−III to 0.5 A (peak)
• Integrated Power MOSFETs with Thermal Protection
• Stable with 10 mF Ceramic V Capacitor
TT
• High Accuracy Output Voltage at Full−Load
• Minimal External Component Count
• Shutdown for Standby or Suspend to RAM (STR) mode
• Built−in Soft Start
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These are Pb−Free Devices
Appications
• Desktop PC’s, Notebooks, and Workstations
• Graphics Card DDR Memory Termination
• Set Top Boxes, Digital TV’s, Printers
• Embedded Systems
• Active Bus Termination
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2014 − Rev. 3
NCP51190/D
NCP51190, NCV51190
1.5 A, DDR−I /−II /−III TERMINATION REGULATOR
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION – NCP51190
Pin Number
Pin Name
Pin Function
1
PV
The PV pin provides the rail voltage from where the V pin draws load current. There is a limitation
CC
CC
TT
between V and PV . The PV voltage must be less or equal to the V voltage to ensure the
CC
CC
CC
CC
correct output voltage regulation. The V source current capability is dependent on PV voltage. The
TT
CC
higher the voltage on PV , the higher the source current.
CC
2
3
4
V
Regulator output voltage capable of sinking and sourcing current while regulating the output rail.
Common Ground.
TT
GND
/SS
Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V output to
TT
high impedance state. Logic HI = Enable, Logic LO = Shutdown.
5
6
V
V
is the V sense input.
TTS
TTS
TT
V
REF
V
V
is an output pin that provides the buffered output of the internal reference voltage equal to half of
. Two resistors dividing down the V
REF
DDQ
voltage on the pin to create the regulated output voltage.
DDQ
7
V
DDQ
The V
pin is an input pin for creating the internal reference voltage to regulate V . The V
volt-
DDQ
TT
DDQ
age is connected to an internal resistor divider. The central tap of resistor divider (V
/2) is con-
DDQ
nected to the internal voltage buffer, which output is connected to V
of the error amplifier as the reference voltage.
pin and the non−inverting input
REF
8
V
CC
Power for the analog control circuitry.
THERMAL
PAD
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
http://onsemi.com
2
NCP51190, NCV51190
ABSOLUTE MAXIMUM RATINGS
Rating
, /SS to GND (Note 1)
Symbol
Value
−0.3 to +6
−65 to +150
−40 to +125
TBD
Unit
V
V
CC
, PV ,V
CC DDQ
Storage Temperature
T
stg
°C
Operating Junction Temperature Range
T
J
°C
Thermal Characteristics, SO8−EP Thermal Resistance, Junction−to−Air
Power Rating at 25°C ambient
R
°C/W
q
JA
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
2000
150
V
V
HBM
ESD
MM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. No pin to exceed V . Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
CC
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
V
Bias Supply Voltage
Input Voltage
V
CC
2.2 to 5.5
1.5 to 2.5
1.35 to 2.7
PV
V
CC
Reference Input Voltage
V
DDQ
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
−40°C ≤ T ≤ 125°C; V = PV = V
= 2.5 V; unless otherwise noted. Typical values are at T = +25°C
J
J
CC
CC
DDQ
Parameter
Condition
Symbol
Min
Typ
Max
Unit
Reference Voltage (DDR I)
= 0 mA (unloaded)
PV = V
= 2.3 V
= 2.5 V
= 2.7 V
V
REF
(DDR−I)
1.125
1.225
1.325
1.151
1.251
1.351
1.175
1.275
1.375
CC
DDQ
DDQ
DDQ
I
V
REF
Reference Voltage (DDR II)
= 0 mA (unloaded)
PV = V
= 1.7 V
= 1.8 V
= 1.9 V
V
REF
0.830
0.880
0.925
0.851
0.901
0.951
0.880
0.930
0.975
CC
I
(DDR−II)
V
REF
Reference Voltage (DDR III)
= 0 mA (unloaded)
PV = V
= 1.35 V
= 1.5 V
= 1.6 V
V
REF
0.660
0.735
0.785
0.676
0.751
0.801
0.695
0.770
0.820
CC
I
(DDR−III)
V
REF
V
V
− Output Impedance
I
I
= −30 mA to +30 mA
Z
REF
2.5
kW
REF
REF
Output Voltage
= 0 A
V
TT
−
−
−
TT
OUT
(DDR−I)
PV = V
= 2.3 V
= 2.5 V
= 2.7 V
(DDR−I)
1.112
1.202
1.312
1.150
1.250
1.350
1.182
1.282
1.382
CC
DDQ
DDQ
DDQ
PV = V
CC
PV = V
CC
I
I
= +1.5 A
V
−
−
−
OUT
TT
PV = V
= 2.3V
= 2.5V
= 2.7V
(DDR−I)
1.115
1.215
1.315
1.150
1.250
1.350
1.185
1.285
1.385
CC
DDQ
DDQ
DDQ
V
PV = V
CC
PV = V
CC
= −1.5 A
V
TT
−
−
−
OUT
PV = V
= 2.3V
= 2.5V
= 2.7V
(DDR−I)
1.117
1.217
1.317
1.150
1.250
1.350
1.182
1.282
1.382
CC
DDQ
DDQ
DDQ
PV = V
CC
PV = V
CC
http://onsemi.com
3
NCP51190, NCV51190
ELECTRICAL CHARACTERISTICS
−40°C ≤ T ≤ 125°C; V = PV = V
= 2.5 V; unless otherwise noted. Typical values are at T = +25°C
J
CC
CC
DDQ
J
Parameter
Condition
Symbol
Min
Typ
Max
Unit
V
Output Voltage
I
I
I
I
= 0 A
V
TT
(DDR−II)
−
−
−
TT
OUT
(DDR−II)
PV = V
= 1.7 V
= 1.8 V
= 1.9 V
0.816
0.866
0.916
0.850
0.900
0.950
0.881
0.931
0.981
CC
DDQ
DDQ
DDQ
PV = V
CC
PV = V
CC
= +0.5 A
V
TT
−
−
−
OUT
PV = V
= 1.7 V
= 1.8 V
= 1.9 V
(DDR−II)
0.815
0.863
0.914
0.851
0.900
0.950
0.885
0.933
0.984
CC
DDQ
DDQ
DDQ
V
PV = V
CC
PV = V
CC
= −0.5 A
V
TT
−
−
−
OUT
PV = V
= 1.7 V
= 1.8 V
= 1.9 V
(DDR−II)
0.814
0.862
0.913
0.850
0.900
0.950
0.884
0.932
0.983
CC
DDQ
DDQ
DDQ
PV = V
CC
PV = V
CC
V
TT
Output Voltage
= 0 A
V
TT
−
−
−
OUT
(DDR−III)
P
= V
= 1.35 V
= 1.5 V
= 1.6 V
(DDR−III)
0.650
0.725
0.775
0.675
0.750
0.800
0.700
0.775
0.825
VCC
DDQ
DDQ
DDQ
PV = V
PV = V
CC
CC
I
I
= +0.2 A,
V
−
0.649
−
−
−
OUT
TT
(DDR−III)
0.675
−
0.675
0.700
−
0.700
PV = V
= 1.35 V
= 1.35 V
DDQ
CC
DDQ
= −0.2 A,
OUT
PV = V
0.640
CC
V
I
I
= +0.4 A,
V
−
−
−
OUT
TT
PV = V
= 1.5 V
= 1.5 V
DDQ
(DDR−III)
0.722
−
0.725
0.751
−
0.750
0.776
−
0.774
CC
DDQ
= −0.4 A,
OUT
PV = V
CC
I
I
= +0.5 A,
V
−
−
−
OUT
TT
PV = V
= 1.6 V
= 1.6 V
(DDR−III)
0.773
−
0.775
0.801
−
0.800
0.827
−
0.824
CC
DDQ
= −0.5 A,
OUT
PV = V
CC
DDQ
DDQ
DDQ
DDQ
V
TT
Output Offset Voltage
I
I
I
I
=
1.5 A,
V
OS
(DDR−I)
−30
−30
−30
0
0
0
+30
+30
+30
500
OUT
PV = V
= 2.5 V
= 1.8V
= 1.5V
CC
=
0.5A,
V
OS
(DDR−II)
OUT
mV
PV = V
CC
=
0.5A,
V
OS
(DDR−III)
OUT
PV = V
CC
Quiescent Current
Input Impedance
= 0 A
I
Q
380
100
2
mA
kW
mA
mA
OUT
V
DDQ
Z
I
VDDQ
L_SS
Q_SS
/SS Leakage Current
/SS = 0 V
/SS = 0 V
5
Quiescent Current in Suspend Shutdown
Suspend Shutdown Threshold
I
115
150
V
1.9
IH
V
V
0.8
10
IL
L_VTT
V
V
leakage Current in Suspend Shutdown
/SS = 0 V, V = 1.25 V
I
1
mA
nA
°C
°C
TT
TT
Current
I
13
TTS
TTS
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
T
165
10
SD
SH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
http://onsemi.com
4
NCP51190, NCV51190
TYPICAL PERFORMANCE CHARACTERISTICS
140
120
700
600
100
80
500
400
300
200
60
40
100
0
20
0
2
2
0
3
4
5
6
6
6
2
0
2
3
4
5
6
6
6
V
(V)
V
(V)
CC
CC
Figure 2. IqSD vs. VCC
Figure 3. Iq vs. VCC
3.5
3.0
2.5
3.0
2.5
2.0
1.5
1.0
2.0
1.5
1.0
0.5
0.5
0
3
4
5
1
2
3
4
5
V
(V)
V
(V)
DDQ
CC
Figure 4. VIH and VIL
Figure 5. VREF vs. VDDQ
3.0
2.5
2.0
1.5
1.0
160
140
120
100
80
60
−40°C
25°C
85°C
40
0.5
0
20
0
125°C
1
2
3
4
5
3
4
5
V
DDQ
(V)
V
CC
(V)
Figure 6. VTT vs. VDDQ
Figure 7. IqSD vs. VCC over Temperature
http://onsemi.com
5
NCP51190, NCV51190
TYPICAL PERFORMANCE CHARACTERISTICS
800
700
600
500
400
300
200
−40°C
25°C
85°C
125°C
100
0
2
3
4
5
6
V
CC
(V)
Figure 8. Iq vs. VCC over Temperature
http://onsemi.com
6
NCP51190, NCV51190
General
significant IR drop resulting in a sagging termination
voltage at one end of the bus than the other. The V pin can
The NCP/NCV51190 is a bus termination, linear
TTS
regulator designed to meet the JEDEC requirements for
DDR−I, DDR−II and DDR−III memory termination. The
NCP/NCV51190 is capable of sourcing and sinking current
be used to improve performance by connecting it to the
middle of the bus. This will provide better power
distribution across the entire termination bus. If remote load
while accurately tracking and regulating the V output
regulation is not used, then the V
pin must still be
TT
TTS
voltage equal to (V
/ 2). The output stage has been
connected to V . Care should be taken when a long V
DDQ
TT
TTS
designed to maintain excellent load regulation and
preventing shoot−through. The NCP/NCV51190 uses two
distinct power rails to separate the analog circuitry from the
power output stage and decrease internal power dissipation.
trace is implemented in close proximity to the memory.
Noise pickup in the V trace can cause problems with
TTS
precise regulation of V . A small 0.1 mF ceramic capacitor
TT
placed next to the V
pin can help filter out any high
TTS
frequency noise and thereby keeping the V power rail in
spec.
TT
Supply Voltage Inputs
For added flexibility, separate input pins (V and PV
are provided for each required supply input. V is used to
)
CC
CC
Regulator Shutdown Function
CC
The NCP/NCV51190 contains an active low enable pin
(/SS) that can be used for suspend to RAM functionality. In
supply all the internal control circuitry and PV is used
exclusively to provide the rail voltage for the output stage
CC
this condition the V output will tri−state, with the V
used to create V . These pins have the capability to work
TT
REF
TT
output remaining active in order to provide a constant
reference signal for the memory and chipset. During
off separate supplies with the condition that V is always
CC
greater than or equal to PV , and should always be used
CC
shutdown, V should not be exposed to voltages that
with either a 1.8 V or 2.5 V rail. If the junction temperature
exceeds the thermal shutdown threshold, the part will enter
a shutdown state identical to the manual shutdown where
TT
exceed PV
.
CC
With the enable pin asserted low the quiescent current of
the NCP/NCV51190 will drop, however the V input pin
V
TT
is tri−stated and V
remains active. Lower voltage
DDQ
REF
will always draw a constant current due to the integrated
100 kW impedance used for generating the internal
reference. Therefore, to calculate the total power loss in
shutdown, both currents need to be considered. The enable
pin also has an internal pull−up current. Therefore, to turn
rails, such as 1.5 V can be used but will reduce the maximum
available output current.
Generation of Internal Voltage Reference
V
DDQ
is the input used to create the internal reference
voltage for regulating V . The reference voltage is
TT
the part on, the enable pin can either be connected to V or
CC
generated from a resistor divider of two internal 50 kW
left open.
resistors. This guarantees that V will precisely track
TT
Termination Voltage Output Regulation
(V
/ 2). The optimal implementation of the V
input
DDQ
DDQ
V
TT
is the regulated output that is used to terminate the
pin is as a remote sense. This can be achieved by connecting
directly to the 1.8 V rail at the DIMM memory
bus resistors. It is capable of sourcing and sinking current
while regulating the output precisely to V / 2. The
V
DDQ
DDQ
module instead of connecting it to PV . This ensures that
CC
NCP/NCV51190 is designed to handle continuous currents
of up to 1.5 A with excellent load regulation. If a transient
is expected to last above the maximum continuous current
rating for a significant amount of time, then the bulk output
capacitor should be sized large enough to prevent an
excessive voltage drop.
the reference voltage precisely tracks the DDR memory
power rail without introducing a large voltage drop due to
power traces. For DDR−II applications the V
input will
DDQ
be 1.8 V, which will create a (V
/ 2) = 0.9 V termination
DDQ
voltage at the V output.
TT
V
REF
provides a buffered output of the internal reference
voltage (V
/ 2). For improved performance, an output
Thermal Shutdown with Hysteresis
DDQ
bypass capacitor can be placed, close to the pin, to help
reduce any potential stray noise. A ceramic capacitor in the
If the NCP/NCV51190 is to operate in elevated
temperatures for long durations, care should be taken to
ensure that the maximum operating junction temperature is
not exceeded. To guarantee safe operation, the
NCP/NCV51190 provides on−chip thermal shutdown
protection. When the chip junction temperature exceeds
165°C (typical) the part will shutdown. When the junction
temperature falls back to 155°C (typical) the device resumes
normal operation. If the junction temperature exceeds the
range of 0.01mF to 0.1 mF is recommended. The V
output
REF
remains active during the shutdown state and thermal
shutdown events for the suspend to RAM functionality.
Remote Voltage Feedback Sensing
The purpose of the V
sense pin is to provide improved
TTS
remote load regulation. In most motherboard applications,
the termination resistors will connect to V in a long plane.
TT
thermal shutdown threshold, V will tri−state until the part
TT
If the output voltage was regulated only at the output of the
NCP/NCV51190, then any long traces will generate a
returns below the temperature hysteresis trip−point.
http://onsemi.com
7
NCP51190, NCV51190
Table 1. ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCP51190MNTAG
A5
DFN8
(Pb-Free)
3000 / Tape & Reel
NCV51190MNTAG*
CC
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
8
NCP51190, NCV51190
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
MILLIMETERS
2X
0.10
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
2X
0.10
C
TOP VIEW
0.20
0.30
D
2.00 BSC
D2
E
E2
e
K
L
L1
1.10
2.00 BSC
0.70
0.50 BSC
0.30 REF
0.25
−−−
1.30
A
C
DETAIL B
0.10
0.08
C
C
DETAIL B
0.90
OPTIONAL
CONSTRUCTION
0.35
0.10
(A3)
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
8X
D2
1.30
0.50
8X
L
PACKAGE
OUTLINE
4
1
E2
0.90
2.30
5
8
K
8X b
1
e/2
0.10
0.05
C
C
A
B
8X
0.30
e
0.50
PITCH
NOTE 3
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP51190/D
相关型号：
©2020 ICPDF网 联系我们和版权申明