NCP51530BDR2G [ONSEMI]
High Frequency High and Low Side Driver;
| 型号： | NCP51530BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | High Frequency High and Low Side Driver |
| 文件： | 总25页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP51530
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High Frequency, 700 V- 2 A
High and Low Side Driver
NCP51530 is a 700 V high side and low side driver with 2 A current
drive capability for AC−DC power supplies and inverters. NCP51530
offers best in class propagation delay, low quiescent current and low
switching current at high frequencies of operation. This device is
tailored for highly efficient power supplies operating at high
frequencies. NCP51530 is offered in two versions, NCP51530A/B.
NCP51530A has a typical 60 ns propagation delay, while NCP51530B
has a typical propagation delay of 25 ns. NCP51530 comes in SOIC8
and DFN10 packages.
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MARKING
DIAGRAMS
8
1
1
SOIC−8
NCP51530x
ALYW
G
D SUFFIX
CASE 751−07
Features
• High voltage range: Up to 700 V
• NCP51530A: Typical 60 ns Propagation Delay
• NCP51530B: Typical 25 ns Propagation Delay
• Low Quiescent and Operating Currents
• 15 ns Rise and Fall Time
1
51530x
ALYWG
G
DFN10
MN SUFFIX
CASE 506DJ
• 2.2 A/1.7 A Source/sink Currents
NCP5106 = Specific Device Code
• Under−voltage Lockout for Both Channels
• 3.3 V and 5 V Input Logic Compatible
• High dv/dt Immunity up to 50 V/ns
• Pin to Pin Compatible with Industry Standard Half−bridge ICs.
• Matched Propagation Delay (7 ns Max)
• High Negative Transient Immunity on Bridge Pin
• DFN10 Package Offers Both Improved Creepage and Exposed Pad
x
A
WL
YY
WW
G
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
Applications
VB
HO
HB
HIN
LIN
GND
1
• High−density SMPS for Servers, Telecom and Industrial
• Half/Full−bridge & LLC Converters
• Active Clamp Flyback/Forward Converters
• Solar Inverters & Motor Controls
• Electric Power Steering
LO
VCC
8 Pin Package
(Top View)
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
1
VCC
HIN
LIN
GND
GND
VB
HO
HB
NC
LO
10 Pin DFN Package
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
March, 2018 − Rev. P0
NCP51530/D
NCP51530
HIN
LIN
VB
HO
VB
VCC
HIN
HO
LIN
GND
GND
HB
NC
LO
GND
LO
HB
VCC
SOIC8
DFN10
(Top View)
(Top View)
Table 1. PIN DESCRIPTION SOIC 8 PACKAGE
Pin Out
Name
HIN
LIN
Function
1
2
3
4
5
6
7
8
High side input
Low side input
Ground reference
Low side output
GND
LO
VCC
HB
Low side and logic supply
High side supply return
High side output
HO
VB
High side voltage supply
Table 2. PIN DESCRIPTION DFN10 PACKAGE
Pin Out
Name
VCC
HIN
LIN
Function
1
2
Low side and logic supply
High side input
3
Low side input
4
GND
GND
LO
Ground reference
Ground reference
Low side output
5
6
7
NC
No Connect
8
HB
High side supply return
High side output
9
HO
10
VB
High side voltage supply
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2
NCP51530
VHV
ADRV
LDRV
HIN
LIN
VB
HO
PWM CONTROLLER
NCP51530
GND
LO
HB
VCC
COMP
Figure 1. Simplified Applications Schematic for a Half−Bridge Converter (SOIC8)
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NCP51530
VHV
VCC
VB
HIN
LIN
HO
HB
NC
GND
GND
LO
VCC
VB
HIN
LIN
HO
HB
NC
GND
GND
LO
LIN 1
HIN 1
LIN 2
Micro Controller
Digital Isolator
HIN 2
Figure 2. Simplified Applications Schematic for a Full Bridge Converter (DFN 10)
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NCP51530
VCC
VB
UV
Detect
Q
Q
S
R
Pulse
Trigg er
Level
Shifter
HIN
HO
HB
r
UV
DETECT
VCC
LO
DELAY
LIN
r
GND
Figure 3. Internal Block Diagram for NCP51530
Table 3. ABSOLUTE MAXIMUM RATINGS All voltages are referenced to GND pin.
Rating Symbol
Value
Unit
V
Input voltage range
V
CC
−0.3 to 19
−0.3 to 720
−0.3 to 20
High side boot pin voltage
High side floating voltage
High side drive output voltage
Low side drive output voltage
Allowable hb slew rate
Drive input voltage
V
V
B
V −V
V
B
HB
HO
V
V
HB
– 0.3 to V + 0.3
V
B
V
LO
−0.3 to V + 0.3
V
CC
dV /dt
HB
50
V/ns
V
V
,
−5 to V + 0.3
LIN
HIN
CC
V
Junction temperature
T
150°
C
C
V
J(MAX)
Storage temperature range
ESD Capability (Note 1)
T
−55° to 150°
STG
Human Body Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
4000
1000
Lead Temperature Soldering
Reflow (SMD Styles ONLY), Pb−Free Versions (Note 2)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods. ESD Human Body Model tested per
AEC−Q100−002(EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11(EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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NCP51530
Table 4. THERMAL CHARACTERSTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC8 (Note 3)
Thermal Resistance, Junction to Air (Note 4)
R
130
45
145
72
°C/W
q
JA
Thermal Characteristics, DFN10
Thermal Resistance, Junction to Air
R
°C/W
q
JA
3. Refer to ELECTRICAL CHARACTERSTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
4. Values based on copper area of 645 mm (or 1 in ) of 1 oz thickness and FR4 PCB substrate.
Table 5. RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
10
Max
17
Unit
V
Input Voltage Range
V
CC
High Side Floating Voltage
High Side Bridge pin Voltage
High Side Output Voltage
High Side Output Voltage
V −V
10
17
V
B
HB
V
HB
−1
700
V
V
HO
V
HB
V
B
V
V
LO
GND
GND
V
CC
V
Input Voltage on LIN and HIN pins
V
,
V
−2
V
LIN
HIN
CC
V
Operating Junction Temperature Range
T
J
−40
125
°C
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <T < 125°C, V =V =12V, V = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
J
CC
B
HB
Typical values are at T = 25°C.)
J
Parameters
Test Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION
V
quiescent current
operating current
V
=V =0
I
I
0.15
2
0.25
2.5
mA
mA
mA
mA
mA
CC
CC
LIN
HIN
CCQ
V
f = 500 kHz, C
= 0
= 0
LOAD
CCO
Boot voltage quiescent current
Boot voltage operating current
HB to GND quiescent current
INPUT SECTION
V
LIN
= V
= 0 V
I
I
0.1
2
0.15
2.5
HIN
BQ
f = 500 kHz, C
LOAD
BO
V
HS
= V = 700 V
I
6
11
HB
HBQ
Input rising threshold
V
2.3
1
2.7
1.4
1.3
175
3.1
1.8
V
V
HIT
Input falling threshold
V
LIT
Input voltage Hysteresis
Input pulldown resistance
V
IHYS
V
V
= 5 V
R
100
8.6
8
250
9.6
9
kW
XIN
IN
UNDER VOLTAGE LOCKOUT (UVLO)
V
V
V
V
ON
V
CC
Rising
V
CCon
9.1
0.5
8.5
0.5
V
V
CC
CC
hysteresis
V
CChys
ON
V
B
Rising
V
Bon
V
B
B
hysteresis
V
Bhyst
V
st
High Side Startup Time
Time between V > UVLO & 1
T
10
ms
B
startup
HO Pulse
Low level output voltage
High level output voltage
I
I
= 100 mA
V
0.250
0.270
V
V
LO
LOL
= −100 mA, V
LO
= V
V
LOH
LO
−V
LOH
CC
Peak source current
Peak sink current
V
LO
V
LO
= 0 V
I
2.2
1.7
A
A
LOpullup
= 12 V
I
LOpulldown
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NCP51530
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C <T < 125°C, V =V =12V, V = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted,
J
CC
B
HB
Typical values are at T = 25°C.)
J
Parameters
HO GATE DRIVER
Test Conditions
Symbol
Min
Typ
Max
Unit
Low level output voltage
High level output voltage
I
I
= 100 mA
V
0.250
0.270
V
V
HO
HOL
= −100 mA, V
HO
= V
V
HOH
HO
–V
HOH
HB
Peak source current
Peak sink current
V
HO
V
HO
= 0 V
I
2.2
1.7
A
A
HOpullup
= 12 V
I
HOpulldown
OUTPUT RISE AND FALL TIME
Rise Time LO, HO
Fall Time LO, HO
C
C
= 1000 pF
= 1000 pF
T
8
8
15
15
ns
ns
load
load
R
T
F
DELAY MATCHING
LI ON, HI OFF
Pulse width = 1 ms
Pulse width = 1 ms
T
7
7
ns
ns
MON
LI OFF, HI ON
T
MOFF
TIMING
Minimum Input Filter (NCP51530A)
V
= 5 V , Input pulse width
T
FT
30
40
ns
XIN
above which output change oc-
curs.
PROPAGATION DELAY
NCP51530A
V
LI
V
HI
V
LI
V
HI
falling to V falling
C
= 0, Minimum On/Off−time
T
60
60
60
60
100
100
100
100
ns
ns
ns
ns
LO
load
DLFF
DHFF
DLRR
DHRR
to register as a valid change =
50 ns
falling to V falling
C
= 0, Minimum On/Off−time
load
T
T
HO
to register as a valid change =
50 ns
rising to V rising
C
= 0, Minimum On/Off−time
load
LO
to register as a valid change =
50 ns
rising to V rising
C
= 0, Minimum On/Off−time
load
T
HO
to register as a valid change =
50 ns
PROPAGATION DELAY
NCP51530B
V
LI
V
HI
V
LI
V
HI
falling to V falling
C
= 0, Minimum On/Off−time
T
25
25
25
25
40
40
40
40
ns
ns
ns
ns
LO
load
DLFF
DHFF
DLRR
DHRR
to register as a valid change =
50 ns
falling to V falling
C
= 0, Minimum On/Off−time
load
T
T
HO
to register as a valid change =
50 ns
rising to V rising
C
= 0, Minimum On/Off−time
load
LO
to register as a valid change =
50 ns
rising to V rising
C
= 0, Minimum On/Off−time
load
T
HO
to register as a valid change =
50 ns
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NCP51530
Figure 4. Propagation Delay, Rise and Fall Times
Figure 5. Delay Matching
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NCP51530
Figure 6. NCP51530 Operating Currents (No Load, VCC = 12V)
Figure 7. NCP51530 Operating Currents (1nF load, VCC = 12V)
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NCP51530
9.2
9.1
9
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
8.9
8.8
8.7
8.6
8.5
7.9
7.8
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. VCCON vs Temperature
Figure 9. VCCOFF vs Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
0
8
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
Figure 10. VCCHyst vs Temperature
TEMPERATURE (°C)
Figure 11. VBON vs Temperature
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
7.7
7.6
7.5
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
7.4
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. VBOff vs Temperature
Figure 13. VbHyst vs Temperature
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NCP51530
300
280
260
240
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
20
40
20
0
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. ICCQ vs Temperature
Figure 15. IBQ vs Temperature
100
14
12
10
8
90
80
70
60
50
40
30
20
10
6
4
2
0
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. IHB_Leakage vs Temperature
Figure 17. Low Side Turn on Propagation
Delay vs Temperature
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Low Side Turn on Propagation
Delay vs Temperature
Figure 19. High Side Turn off Propagation
Delay vs Temperature
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NCP51530
100
90
80
70
60
50
40
30
20
10
0
14
12
10
8
6
4
2
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. High Side Turn off Propagation
Delay vs Temperature
Figure 21. Low Side Rise Time vs Temperature
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. High Side Rise Time vs
Temperature
Figure 23. Low Side Fall Time vs Temperature
0
14
−20
12
10
8
−40
−60
6
−80
4
−100
−120
2
0
0
100
200
300
400
500
600
−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0
TEMPERATURE (°C)
NEGATIVE PULSE WIDTH (ns)
Figure 24. High Side Fall Time vs Temperature
Figure 25. Typical Safe Operating Area with
Negative Transient Voltage on HB Pin
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NCP51530
GENERAL DESCRIPTION
ensures operation at correct V and V voltage levels. The
CC B
For popular topologies like LLC, half bridge converters,
full bridge converters, two switch forward converter etc.
low−side high−side drivers are needed which perform the
function of both buffer and level shifter. These devices can
drive the gate of the topside MOSFETs whose source node
is a dynamically changing node. The bias for the high side
driver in these devices is usually provided through a
bootstrap circuit.
In a bid to make modern power supplies more compact
and efficient, power supply designers are increasingly
opting for high frequency operations. High frequency
operation causes higher losses in the drivers, hence reducing
the efficiency of the power supply.
NCP51530 is a 700 V high side−low side driver for
AC−DC power supplies and inverters. NCP51530 offers
best in class propagation delay, low quiescent current and
low switching current at high frequencies of operation. This
device thus enables highly efficient power supplies
operating at high frequencies.
NCP51530 is offered in two versions, NCP51530A/B.
NCP51530A has a typical 60 ns propagation delay, while
NCP51530B has propagation delay of 25 ns.
NCP51530 comes in SOIC8 and DFN10 packages.
SOIC8 package of the device is pin to pin compatible with
industry standard solutions.
NCP51530 has two independent input pins HI and LI
allowing it to be used in a variety of applications. This device
also includes features wherein, in case of floating input, the
logic is still defined. Driver inputs are compatible with both
CMOS and TTL logic hence it provides easy interface with
analog and digital controllers. NCP51530 has under voltage
lock out feature for both high and low side drivers which
output stage of NCP51530 has 2.2 A/1.7 A current
source/sink capability which can effectively charge and
discharge a 1 nF load in 15 ns.
FEATURES
INPUT STAGES
NCP51530 has two independent input pins HIN and LIN
allowing it to be used in a variety of applications. The input
stages of NCP51530 are TTL and CMOS compatible. This
ensures that the inputs of NCP51530 can be driven with
3.3 V or 5 V logic signals from analog or digital PWM
controllers or logic gates.
The input pins have Schmitt triggers to avoid noise
induced logic errors. The hysteresis on the input pins is
typically 1.3 V. This high value ensures good noise
immunity.
NCP51530 comes with an important feature wherein
outputs (HO, LO) stays low in case any of the input pin is
floating. At both the input pins there is an internal pull down
resistor to define its logic value in case the pin is left open
or NCP51530 is driven by open drain signal. The input logic
is explained in the Table 7 below.
NCP51530 input pins are also tolerant to negative voltage
below the GND pin level as long as it is within the ratings
defined in the datasheet. This tolerance allows the use of
transformer as an isolation barrier for input pulses.
NCP51530A features a noise rejection function to ensure
that any pulse glitch shorter than 30 ns will not produce any
output. These features are well illustrated in the Figure 28
below.
NCP51530B has no such filters in the input stages. The
timing diagram NCP51530B is Figure 29 below.
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NCP51530
Table 7. INPUT TABLE
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NCP51530
50ns
40ns
80ns
30ns
10ns
LIN/HIN
80ns
60ns
100ns
60ns
LO /HO
Figure 26. Input Filter (NCP51530A)
50ns
40ns
80ns
30ns
10ns
LIN/HIN
50ns
25ns
25ns
30ns
80ns
25ns
10ns
Figure 27. No Input Filter (NCP51530B)
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NCP51530
V
ON
CC
V
OFF
CC
V
CC
LIN
LO
V ON
B
V
− V
HB
B
HIN
HO
Figure 28. UVLO Timing Diagram
UNDER VOLTAGE LOCK−OUT
If the V is below the V UVLO voltage, the low side
CC
CC
NCP51530 has under voltage lockout protection on both
the high side and the low side driver. The function of the
UVLO circuits is to ensure that there is enough supply
voltages (V and V ) to correctly bias high side and low
driver output (LO) and high side driver output (HO) both
remain low.
If V is below V UVLO voltage the high side driver
B
B
output (HO) remains low. However if the V is above V
CC
B
CC
CC
side circuits. This also ensures that the gate of external
MOSFETs are driven at an optimum voltage.
UVLO voltage level, the low side driver output (LO) can
still turn on and off based on the low side driver input (LI)
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NCP51530
and is not affected by the V status. This ensures proper
charging of the bootstrap capacitor to bring the high side bias
ensures continuous operation in case of a small drop in the
bias voltage. This drop in the bias can happen when device
starts switching MOSFET and the operating current of the
device increases. The UVLO feature of the device is
explained in the Figure 30.
B
supply V above UVLO voltage.
B
Both the V and V UVLO circuits are provided with
CC
B
hysteresis feature. This hysteresis feature avoids errors due
to ground noise in the power supply. The hysteresis also
Figure 29. NCP51530 Turn ON−OFF Paths
OUTPUT STAGES
side external MOSFETs respectively. When a logic high is
The NCP51530 is equipped with two independent drivers.
The output stage of NCP51530 has 1.7 A/2.2 A current
source/sink capability which can effectively charge and
discharge a 1 nF load in 15 ns.
The outputs of NCP51530 can be turned on at the same
time and there is no internal dead−time built between them.
This allows NCP51530 to be used in topologies like two
switch forward converter.
received from input stage, Qsource turns on and V /V
CC
B
starts charging Cgs through Rg. Once the Cgs is charged to
the drive voltage level the external power MOSFET turns on
the external MOSFET to discharge to GND/HB level.
When a logic low signal is received from the input stage,
Qsource turns off and Qsink turns on providing a path for
gate terminal of
As seen in the figure, there are parasitic inductances in
charging and discharging path of the Cgs. This can result in
The figure below show the output stage structure and the
charging and discharging path of the external power
MOSFET. The bias supply V or V supply the energy to
a little dip in the bias voltages V /V . If the V /V drops
CC
B
CC
B
below UVLO the power supply can shut down the device.
CC
B
charge the gate capacitance Cgs of the low side or the top
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17
NCP51530
Figure 30. Low Side Turn−ON Propagation Delay (NCP51530A)
FAST PROPAGATION DELAY
Since NCP51530B doesn t have the input filter included,
the propagation delay are even faster. NCP51530B offers
30 ns propagation delay between input and output.
NCP51530 boasts of industry best propagation delay
between input and output. NCP51530A has a typical of
60 ns propagation delay. The best in class propagation delay
in NCP51530 makes it suitable for high frequency
operation.
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18
NCP51530
Figure 31. Low Side Turn−Off Propagation Delay (NCP51530A)
Figure 32. High Side Turn−Off Propagation Delay (NCP51530B)
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19
NCP51530
Figure 33. High Side Turn−Off Propagation Delay (NCP51530B)
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20
NCP51530
Figure 34. Bootstrap Circuit
COMPONENT SELECTION
It is recommended to use a larger value so as to cover any
variations in the gate charge and voltage with temperature.
CBOOT CAPACITOR VALUE CALCULATION
NCP51530 has two independent drivers for driving high
side and low side external MOSFETs. The bias for the high
side driver is usually provided through a bootstrap circuit. A
typical bootstrap circuit is shown in the figure 8 below.
Rboot RESISTOR VALUE CALCULATION
R
boot
resistor value is very important to ensure proper
function of the device. A high value of R
would slow
boot
down the charging of the C
while too low a value would
boot
The high side driver is biased by the C
(bootstrap
push very high charging currents for C . For NCP51530
boot
boot
capacitor). As can be seen in the circuit, C
will charge
a value between 2 W and 10 W is recommended for R
.
boot
boot
only when HB goes to GND level. Low value of C
can
boot
For example R
= 5 W
boot
result in a little dip in the bias voltages V . If the V drops
B
B
V
CC * VD
15 V * 1 V
5 W
below UVLO the power supply can shut down the high side
Iboot(pk)
+
+
+ 2.8 A
(eq. 5)
Rboot
driver. Therefore choosing the right value of C
important for a robust design.
is very
boot
Where V is the bootstrap diode forward drop.
D
An example design for C
is given below.
boot
Thus, R
value of 5 W keeps the peak current below 2.8 A.
boot
Qg + 30 nC, VCC + 15 V
(eq. 1)
(eq. 2)
(eq. 3)
HIN AND LIN INPUT FILTER
Qb + IBQ * tdischarge + 81 mC * 5 mS + 405 pC
Qtot + Qg ) Qb + 30 nC ) 405p + 30.4 pC
For PWM connection on the LIN and HIN pin of the
NCP51530, a RC is recommended to filter high frequency
input noise.
This filter is particularly important in case of NCP51530B
where no internal filter is included.
Qtot
30.4 nC
150 mV
Cboot
+
+
+ 203 nF
(eq. 4)
Vripple
The recommended value for R /R
and C /C
LIN HIN
HIN LIN
are as below.
Qg is equivalent gate charge of the FET
I
t
V
is the boot quiescent current
R
C
/R
= 100 W
= 120 pF
BQ
LIN HIN
is the discharge time for bootstrap capacitor
/C
dishcharge
HIN LIN
is the allowed ripple voltage in the bootstrap
ripple
capacitor
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21
NCP51530
VCC CAPACITOR SELECTION
P
+ V
* I
) V * I
CC CCO
(eq. 11)
operating
boot BO
V
capacitor value should be selected at least ten times
CC
+ 14 V * 0.4 mA ) 15 V * 0.4 mA + 11.6 mW
the value of C . In this case thus C
> 2 mF.
boot
VCC
I
I
is the operating current for the high side driver
is the operating current for the low side driver
BO
Rgate SELECTION
CCO
2. Power loss of driving external FET (Hard
Switching)
R
are selected to limit the peak gate current during
gate
charging and discharging of the gate capacitance. This
resistance also helps to damp the ringing due to the parasitic
inductances.
ǒ
Ǔ ) ǒQ * V
Ǔ
CC Ǔf
g
+ ǒ Q * V
P
g
drivers
boost
(eq. 12)
ǒǒ
Ǔ
ǒ
ǓǓ
+
30 nC * 14 V ) 30 nC * 15 V * 100 kHz + 87 mW
For example for a R
value of 5 W, the peak source and
gate
sink currents would be limited to the following values.
Q is total gate charge of the MOSFET
g
3. Power loss of driving external FET (Soft
Switching)
R
gate + 5W
(eq. 6)
(eq. 7)
VCC
15 V
ILO_Source
+
+
+ 2.23 A
ǒ
Ǔ ) Q
ǒ
* V
gs
boot
+ ǒ Q
CCǓǓ* f
P
* V
(eq. 13)
gs
drivers
R
Lgate ) RLOH
6.7 W
ǒǒ
Ǔ
ǒ
ǓǓ
+
4 nC * 14 V ) 4 nC * 15 V * 100 kHz + 11 mW
VCC
15 V
4. Level shifting losses
ILO_Sink
+
+
+ 2.20 A
(eq. 8)
R
Lgate ) RLOL
6.8 W
ǒ
Ǔ
Plevelshifting + Vr ) Vb * Q * f
+ 415 V * 1 nC * 100 kHz + 41.5 mW
(eq. 14)
V
CC * VDboot
14 V
IHO_Source
+
+
+ 2.09 A
(eq. 9)
Vr is the rail voltage
Q is the substrate charge on the level shifter
5. Total Power Loss (Hard Switching)
R
Lgate ) RHOH
6.7 W
(eq. 10)
V
CC * VDboot
15 V * 1 V
6.8 W
IHO_Sink
+
+
+ 2.06 A
P
total + Pdriver ) Poperating ) Plevelshifting
R
Lgate ) RHOL
(eq. 15)
+ 11.6 mW ) 87 mW ) 40 mW + 138.6 mW
TOTAL POWER DISSIPATION
Total power dissipation of NCP51530 can be calculated as
follows.
6. Junction temperature increase
tJ + RqJA * Ptotal + 183 * 0.14 + 25° C
(eq. 16)
1. Static power loss of device (excluding drivers)
while switching at an appropriate frequency.
www.onsemi.com
22
NCP51530
LAYOUT RECOMMENDATIONS
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
NCP51530 is a high speed and high current high side and
low side driver. To avoid any device malfunction during
device operation, it is very important that there is very low
parasitic inductance in the current switching path. It is very
important that the best layout practices are followed for the
PCB layout of the NCP51530. An example layout is shown
in the figure below. Some of the layout rules to be followed
are listed below.
• Keep the low side drive path LO−Q1−GND as small as
possible. This reduces the parasitic inductance in the
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
• Keep C
as near to the V pin as possible and the
−CV −GND loop as small as possible.
CC
VCC
CC
V
CC
• Keep C as near to VB pin as possible and
VB
VB−CVB−HB loop as small as possible.
• Keep the HB−GND−Q1 loop as small as possible. This
loop has the potential to produce a negative voltage
spike on the HB pin. This negative voltage spike can
cause damage to the driver. This negative spike can
increase the boot capacitor voltage above the maximum
rating and hence cause damage to the driver.
• Keep the high side drive loop HO−Q2−HB as small as
possible. This reduces the parasitic inductance in the
Figure 35. Example Layout
ORDERING INFORMATION17
Propagation Delay
†
Input filter
Package
Shipping
(ns)
Device
SOIC−8
NCP51530ADR2G
60
Yes
No
2500 / Tape & Reel
2500 / Tape & Reel
4000 / Tape & Reel
4000 / Tape & Reel
(Pb−Free)
SOIC−8
(Pb−Free)
NCP51530BDR2G
NCP51530AMNTWG
NCP51530BMNTWG
25
60
25
DFN10 4x4
(Pb−Free)
Yes
No
DFN10 4x4
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
23
NCP51530
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
24
NCP51530
PACKAGE DIMENSIONS
DFN10 4x4, 0.8P
CASE 506DJ
ISSUE O
NOTES:
B
E
A
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A
ALTERNATE CONSTRUCTION A−2 AND DETAIL B AL-
TERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
L
L
L1
ALTERNATE A−1
ALTERNATE A−2
PIN ONE
REFERENCE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
2X
DIM MIN
MAX
1.00
0.05
A3
A
A1
A3
b
0.80
0.00
0.10
0.10
C
EXPOSED Cu
MOLD CMPD
A1
0.20 REF
2X
C
0.25
0.35
TOP VIEW
D
4.00 BSC
D2
E
E2
E3
e
K
L
2.90
4.00 BSC
1.85
0.375 BSC
3.10
DETAIL B
ALTERNATE B−1
ALTERNATE B−2
0.10
C
C
A
2.05
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.80 BSC
10X
0.90
0.35
0.00
−−−
0.45
0.15
0.08
A3
SEATING
PLANE
L1
A1
C
NOTE 4
SIDE VIEW
D2
0.10 C A B
RECOMMENDED
MOUNTING FOOTPRINT*
DETAIL A
10X L
1
5
10X
0.60
3.20
PACKAGE
OUTLINE
0.10 C A B
E3
E2
4.30
2.15
0.75
1
K
10
6
10X
b
10X
0.42
e
0.80
0.10 C A B
PITCH
DIMENSIONS: MILLIMETERS
0.05
C
NOTE 3
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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◊
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