NCP5392P [ONSEMI]
2/3/4-Phase Controller for CPU Applications; 2/3/ 4相位控制器的CPU应用型号: | NCP5392P |
厂家: | ONSEMI |
描述: | 2/3/4-Phase Controller for CPU Applications |
文件: | 总32页 (文件大小:314K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCP5392P
2/3/4-Phase Controller for
CPU Applications
The NCP5392P provides up to a four-phase buck solution which
combines differential voltage sensing, differential phase current
sensing, and adaptive voltage positioning to provide accurately
regulated power for both Intel and AMD processors. Dual-edge
pulse-width modulation (PWM) combined with inductor current
sensing reduces system cost by providing the fastest initial response
to dynamic load events. Dual-edge multiphase modulation reduces
the total bulk and ceramic output capacitance required to meet
transient regulation specifications.
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MARKING
DIAGRAM
1
A high performance operational error amplifier is provided to
simplify compensation of the system. Dynamic Reference Injection
further simplifies loop compensation by eliminating the need to
compromise between closed-loop transient response and Dynamic
VID performance.
1
40
NCP5392P
AWLYYWWG
40 PIN QFN, 6x6
MN SUFFIX
CASE 488AR
In addition, NCP5392P provides an automatic power saving
feature (Auto-PSI). When Auto-PSI function is enabled, NCP5392P
will automatically detect the VID transitions and direct the Vcore
regulator in or out of low power states. As a result, the best efficiency
scheme is always chosen.
NCP5392P = Specific Device
Code
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
G
= Work Week
= Pb-Free Package
Features
•ꢀMeets Intel's VR11.1 Specifications
*Pin 41 is the thermal pad on the bottom of the device.
•ꢀMeets AMD 6 Bit Code Specifications
•ꢀDual-edge PWM for Fastest Initial Response to Transient Loading
•ꢀHigh Performance Operational Error Amplifier
•ꢀInternal Soft Start
•ꢀDynamic Reference Injection (Patent #US07057381)
•ꢀDAC Range from 0.375 V to 1.6 V
•ꢀDAC Feed Forward Function (Patent Pending)
•ꢀ 0.5% DAC Voltage Accuracy from 1.0 V to 1.6 V
•ꢀTrue Differential Remote Voltage Sensing Amplifier
•ꢀPhase-to-Phase Current Balancing
ORDERING INFORMATION
†
Device
Package
Shipping
NCP5392PMNR2G* QFN-40 2500/Tape & Reel
(Pb-Free)
*TemperatureRange: 0°C to 85°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•ꢀ“Lossless” Differential Inductor Current Sensing
•ꢀDifferential Current Sense Amplifiers for each Phase
•ꢀAdaptive Voltage Positioning (AVP)
•ꢀOscillator Frequency Range of 100 kHz – 1 MHz
•ꢀLatched Over Voltage Protection (OVP)
•ꢀGuaranteed Startup into Pre-Charged Loads
•ꢀThreshold Sensitive Enable Pin for VTT Sensing
•ꢀPower Good Output with Internal Delays
•ꢀThermally Compensated Current Monitoring
•ꢀAutomatic Power Saving (AUTO PSI Mode)
•ꢀCompatible to PSI Power Saving Requirements
•ꢀThis is a Pb-Free Device
Applications
•ꢀDesktop Processors
©ꢀ Semiconductor Components Industries, LLC, 2008
April, 2008 - Rev. 0
1
Publication Order Number:
NCP5392P/D
NCP5392P
PIN CONNECTIONS
1
2
3
4
5
6
30
29
28
27
EN
G1
VID0
VID1
VID2
VID3
VID4
DRVON
CS4
CS4N
CS3
26
25
24
23
NCP5392P
CS3N
2/3/4-PhaseBuck Controller
(QFN40)
7
8
VID5
VID6
VID7
ROSC
CS2
CS2N
CS1
9
22
21
10
CS1N
Figure 1. NCP5392P QFN40 Pin Connections (Top View)
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2
NCP5392P
VID0
VID1
VID2
VID3
VID4
Flexible DAC
VID5
VID6
VID7/AMD
Overvoltage
Protection
-
+
DAC
-
+
VSN
VSP
+
-
G1
G2
G3
Diff Amp
DIFFOUT
Error Amp
+
+
1.3 V
-
VFB
+
-
COMP
+
-
VDRP
Droop Amp
VDFB
-2/3
+
CSSUM
+
-
CS1P
CS1N
+
+
-
Gain = 6
Gain = 6
CS2P
CS2N
+
-
+
CS3P
CS3N
+
-
+
Gain = 6
Gain = 6
+
-
CS4P
CS4N
+
G4
+
-
+
Oscillator
IMON
ROSC
ILIM
DRVON
PSI
+
-
Control,
Fault Logic
and
APSI_EN
PH_PSI
ILimit
EN
Monitor
Circuits
12VMON
VR_RDY
VCC
+
-
+
4.25 V
UVLO
GND (FLAG)
Figure 2. NCP5392P Block Diagram
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NCP5392P
12V_FILTER
12V_FILTER
12V_FILTER
+5V
VTT +5V
D1
C4
C3
VTT
BST
Q1
C1
VCC
OD
IN
U2
DRH
34
35
L1
NCP5359
37
38
2
PSI
PSI
SW
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
APSI_EN
PH_PSI
APSI_EN
3
4
5
6
7
8
9
40
DRL
Q2
R2
RS1
PH_PSI
PGND
12
IMON
G1
IMON
C2
CS1
30
22
21
31
24
23
32
26
25
33
28
27
CS1P
CS1N
12V_FILTER
12V_FILTER
1
EN
39
G2
VR_RDY
CS2P
CS2N
14
13
VSN
VSP
NCP5392P
BST
G3
CS3P
CS3N
G4
VCC
OD
IN
RFB
DRH
NCP5359
SW
CFB1
RFB1
RF
15
16
17
18
DRL
DIFFOUT
COMP
VFB
CS4P
CS4N
CF
PGND
CH
29
VDRP
VDFB
DRVON
RDRP
19
20
12V_FILTER
12V_FILTER
R6
RNOR
CDFB
CSSUM
+
36
DAC
RISO1 RT2 RISO2
41
11
10
BST
RDNP
VCC
OD
IN
DRH
RLIM1
RLIM2
NCP5359
SW
DRL
PGND
12V_FILTER
12V_FILTER
BST
VCC
OD
IN
DRH
NCP5359
SW
DRL
PGND
VCCP
VSSN
Figure 3. Application Schematic for Four Phases
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NCP5392P
12V_FILTER
12V_FILTER
12V_FILTER
+5V
VTT +5V
D1
C4
C3
VTT
BST
Q1
Q2
C1
U2
37
VCC
L1
DRH
34
35
NCP5359
PSI
PSI
2
SW
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
OD
3
4
5
6
7
8
9
38
40
APSI_EN
PH_PSI
APSI_EN
DRL
R2
RS1
CS1
IN
PH_PSI
PGND
12
IMON
G1
IMON
C2
30
22
21
31
24
23
32
26
25
33
28
27
CS1P
CS1N
12V_FILTER
12V_FILTER
1
EN
39
G2
VR_RDY
CS2P
CS2N
14
13
VSN
VSP
NCP5392
BST
G3
CS3P
CS3N
G4
VCC
OD
IN
RFB
DRH
NCP5359
SW
CFB1
RFB1
RF
15
16
17
18
19
20
DRL
DIFFOUT
COMP
VFB
CS4P
CS4N
CF
PGND
CH
29
VDRP
VDFB
DRVON
RDRP
12V_FILTER
12V_FILTER
R6
RNOR
CDFB
CSSUM
+
36
DAC
RISO1 RT2 RISO2
41
11
10
BST
RDNP
VCC
OD
IN
DRH
RLIM1
RLIM2
NCP5359
SW
DRL
PGND
VCCP
VSSN
Figure 4. Application Schematic for Three Phases
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NCP5392P
12V_FILTER
12V_FILTER
12V_FILTER
+5V
VTT +5V
D1
C4
C3
VTT
BST
Q1
Q2
C1
VCC
U2
37
RNTC1
PSI
APSI_EN
PH_PSI
L1
DRH
34
35
NCP5359
2
PSI
SW
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
OD
3
4
5
6
7
8
9
38
40
DRL
APSI_EN
PH_PSI
R2
RS1
CS1
IN
PGND
12
IMON
G1
IMON
C2
30
22
21
31
24
23
32
26
25
33
28
27
CS1P
CS1N
1
EN
39
G2
VR_RDY
CS2P
CS2N
14
13
VSN
VSP
NCP5392
G3
CS3P
CS3N
G4
RFB
CFB1
RFB1
RF
15
16
17
18
19
20
DIFFOUT
COMP
VFB
CS4P
CS4N
CF
CH
29
VDRP
VDFB
DRVON
RDRP
12V_FILTER
12V_FILTER
R6
RNOR
CDFB
CSSUM
+
36
DAC
RISO1 RT2 RISO2
41
11
10
BST
RDNP
VCC
OD
IN
DRH
RLIM1
RLIM2
NCP5359
SW
DRL
PGND
VCCP
VSSN
Figure 5. Application Schematic for Two Phases
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NCP5392P
PIN DESCRIPTIONS
Pin No.
Symbol
EN
Description
1
2
Threshold sensitive input. High = startup, Low = shutdown.
Voltage ID DAC input
VID0
3
VID1
Voltage ID DAC input
4
VID2
Voltage ID DAC input
5
VID3
Voltage ID DAC input
6
VID4
Voltage ID DAC input
7
VID5
Voltage ID DAC input
8
VID6
Voltage ID DAC input
9
VID7/AMD
ROSC
Voltage ID DAC input. Pull to V (5 V) to enable AMD 6-bit DAC code.
CC
10
A resistance from this pin to ground programs the oscillator frequency according to f . This pin supplies a
SW
trimmed output voltage of 2 V.
11
ILIM
Overcurrent shutdown threshold setting. Connect this pin to the ROSC pin via a resistor divider as shown in
the Application Schematics. To disable the overcurrent feature, connect this pin directly to the ROSC pin. To
guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do
not connect this pin to any externally generated voltages.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IMON
VSP
0 mV to 900 mV analog signal proportional to the output load current. VSN referenced
Non-inverting input to the internal differential remote sense amplifier
Inverting input to the internal differential remote sense amplifier
Output of the differential remote sense amplifier
Output of the error amplifier
VSN
DIFFOUT
COMP
VFB
Compensation Amplifier Voltage feedback
VDRP
VDFB
CSSUM
CS1N
CS1
Voltage output signal proportional to current used for current limit and output voltage droop
Droop Amplifier Voltage Feedback
Inverted Sum of the Differential Current Sense inputs. Av=CSSUM/CSx = -4
Inverting input to current sense amplifier #1
Non-inverting input to current sense amplifier #1
Inverting input to current sense amplifier #2
CS2N
CS2
Non-inverting input to current sense amplifier #2
Inverting input to current sense amplifier #3
CS3N
CS3
Non-inverting input to current sense amplifier #3
Inverting input to current sense amplifier #4
CS4N
CS4
Non-inverting input to current sense amplifier #4
Bidirectional Gate Drive Enable
DRVON
G1
PWM output pulse to gate driver. 3-level output: Low = LSFET Enabled, Mid = Diode Emulation Enabled,
High = HSFET Enabled
31
32
33
34
35
36
37
G2
G3
PWM output pulse to gate driver. 3-level output (see G1)
PWM output pulse to gate driver. 3-level output (see G1)
PWM output pulse to gate driver. 3-level output (see G1)
Monitor a 12 V input through a resistor divider.
Power for the internal control circuits.
G4
12VMON
VCC
DAC
PSI
DAC Feed Forward Output
Power Saving Control. Low = power saving operation, High = normal operation. PSI signal has higher priority
over APSI_EN signal.
38
APSI_EN
APSI_EN High: Enable AUTO PSI function. When PSI = low, system will be forced into PSI mode, uncondi‐
tionally. When PSI = high, APSI_EN will determine if the system needs to be in AUTO PSI mode. Once in
AUTO PSI mode, system switches on/off PSI functions automatically based on VID change status.
39
40
VR_RDY
PH_PSI
Open collector output. High indicates that the output is regulating
PH_PSI Pin select one or two phase operation in PSI mode. PH_PSI = high, two phase operation, PH_PSI =
low, one phase operation.
FLAG
GND
Power supply return (QFN Flag)
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7
NCP5392P
PIN CONNECTIONS VS. PHASE COUNT
Number of Phases
G4
G3
G2
G1
CS4-CS4N
CS3-CS3N
CS2-CS2N
CS1-CS1N
4
Phase 4
Out
Phase 3
Out
Phase 2
Out
Phase 1
Out
Phase 4 CS
input
Phase 3 CS
input
Phase 2 CS
input
Phase 1 CS
input
3
2
Tie to
GND
Phase 3
Out
Phase 2
Out
Phase 1
Out
Tie to CSN
pin used
Phase 3 CS
input
Phase 2 CS
input
Phase 1 CS
input
Tie to
GND
Phase 2
Out
Tie to
GND
Phase 1
Out
Tie to CSN
pin used
Phase 2 CS
input
Tie to CSN
pin used
Phase 1 CS
input
MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
V
MAX
V
MIN
I
I
SINK
SOURCE
COMP
5.5 V
5.5 V
-0.3 V
10 mA
10 mA
V
DRP
-0.3 V
5 mA
1 mA
20 mA
N/A
5 mA
1 mA
20 mA
20 mA
10 mA
N/A
V–
GND + 300 mV
5.5 V
GND – 300 mV
-0.3 V
DIFFOUT
VR_RDY
VCC
5.5 V
-0.3 V
7.0 V
-0.3 V
N/A
ROSC
5.5 V
-0.3 V
1 mA
IMON Output
All Other Pins
1.1 V
5.5 V
-0.3 V
*All signals referenced to AGND unless otherwise noted.
THERMAL INFORMATION
Rating
Symbol
Value
34
Unit
°C/W
°C
Thermal Characteristic, QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level, QFN Package
R
q
JA
T
J
0 to 125
0 to +85
-55 to +150
1
T
A
°C
T
STG
°C
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM.
2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM.
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NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
ERROR AMPLIFIER
Input Bias Current (Note 3)
Test Conditions
Min
Typ
Max
Unit
-200
0
200
3
nA
V
Noninverting Voltage Range (Note 3)
Input Offset Voltage (Note 3)
Open Loop DC Gain
1.3
-
V+ = V- = 1.1 V
C = 60 pF to GND,
R = 10 KW to GND
-1.0
-
1.0
mV
dB
100
L
L
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
C = 60 pF to GND,
L
R = 10 KW to GND
-
-
-
10
80
5
-
-
-
MHz
°
L
C = 60 pF to GND,
L
R = 10 KW to GND
L
DV = 100 mV, G = - 10 V/V,
in
DV = 1.5 V – 2.5 V,
V/ms
out
C = 60 pF to GND,
L
DC Load = 125 mA to GND
Maximum Output Voltage
Minimum Output Voltage
I
I
= 2.0 mA
3.5
-
-
-
-
-
-
50
-
V
SOURCE
= 0.2 mA
mV
mA
mA
SINK
Output source current (Note 3)
Output sink current (Note 3)
DIFFERENTIAL SUMMING AMPLIFIER
VSN Input Bias Current
V
= 3.5 V
2
out
V
= 1.0 V
2
-
out
VSN Voltage = 0 V
30
mA
kW
VSP Input Resistance
DRVON = Low
DRVON = High
1.5
17
VSP Input Bias Voltage
DRVON = Low
DRVON = High
0.09
0.66
V
Input Voltage Range (Note 3)
-3 dB Bandwidth
-0.3
-
-
3.0
-
V
C = 80 pF to GND,
L
R = 10 KW to GND
10
MHz
L
Closed Loop DC Gain VS to Diffout
Maximum Output Voltage
VS+ to VS- = 0.5 to 1.6 V
0.98
3.0
-
1.0
-
1.025
V/V
V
I
= 2 mA
-
0.5
-
SOURCE
Minimum Output Voltage
I
= 2 mA
-
V
SINK
Output source current (Note 3)
Output sink current (Note 3)
INTERNAL OFFSET VOLTAGE
V
out
= 3 V
2.0
2.0
-
mA
mA
V
out
= 0.5 V
-
-
Offset Voltage to the (+) Pin of the
Error Amp and the VDRP pin
-
1.30
-
V
VDROOP AMPLIFIER
Input Bias Current (Note 3)
Non-inverting Voltage Range (Note 3)
Input Offset Voltage (Note 3)
Open Loop DC Gain
-200
0
200
3
nA
V
1.3
-
V+ = V- = 1.1 V
C = 20 pF to GND including
ESD, R = 1 kW to GND
-4.0
-
4.0
mV
dB
100
L
L
Open Loop Unity Gain Bandwidth
Slew Rate
C = 20 pF to GND including
L
ESD, R = 1 kW to GND
-
-
10
5
-
-
MHz
L
C = 20 pF to GND including
L
ESD, R = 1 kW to GND
V/ms
L
Maximum Output Voltage
Minimum Output Voltage
I
I
= 4.0 mA
3
-
-
-
-
1
V
V
SOURCE
= 1.0 mA
SINK
3. Guaranteed by design, not tested in production.
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NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VDROOP AMPLIFIER
Output source current (Note 3)
Output sink current (Note 3)
CSSUM AMPLIFIER
V
= 3.0 V
4
1
-
-
-
-
mA
mA
out
V
out
= 1.0 V
Current Sense Input to CSSUM Gain
-60 mV < CS < 60 mV
C = 10 pF to GND,
R = 10 kW to GND
-4.00
-
-3.88
4
-3.76
-
V/V
Current Sense Input to CSSUM -3 dB
Bandwidth
MHz
L
L
Current Sense Input to CSSUM
Output Slew Rate
DV = 25 mV, CL = 10 pF to
in
GND, Load = 1 k to 1.3 V
-
-15
3.0
-
4
-
-
-
-
+15
-
V/s
mV
V
Current Summing Amp Output Offset
Voltage
CSx – CSNx = 0, CSx = 1.1 V
Maximum CSSUM Output Voltage
CSx – CSxN = -0.15 V
(All Phases) I
= 1 mA
SOURCE
Minimum CSSUM Output Voltage
CSx – CSxN = 0.066 V
(All Phases) I = 1 mA
0.3
V
SINK
Output source current (Note 3)
Output sink current (Note 3)
PSI (Power Saving Control, Active Low)
Enable High Input Leakage Current
Upper Threshold
V
= 3.0 V
= 0.3 V
1
1
-
-
-
-
mA
mA
out
V
out
External 1 K Pullup to 3.3 V
-
-
-
1.0
770
-
mA
mV
mV
mV
V
V
V
650
550
100
UPPER
LOWER
UPPER
Lower Threshold
450
-
Hysteresis
- V
-
LOWER
APSI_EN (AUTO PSI Function Enable, Active High)
Enable High Input Leakage Current
Upper Threshold
External 1k Pullup to 3.3 V
-
-
-
1.0
770
-
mA
mV
mV
mV
V
V
V
650
550
100
UPPER
LOWER
UPPER
Lower Threshold
450
-
Hysteresis
- V
-
LOWER
PH_PSI (PSI Phase Selection)
Enable High Input Leakage Current
Upper Threshold
External 1k Pullup to 3.3 V
-
-
-
-
-
1.0
0.7
-
mA
V
V
UPPER
LOWER
CC
CC
Lower Threshold
V
0.3
V
DRVON
Output High Voltage
Sourcing Current for Output High
Output Low Voltage
Sinking Current for Output Low
Delay Time
Sourcing 500 mA
= 5 V
3.0
-
-
2.5
-
-
4.0
0.7
-
V
mA
V
V
CC
Sinking 500 mA
-
2.5
-
-
mA
ns
Propagation Delay from EN Low
to DRVON
10
-
Rise Time
C (PCB) = 20 pF, DV = 10% to
o
-
-
130
10
-
-
ns
ns
L
90%
Fall Time
C (PCB) = 20 pF, DV = 10% to
L o
90%
Internal Pulldown Resistance
35
-
70
-
140
2.0
kW
V Voltage when DRVON
CC
Output Valid
V
3. Guaranteed by design, not tested in production.
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NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
CURRENT SENSE AMPLIFIERS
Input Bias Current (Note 3)
CSx = CSxN = 1.4 V
-
0
-
-
nA
V
Common Mode Input Voltage Range
(Note 3)
-0.3
2.0
Differential Mode Input Voltage Range
(Note 3)
-120
-
120
mV
Input Offset Voltage
CSx = CSxN = 1.1 V,
-1.0
5.7
-
1.0
6.3
mV
V/V
Current Sense Input to PWM Gain
(Note 3)
0 V < CSx - CSxN < 0.1 V,
6.0
Current Sharing Offset CS1 to CSx
All VID codes
-2.5
-
2.5
mV
IMON
V
DRP
V
DRP
to IMON Gain
1.325 V< V
< 1.8 V
1.98
-
2
4
2.02
V/V
DRP
to IMON -3 dB Bandwidth
C = 30 pF to GND,
L
R = 100 kW to GND
MHz
L
Output Referred Offset Voltage
Minimum Output Voltage
V
V
= 1.6 V, I
= 0 mA
SOURCE
81
-
90
-
99
0.11
-
mV
V
DRP
= 1.2 V, I
= 100 mA
DRP
SINK
Output source current (Note 3)
Output sink current (Note 3)
Maximum Clamp Voltage
V
out
= 1 V
300
300
-
-
mA
mA
V
V
out
= 0.3 V
-
-
V
DRP
Voltage = 2 V,
= 100 k
-
1.15
R
LOAD
OSCILLATOR
Switching Frequency Range (Note 3)
100
200
374
800
191
354
755
1.95
-
-
1000
224
kHz
kHz
Switching Frequency Accuracy 2- or
4-Phase
R
OSC
R
OSC
R
OSC
R
OSC
R
OSC
R
OSC
= 49.9 kW
= 24.9 kW
= 10 kW
-
414
-
978
Switching Frequency Accuracy
3-Phase
kHz
V
= 49.9 kW
= 24.9 kW
= 10 kW
-
234
-
434
-
1000
2.065
R
OSC
Output Voltage
2.01
MODULATORS (PWM Comparators)
Minimum Pulse Width
Propagation Delay
F
= 800 KHz
-
-
-
30
10
-
-
-
ns
ns
V
SW
20 mV of Overdrive
0% Duty Cycle
COMP Voltage when the PWM
Outputs Remain LO
1.3
100% Duty Cycle
COMP Voltage when the PWM
Outputs Remain HI
-
2.3
-
V
PWM Ramp Duty Cycle Matching
PWM Phase Angle Error (Note 3)
VR_RDY (POWER GOOD) OUTPUT
VR_RDY Output Saturation Voltage
VR_RDY Rise Time (Note 3)
Between Any Two Phases
Between Adjacent Phases
-
90
-
-
%
15
15
°
I
= 10 mA,
-
-
-
0.4
V
PGD
External Pullup of 1 kW to 1.25
V, C = 45ꢀpF, DV = 10% to
90%
100
150
ns
TOT
o
VR_RDY Output Voltage at Powerup
(Note 3)
VR_RDY Pulled up to 5 V via
2ꢀkW, t ≤ 3 x t
-
-
1.0
V
R(VCC)
R(5V)
100 ms ≤ t
≤ 20 ms
CC
R(V
)
3. Guaranteed by design, not tested in production.
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11
NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
VR_RDY (POWER GOOD) OUTPUT
VR_RDY High – Output Leakage
Current (Note 3)
VR_RDY = 5.5 V via 1 K
-
-
-
0.2
mA
VR_RDY Upper Threshold Voltage
VCore Increasing, DAC = 1.3 V
310
270
mV
Below
DAC
VR_RDY Lower Threshold Voltage
VCore Decreasing
DAC = 1.3 V
410
370
mV
Below
DAC
VR_RDY Rising Delay
VR_RDY Falling Delay
PWM OUTPUTS
VCore Increasing
VCore Decreasing
-
-
500
5
-
-
ms
ms
Output High Voltage
Mid Output Voltage
Sourcing 500 mA
Sinking 500 mA
3.0
1.4
-
-
1.5
-
-
V
V
1.6
0.7
15
Output Low Voltage
Delay + Fall Time (Note 3)
V
C (PCB) = 50 pF,
L
DVo = V to GND
-
10
ns
CC
Delay + Rise Time (Note 3)
C (PCB) = 50 pF,
L
DVo = GND to V
-
-
10
75
15
-
ns
CC
Output Impedance – HI or LO State
Resistance to V (HI) or GND
CC
(LO)
W
2/3/4-PhASE DETECTION
Gate Pin Source Current
Gate Pin Threshold Voltage
Phase Detect Timer
60
210
15
80
240
20
150
265
27
mA
mV
ms
DIGITAL SOFT-START
Soft-Start Ramp Time
VR11 Vboot time
DAC = 0 to DAC = 1.1 V
1.0
-
1.5
ms
400
500
600
ms
VID7/VR11/AMD INPUT
VID Upper Threshold
VID Lower Threshold
VID Hysteresis
V
V
V
-
450
-
650
550
100
-
770
-
mV
mV
mV
mA
UPPER
LOWER
UPPER
- V
-
LOWER
AMD Input Bias Current
VR11 Input Bias Current (Note 3)
10
20
200
300
nA
ns
Delay before Latching VID Change
(VID De-Skewing) (Note 3)
Measured from the edge of the
st
200
-
1
VID change
AMD Upper Threshold (Note 3)
AMD Lower Threshold (Note 3)
ENABLE INPUT
2.9
V
V
2.4
-
Enable High Input Leakage Current
(Note 3)
Pullup to 1.3 V
-
200
nA
VR11 Rising Threshold
VR11 Falling Threshold
VR11 Total Hysteresis
AMD Upper Threshold
AMD Lower Threshold
-
450
-
650
550
100
1.3
770
-
mV
mV
mV
V
Rising- Falling Threshold
-
-
1.5
-
0.9
1.1
V
3. Guaranteed by design, not tested in production.
http://onsemi.com
12
NCP5392P
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < T < 85°C; 4.75 V < V < 5.25 V; All DAC Codes; C
= 0.1 mF)
A
CC
VCC
Parameter
ENABLE INPUT
Test Conditions
Min
Typ
Max
Unit
AMD Total Hysteresis
Enable Delay Time
Rising - Falling Threshold
200
mV
ms
Measure Time from Enable
Transitioning HI to when Output
Begins
2.5
4.0
CURRENT LIMIT
I
I
I
I
I
to V
to V
to V
to V
Gain
Between V
and V
- V = 450 mV
DFB
= 650 mV
0.95
1
1.05
V/V
V/V
V/V
V/V
LIM
LIM
LIM
LIM
LIM
DRP
DRP
DRP
DRP
DRP
- V
DRP
DFB
Gain in PSI 4 phase
Gain in PSI 3 phase
Gain in PSI 2 phase
Between V
and V
- V
= 450 mV
-
-
-
0.25
0.33
0.5
-
-
-
DRP
- V
DFB
= 650 mV
DRP
DFB
Between V
and V
- V
= 450 mV
DRP
- V
DFB
= 650 mV
DRP
DFB
Between V
and V
- V
= 450 mV
DRP
- V
DFB
= 650 mV
DRP
DFB
Offset
V
DRP
- V
= 520 mV
-50
-
0
50
-
mV
ns
DFB
Delay
100
OVERVOLTAGE PROTECTION
VR11 Overvoltage Threshold
DAC +150
DAC +185
DAC +200
mV
mV
VR11 PSI Overvoltage Threshold
(Note 3)
(1.6ꢀV DAC)
+150
(1.6ꢀV DAC)
+200
AMD Overvoltage Threshold (Note 3)
DAC +200
DAC +235
DAC +305
mV
mV
AMD PSI Overvoltage Threshold
(Note 3)
(1.55ꢀV DAC)
+200
(1.55ꢀV DAC)
+235
(1.55ꢀV DAC)
+305
Delay
100
ns
UNDERVOLTAGE PROTECTION
VCC UVLO Start Threshold
VCC UVLO Stop Threshold
VCC UVLO Hysteresis
DAC (FEED FORWARD FUNCTION)
Output Source Current
Output Sink Current
4
4.25
4.05
200
4.5
4.3
V
V
3.8
mV
V
V
= 3 V
0.25
1.5
3
mA
mA
V
OUT
= 0.3 V
OUT
Max Output Voltage (Note 3)
Min Output Voltage (Note 3)
VRM 11 DAC
I = 2 mA
source
I
= 2 mA
0.5
V
sink
Positive DAC Slew Rate
11
-
16.5
mV/ms
System Voltage Accuracy
(DAC Value has a 19 mV Offset Over
the Output Value)
1.0 V < DAC < 1.6 V
0.8 V < DAC < 1.0 V
0.5 V < DAC < 0.8 V
-
-
-
-
-
-
0.5
5
8
%
mV
mV
AMD DAC
Positive DAC Slew Rate
-
-
3.5
-
5
mV/ms
System Voltage Accuracy
(DAC Value has a 19 mV Offset Over
the Output Value)
1.0 V < DAC < 1.55 V
0.3750 < DAC < 0.8 V
0.5
5.0
%
mV
V
CC
V
CC
Operating Current
EN Low, No PWM
-
15
30
mA
3. Guaranteed by design, not tested in production.
http://onsemi.com
13
NCP5392P
Table 1. VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
50 mV
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
http://onsemi.com
14
NCP5392P
Table 1. VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
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15
NCP5392P
Table 1. VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
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NCP5392P
Table 1. VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
90
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
FE
FF
OFF
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NCP5392P
Table 2. AMD Processor 6-bit VID Code
(VID) Codes
Nominal V
Units
out
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
0
0
0
0
0
0
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
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NCP5392P
Table 2. AMD Processor 6-bit VID Code
(VID) Codes
Nominal V
Units
out
V
ID5
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
1
0
1
0
0
1
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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NCP5392P
FUNCTIONAL DESCRIPTION
General
High Performance Voltage Error Amplifier
The NCP5392P provides up to four-phase buck solution
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as
the controller of a voltage regulator, a capacitor from
COMP to VFB is required for stable unity gain test
configurations.
which combines differential voltage sensing, differential
phase current sensing, and adaptive voltage positioning to
provide accurately regulated power necessary for both
Intel VR11.1 and AMD CPU power system. NCP5392P has
been designed to work with the NCP5359 driver.
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2-, 3-, or 4-phase
mode. In 2-phase mode, phases 1 and 3 should be used to
drive the external gate drivers as shown in the 2-phase
Applications Schematic, G2 and G4 must be grounded. In
3-phase mode, gate output G4 must be grounded as shown
in the 3-phase Applications Schematic. In 4-phase mode
all 4 gate outputs are used as shown in the 4-phase
Applications Schematic. The Current Sense inputs of
unused channels should be connected to VCCP shown in
the Application Schematics. Please refer to table “PIN
CONNECTIONS vs. PHASE COUNTS” for details.
AUTO-PSI Function
NCP5392P makes energy saving possible without
receiving PSI signal from the CPU by wisely introducing
Auto-PSI feature. The device will monitor VID lines for
transition into/out-of Low Power States. When the VID
drops (An indication of entering power saving state), the
Auot-PSI logic will detect the transition and enable PSI
mode. On the other hand, when the VID rises (exiting
power saving mode), the Auto-PSI logic detects the
transition and exit PSI mode automatically. Auto-PSI uses
the dynamic VID(DVID) transitions of VR11.0 and
VR11.1 to shed phases. The phase shedding improves the
efficiency of the Vcore regulator eventually. In PSI mode,
the total current limit is reduced by the ratio of the phase
count left after phase shedding.
Differential Current Sense Amplifiers and Summing
Amplifier
Four differential amplifiers are provided to sense the output
current of each phase. The inputs of each current sense
amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase's current sense amplifier must
be shorted together and connected to the output as shown in
the 2- and 3-phase Application Schematics.
Auto-PSI function can be activated and deactivated by
toggling APSI_EN (PIN38), but with lower priority
compared to PSI signal. When PSI (PIN37) is pulled to low,
the system will be forced into PSI mode unconditionally,
and APSI_EN signal will be shielded.
NCP5392P can be operated up to four phases. It can be
configured as 1 or 2 phase operation when the system enter
PSI mode automatically (for example, VID down from 1.2ꢁV
to 1.1ꢁV). Choice of going down to 1 or 2 phases can be set
up by Pin40-PH_PSI. PH_PSI=high means one-phase
operation. PH_PSI=low means two-phase operation.
The current signals sensed from inductor DCR are fed into
a summing amplifier to have a summed-up output (CSSUM).
Signal of CSSUM combines information of total current of all
phases in operation.
The outputs of current sense amplifiers control three
functions. First, the summing current signal (CCSUM) of
all phases will go through DROOP amplifier and join the
voltage feedback loop for output voltage positioning.
Second, the output signal from DROOP amplifier also goes
to ILIM amplifier to monitor the output current limit.
Finally, the individual phase current contributes to the
current balance of all phases by offsetting their ramp
signals of PWM comparators.
Remote Output Sensing Amplifier(RSA)
A true differential amplifier allows the NCP5392P to
voltage feedback with respect to the V
core
measure V
ground reference point by connecting the V
core
reference
ground reference point to VSN.
core
point to VSP, and the V
core
This configuration keeps ground potential differences
between the local controller ground and the V ground
core
reference point from affecting regulation of V
and V
between
ground reference points. The RSA also
core
V
core
core
Thermal Compensation Amplifier with VDRP and VDFB
Pins
subtracts the DAC (minus VID offset) voltage, thereby
producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage as
the floating ground to allow both positive and negative
error voltages.
Thermal compensation amplifier is an internal amplifier
in the path of droop current feedback for additional
adjustment of the gain of summing current and temperature
compensation. The way thermal compensation is
implemented separately ensures minimum interference to
the voltage loop compensation network.
Precision Programmable DAC
A precision programmable DAC is provided and system
trimmed. This DAC has 0.5% accuracy over the entire
operating temperature range of the part. The DAC can be
programmed to support either Intel VR11 or AMD 6-bit
VID code specifications.
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The
oscillator's frequency is programmed by the resistance
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NCP5392P
Output Overvoltage and Undervoltage Protection and
Power Good Monitor
connected from the ROSC pin to ground. The user will
usually form this resistance from two resistors in order to
create a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100ꢁkHz per
phase to 1.0ꢁMHz per phase. The oscillator generates up to
4 symmetrical triangle waveforms with amplitude between
1.3ꢁV and 2.3ꢁV. The triangle waves have a phase delay
between them such that for 2-, 3- and 4-phase operation
the PWM outputs are separated by 180, 120, and 90 angular
degrees, respectively.
An output voltage monitor is incorporated. During normal
operation, if the output voltage is 180ꢁmV (typical) over the
DAC voltage, the VR_RDY goes low, the DRVON signal
remains high, the PWM outputs are set low. The outputs will
remain disabled until the V
voltage is removed and
CC
reapplied. During normal operation, if the output voltage falls
more than 350ꢁmV below the DAC setting, the VR_RDY pin
will be set low until the output voltage rises.
Soft-Start
There are two possible soft-start modes: AMD and
from 0 V directly
PWM Comparators with Hysteresis
VR11. AMD mode simply ramps V
to the DAC setting at a fixed rate. The VR11 mode ramps
to 1.1ꢁV boot voltage at a fixed rate of 0.8ꢁmV/mS,
core
Four PWM comparators receive an error signal at their
noninverting input. Each comparator receives one of the
triangle waves at its inverting output. The output of each
comparator generates the PWM outputs G1, G2, G3, and G4.
During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
V
core
pauses at 1.1ꢁV for around 500ꢁmS, reads the VID pins to
determine the DAC setting. Then ramps V to the final
core
DAC setting at the Dynamic VID slew rate of up to
12.5ꢁmV/mS. Typical AMD and VR11 soft-start sequences
are shown in the following graphs (Figure 9 and 10).
duty cycle calculated by V /V . During a transient event,
out in
both high and low comparator output transitions shift phase
to the points where the error signal intersects the down and
up ramp of the triangle wave.
APPLICATION INFORMATION
The NCP5392P demo board for the NCP5392P is
available by request. It is configured as a four phase
solution with decoupling designed to provide a 1ꢁmW load
line under a 100ꢁA step load.
PROTECTION FEATURES
Undervoltage Lockout
An undervoltage lockout (UVLO) senses the V input.
CC
Startup Procedure
During power-up, the input voltage to the controller is
monitored, and the PWM outputs and the soft-start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering.
Start by installing the test tool software. It is best to
power the test tool from a separate ATX power supply. The
test tool should be set to a valid VID code of 0.5ꢁV or above
in order for the controller to start. Consult the VTT help
manual for more detailed instruction.
Overcurrent Shutdown
Step Load Testing
A programmable overcurrent function is incorporated
within the IC. A comparator and latch make up this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels - effectively disabling
overcurrent shutdown. The comparator noninverting input
is the summed current information from the VDRP minus
offset voltage. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are pulled low, and the soft-start is pulled low. The
The VTT tool is used to generate the d /d step load.
t
i
Select the dynamic loading option in the VTT test tool
software. Set the desired step load size, frequency, duty,
and slew rate. See Figure 6.
outputs will remain disabled until the V
voltage is
CC
removed and re-applied, or the ENABLE input is brought
low and then high.
Figure 6. Typical Load Step Response
(full load, 35 A - 100 A)
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NCP5392P
Dynamic VID Testing
Understanding Soft-Start
The VTT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5ꢁV or
greater and set the highest VID to a value that is greater than
the lowest VID selection, then enable the test. See Figures
7 and 8.
The controller supports two different startup routines. An
AMD ramp to the initial VID code, or a VR11 Ramp to the
1.1ꢁV boot voltage, with a pause to capture the VID code
then resume ramping to target value based on internal slew
rate limit. The initial ramp rate was set to be 0.8 mV/mS.
Figure 9. VR11.1 Startup
Figure 7. 1.6 V to 0.5 V Dynamic VID response
Figure 10. AMD Startup
Figure 8. Dynamic VID Settling Time Rising
(CH1: VID1, CH2: DAC, CH3:VCCP)
Programming the Current Limit and the Oscillator
Frequency
The demo board is set for an operating frequency of
pin provides a 2.0ꢁV
Design Methodology
approximately 330ꢁkHz. The R
OSC
reference voltage which is divided down with a resistor
divider and fed into the current limit pin ILIM. Then
calculate the individual RLIM1 and RLIM2 values for the
divider. The series resistors RLIM1 and RLIM2 sink
current from the ILIM pin to ground. This current is
Decoupling the VCC Pin on the IC
An RC input filter is required as shown in the V pin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between 5ꢁV supply and the IC.
CC
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NCP5392P
internally mirrored into a capacitor to create an oscillator.
The current limit function is based on the total sensed
current of all phases multiplied by a controlled gain
(Acssum*Adrp). DCR sensed inductor current is a function
of the winding temperature. The best approach is to set the
maximum current limit based on expected average
maximum temperature of the inductor windings,
The period is proportional to the resistance and frequency
is inversely proportional to the total resistance. The total
resistance may be estimated by Equation 1. This equation
is valid for the individual phase frequency in both three and
four phase mode.
Rosc ^ 20947 FSWā*1.1262
30.5ꢀkW ^ 20947 330*1.1262
(eq. 1)
(eq. 2)
DCRTmax + DCR25C(1 ) 0.00393 @ (Tmax * 25))
60
50
40
30
20
10
Calculation
Real
0
100
1000
Freq-kHz
Figure 11. ROSC vs. Frequency
For multiphase controller, the ripple current can be calculated as,
(Vin * N @ Vout) @ Vout
(eq. 3)
(eq. 4)
Ipp +
L @ FSW @ Vin
Therefore calculate the current limit voltage as below,
VLIMIT ^ ACSSUM @ ADRP @ DCRTmax @ (IMIN_OCP @ ) 0.5 @ Ipp)
(Vin * N @ Vout) @ Vout
@ ǒ
are the gain of current summing amplifier and droop amplifier.
Ǔ
VLIMIT ^ ACSSUM @ ADRP @ DCRTmax
IMIN_OCP @ ) 0.5 @
L @ FSW @ Vin
In Equation 4, A
and A
CSSUM
DRP
Acssum
Adrp
RNOR
R
temperature sense resistor placed near inductor. R
and R
are in series with R , the NTC
is
ISO1
ISO2 T2
SUM
RISO1
RSUM
the resistor connecting between pin VDFB and pin
CSSUM. If PSI = 1, PSI function is off, the current limit
follows the Equation 7; if PSI = 0, the power saving mode
will be enabled, COEpsi is a coefficient for the current
limiting related with power saving function (PSI), the
current limit can be calculated from Equation 8. COEpsi
value is one over the original phase count N. Refer to the
PSI and phase shedding section for more details.
RISO2
I1
RT2
-
+
I2
I3
I4
+
+
-
OCP
event
Ilim
Figure 12. ACSSUM and ADRP
As introduced before, V
comes from a resistor
LIMIT
divider connected to Rosc pin, thus,
RLIM2
(eq. 5)
(eq. 6)
VLIMIT + 2ꢀV @
RLIM1 ) RLIM2
@ COEpsi
ACSSUM + *4
RNOR @ (RISO1 ) RISO2 ) RT2
)
ADRP + *
(RNOR ) RISO1 ) RISO2 ) RT2) @ RSUM
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NCP5392P
Final Equations for the Current Limit Threshold
Final equations are described based on two conditions: normal mode and PSI mode.
2V@R
LIM2
R
)R
(Vin * N @ Vout) @ Vout
L @ FSW @ Vin
LIM1
LIM2
ILIMIT(normal) ^
* 0.5 @
R
@(R
)R )R
ISO2
)
T2
)R )@R
SUM
NOR
)R
ISO1
4 @ (R
@ DCR25C(1 ) 0.00393 @ (Tinductor * 25))
@ COEpsi
LIM2
(eq. 7)
)R
T2
NOR
ISO1
ISO2
2V@R
LIM2
)R
R
(Vin * Vout) @ Vout
L @ FSW @ Vin
LIM1
)R )
ISO2
ILIMIT(PSI) ^
* 0.5 @
(eq. 8)
R
@(R
)R
T2
@ DCR25C(1 ) 0.00393 @ (Tinductor * 25))
)R )@R
SUM
NOR
)R
ISO1
)R
4 @ (R
T2
NOR
ISO1
ISO2
Inductor Current Sensing Compensation
N is the number of phases involved in the circuit.
The inductors on the demo board have a DCR at 25°C of
0.6ꢁmW. Selecting the closest available values of 21.3 kW
The NCP5392P uses the inductor current sensing
method. An RC filter is selected to cancel out the
impedance from inductor and recover the current
information through the inductor's DCR. This is done by
matching the RC time constant of the sensing filter to the
L/DCR time constant. The first cut approach is to use a 0.1
mF capacitor for C and then solve for R.
for R
and 9.28 kW for R
yields a nominal
operating frequency of 330 kHz. Select R 1 = 1ꢁk, R
LIM1
LIM2
ISO
ISO2
= 1 k, R = 10 K (25°C), R
/R
= 2, (refer to
T2
NOR SUM
application diagram). That results to an approximate
current limit of 133ꢁA at 100°C for a four phase operation
and 131ꢁA at 25°C. The total sensed current can be
observed as a scaled voltage at the VDRP with a positive
no-load offset of approximately 1.3 V.
(eq. 9)
L
Rsense(T) +
0.1 @ mF @ DCR25C @ (1 ) 0.00393(T * 25))
Because the inductor value is a function of load and
inductor temperature final selection of R is best done
Inductor Selection
When using inductor current sensing it is recommended
that the inductor does not saturate by more than 10% at
maximum load. The inductor also must not go into hard
saturation before current limit trips. The demo board
includes a four phase output filter using the T44-8 core
from Micrometals with 3 turns and a DCR target of 0.6ꢁmW
@ 25°C. Smaller DCR values can be used, however,
current sharing accuracy and droop accuracy decrease as
DCR decreases. Use the NCP5392P design aide for
regulation accuracy calculations for specific value of DCR.
experimentally on the bench by monitoring the V
droop
and performing a step load test on the actual solution.
pin
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NCP5392P
Simple Average SPICE Model
A simple state average model shown in Figure 13 can be used to determine a stable solution and provide insight into the
control system.
GAIN = 1
{-2/3*4}
E1
+
+
-
-
Voff
E
GAIN = {6}
V3
12V
0
0
L
LBRD
100p
RBRD
0.75m
DCR
{0.6E-3/4}
2
1
{185e-9/4}
1
2
0
12
CCer
{22e-6*18}
CBulk
{560e-6*6}
VRamp_min
I1 = 50
I2 = 110
TD = 100u
RSUM
1k
1.3V
ESRCer
{1.5e-3/18}
I1
ESRBulk
{7e-3/6}
TR = 50n
0Aac
0Adc
2
2
22p
CDFB
Vdrp
RDFB
2k
TF = 50n
PW = 100u
PER = 200u
ESLCer
{1.5e-9/18}
Vout
ESLBulk
{3.5e-9/6}
1E3
R8
1k
Voff
1
1
C5
10.6p
RDAC CDAC
0
0
VDAC
50
12n
DC = 1.2V
AC = 0
R12
5.11k
CFB1
680P
CH
RFB1
69.8
TRAN = PULSE
(0 0.05 400u 5u 5u 500u 1000u)
22p
RFB
RF
2.2k
CF
1.8n
R6
0
1k
Voff
1E3
R11
1k
Vdrp
Voffset
1.3V
1k
C4
10.6p
R10
2k
Unity Gain BW=15MHz
1E3
0
0
R9
C6
0
Voff
IMON
1k 10.6p
Figure 13. NCP5392P Average SPICE Model
Compensation and Output Filter Design
If the required output filter and switching frequency are
significantly different, it's best to use the available PSPICE
models to design the compensation and output filter from
scratch.
plus the board impedance is 1.15 mW + 0.75 mW or
1.9 mW. The actual output filter impedance does not drop
to 1.0 mW until the ceramic breaks in at over 375 kHz. The
controller must provide some loop gain slightly less than
one out to a frequency in excess 300 kHz. At frequencies
below where the bulk capacitance ESR breaks with the
bulk capacitance, the DC-DC converter must have
sufficiently high gain to control the output impedance
completely. Standard Type-3 compensation works well
with the NCP5392P.
The design target for this demo board was 1.0 mW up to
2.0 MHz. The phase switching frequency is currently set to
330 kHz. It can easily be seen that the board impedance of
0.75 mW between the load and the bulk capacitance has a
large effect on the output filter. In this case the six 560 mF
bulk capacitors have an ESR of 7.0 mW. Thus the bulk ESR
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NCP5392P
Zout Open Loop
Zout Closed Loop
Open Loop Gain with Current Loop Closed
Voltage Loop Compensation Gain
80
60
40
20
0
-20
-40
-60
1mOhm
-80
-100
100
1000
10000
100000
1000000
10000000
Frequency
Figure 14. NCP5392P Circuit Frequency Response
CH
CF
The goal is to compensate the system such that the
resulting gain generates constant output impedance from
DC up to the frequency where the ceramic takes over
holding the impedance below 1.0 mW. See the example of
the locations of the poles and zeros that were set to optimize
the model above.
CFB1
RFB1
RF
I Bias
RFB
-
+
-
+
Error
Amp
1.3 V
Droop
Amp
RDRP
RISO2
PWM
Comparator
By matching the following equations a good set of
starting compensation values can be found for a typical
mixed bulk and ceramic capacitor type output filter.
+
-
RNOR
RT
1.3 V
RISO1
RSUM
Gain = 4
-
1
1
+
(eq. 10)
(eq. 11)
2p @ CF @ RF
2p @ (RBRD ) ESRBulk) @ CBulk
+
CSSUM
Amp
1.3 V
1
1
RSx
+
+
2p @ CFB1 @ (RFB1 ) RFB)
2p @ C
@ (RBRD ) ESR
)
Bulk
Cer
+
-
RL
+
R
should be set to provide optimal thermal
compensation in conjunction with thermistor R , R
FB
CSx
Gain = 1
T2
ISO1
and R
. With R set to 1.0 kW, R
FB
is usually set to
ISO2
FB1
100 W for maximum phase boost, and the value of RF is
typically set to 3.0 kW.
Figure 15. Droop Injection and Thermal
Compensation
RDRP determines the target output impedance by the
basic equation:
Droop Injection and Thermal Compensation
The VDRP signal is generated by summing the sensed
output currents for each phase. A droop amplifier is added
to adjust the total gain to approximately eight. VDRP is
externally summed into the feedback network by the
resistor RDRP. This introduces an offset which is
proportional to the output current thereby forcing a
controlled, resistive output impedance.
RFB @ DCR @ ACSSUM @ ADRP
V
out + Zout
Iout
+
(eq. 12)
RDRP
RFB @ DCR @ ACSSUM @ ADRP
RDRP
+
(eq. 13)
Zout
The value of the inductor's DCR is a function of
temperature according to the Equation 14:
DCRꢀ(T) + DCR25C @ (1 ) 0.00393 @ (T * 25))
(eq. 14)
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NCP5392P
Actual DCR increases by temperature, the system can be
thermally compensated to cancel this effect to a great
degree by adding an NTC in parallel with R to reduce
temperature. The series resistor is split and inserted on both
sides of the NTC to reduce noise injection into the feedback
loop. The recommended total value for R
approximately 1.0 kW.
plus R
is
NOR
ISO1
ISO2
the droop gain as the temperature increases. The NTC
device is nonlinear. Putting a resistor in series with the NTC
helps make the device appear more linear with
The output impedance varies with inductor temperature
by the equation:
RFB @ DCR25C @ (1 ) 0.00393 @ (T * 25)) @ ACSSUM @ ADRP
(eq. 15)
(eq. 16)
Zout(T) +
RDRP
By including the NTC R and the series isolation resistors the new equation becomes:
T2
R
@(R
)R )R
ISO2
)R
)
T2
)R )@R
SUM
NOR
)R
ISO1
RFB @ DCR25C @ (1 ) 0.00393 @ (T * 25)) @ ACSSUM
@
(R
T2
NOR
ISO1 ISO2
Zout(T) +
RDRP
Acssum
Adrp
RNOR
The typical equation of an NTC is based on a curve fit
Equation 17
RISO1
RISO2
1
1
298
I1
ƪǒ
Ǔ*ǒ Ǔƫ
RT2
273)T
(eq. 17)
RT2(T) + RT225C @ eb
I2
I3
I4
-
+
+
RSUM
The demo board use a 10 kW NTC with a b value of 3740.
Figure 16 shows the comparison of the compensated output
impedance and uncompensated output impedance varying
with temperature.
+
-
OCP
event
Ilim
Imon
+
-
0.0013
Zout
Zout(uncomp)
0.0012
Gain = 2
0.0011
0.001
Figure 17. IMON Circuit
0.0009
0.0008
0.0007
0.0006
Vimon vs. Iout
1.05
0.84
0.63
0.42
0.21
0
25
45
65
85
105
Celsius
Figure 16. Zout vs. Temperature
IMON for Current Monitor
Since VDRP signal reflects the current information of all
phases. It can be fed into the IMON amplifier for current
monitoring as shown in Figure 17. IMON amplifier has a
fixed gain of 2 with an offset when VDRP is equal to 1.3ꢁV,
the internal floating reference voltage. The IMON
amplifier will be saturated at an maximum output of 1.09ꢁV
therefore the total gain of current should be carefully
considered to make the maximum load current indicated by
the IMON output. Figure 18 shows a typical of the relation
between IMON output and the load current.
0
10 20 30 40 50 60 70 80 90 100
Iout-A
Figure 18. IMON Output vs. Output Current
Power Saving Indicator (PSI) and Phase Shedding
VR11.1 requires the processor to provide an output
signal to the VR controller to indicate when the processor
is in a low power state. NCP5392P use the status of PSI pin
to decide if there is a need to change its operating state to
maximize efficiency at light loads. When PSI = 0, the PSI
function will be enabled, and VR system will be running at
a single phase power saving mode.
The PSI signal will de-assert 1 ms prior to moving to a
normal power state.
At power saving mode, NCP5392P works with the
NCP5359 driver to represent diode emulation mode at light
load for further power saving.
When system switches on PSI function, a phase shedding
will be presented. Only one or two phases (depending on
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27
NCP5392P
Auto-PSI Function:
PH_PSI) are active in the emulation mode while other
phases are shed. Figure 19 indicates a PSI-on transition
from a 3-phase mode to a single phase mode. While staying
stable in PSI mode, the PWM signal of phase 1 will vary
from a mid-state level (1.5 V typical) to high level while
other phases all go to mid-state level. Vice verse, when PSI
signal goes high, the system will go back to the original
phase mode such as shown in Figure 20.
In Auto-PSI mode (APSI_EN=1, PSI=1), the device will
monitor VID lines for transition into/out-of Low Power
States. Figure 21 to 24 describe the Auto-PSI function
during VID transitions, in one-phase and two-phase
operation respectively.
Figure 21. 10 A Load, VID Down, into PSI (One Phase)
Figure 19. PSI turns on, CH1: PWM1, CH2: PWM2,
CH3: PWM3, CH4: PSI
Figure 22. 10 A Load, VID Up, Out of PSI (One Phase)
Figure 20. PSI turns off, CH1: PWM1, CH2: PWM2,
CH3: PWM3, CH4: PSI
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28
NCP5392P
voltage even during a dynamic change in the VID setting
during operation.
Figure 23. 10 A Load, VID Down, into PSI (Two Phase)
Figure 25. VR11.1, 1.6 V OVP Event
Figure 26. AMD, 1.55 V OVP Event
Gate Driver and MOSFET Selection
Figure 24. 10 A Load, VID Up, Out of PSI
(Two Phase)
ONꢁSemiconductor provides the NCP5359 as
a
OVP Improved Performance
companion gate driver IC. The NCP5359 driver is
optimized to work with a range of MOSFETs commonly
used in CPU applications. The NCP5359 provides special
functionality including power saving mode operation and
is required for high performance dynamic VID operation.
Contact your local ONꢁSemiconductor applications
engineer for MOSFET recommendations.
The overvoltage protection threshold is not adjustable.
OVP protection is enabled as soon as soft-start begins and
is disabled when part is disabled. When OVP is tripped, the
controller commands all four gate drivers to enable their
low side MOSFETs and VR_RDY transitions low. In order
to recover from an OVP condition, V must fall below the
CC
UVLO threshold. See the state diagram for further details.
The OVP circuit monitors the output of DIFFOUT. If the
DIFFOUT signal reaches 180 mV (typical) above the
nominal 1.3ꢁV offset the OVP will trip and VRRDY will be
pulled low, after eight consecutive OVP events are
detected, all PWMs will be latched. The DIFFOUT signal
is the difference between the output voltage and the DAC
voltage (minus 19 mV if in VR11.1 modes) plus the 1.3ꢁV
internal offset. This results in the OVP tracking on the DAC
Board Stackup and Board Layout
Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further information or layout review contact
ONꢁSemiconductor.
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29
NCP5392P
SYSTEM TIMING DIAGRAM
12 V (Gate Driver)
5 V (Controller)
UVLO
UVLO
EN
3.5 ms
VID
Valid VID
DRVON
1 ms min
1.5 ms
500 ms
VSP-VSN
VR_RDY
500 ms
Figure 27. Normal Startup
12 V (Gate Driver)
UVLO
5 V (Controller)
UVLO
POR
EN
3.5 ms
DRVON
VID
Valid VID
1 ms min
1.5 ms
500 ms
1 ms
VSP-VSN
VR_RDY
500 ms
Figure 28. Driver UVLO Limited Startup
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30
NCP5392P
1
2
3
4
5
6
7
8
185 mV
Diffout ~ 1.3 V
VR_RDY
DRVON = High
1
2
3
4
5
6
7
8
185 mV
VSP = VID - 19 mV
Figure 29. OVP Shutdown
I
+ 1.3
limit
VDRP
VR_RDY
DRVON
Figure 30. Non-PSI Current Limit
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31
NCP5392P
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 488AR-01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A B
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
2X
0.15
C
0.18
0.30
D
D2
E
E2
e
L
6.00 BSC
TOP VIEW
2X
0.15
C
4.00
4.20
6.00 BSC
4.00 4.20
0.50 BSC
(A3)
0.10
C
C
0.30
0.20
0.50
---
A
K
40X
0.08
SIDE VIEW
D2
A1
SOLDERING FOOTPRINT*
SEATING
PLANE
C
6.30
4.20
L
40X
K
40X
11
20
40X
21
10
0.65
EXPOSED PAD
1
E2
4.20 6.30
40X b
1
30
0.10
0.05
C
C
A B
40
31
36X
e
BOTTOM VIEW
40X
36X
0.50 PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
The products described herein (NCP5392P), is covered by one or more of the following U.S. patent; US07057381. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5392P/D
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