NCP81141MNTXG [ONSEMI]
Vr12.6 单相控制器;
| 型号： | NCP81141MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | Vr12.6 单相控制器 控制器 |
| 文件： | 总24页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81141
Single-Phase Controller
with SVID Interface for
Desktop and Notebook CPU
Applications
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MARKING
The NCP81141 Single−Phase buck solution is optimized for Intel
VR12.6 compatible CPUs. The controller combines true differential
voltage sensing, differential inductor DCR current sensing, input
voltage feed−forward, and adaptive voltage positioning to provide
accurately regulated power for both Desktop and Notebook
applications. The single phase controller uses DCR current sensing
providing the fastest initial response to dynamic load events at reduced
system cost.
DIAGRAM
NCP
81141
ALYWG
G
1
QFN28
CASE 485AR
The NCP81141 incorporates an internal MOSFET driver for
improved system efficiency. High performance operational error
amplifiers are provided to simplify compensation of the system.
Patented Dynamic Reference Injection further simplifies loop
compensation by eliminating the need to compromise between
closed−loop transient response and Dynamic VID performance.
Patented Total Current Summing provides highly accurate digital
current monitoring.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Features
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
• Meets Intel™ VR12.6 Specifications
• High Performance Operational Error Amplifier
• Digital Soft Start Ramp
• Dynamic Reference Injection
• “Lossless” DCR Current Sensing
• Adaptive Voltage Positioning (AVP)
• Switching Frequency Range of 250 kHz – 1 MHz
• VIN Range 4.5 V − 25 V
• Startup into Pre−Charged Load While Avoiding False OVP
• Vin Feed Forward Ramp Slope
• Over Voltage Protection (OVP) and Under Voltage Protection (UVP)
• Over Current Protection (OCP)
• VR−RDY Output with Internal Delays
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Desktop and Notebook Processors
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
September, 2015 − Rev. 2
NCP81141/D
NCP81141
NCP81141
Figure 1. Block Diagram for NCP81141
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2
NCP81141
C OMP
1
F B
1
1
D I F F O U T
2
1
1
2
1
2
1
2
R O S C
C O M P
2 2
V B O O T
1
2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
1 4
F B
S T E N S E
1 3
1 2
D I F F O U T
L G
P G N D
V S N
V S P
V C C
1 1
1 0
S W
H G
B S T
9
8
A D E P
1
2
1
2
8
4
1
1
2
2
1
2
C S C O M P
1
1
1
2
2
2
1
1
2
D N P
R 1 6 0
1
1
2
2
2
7 5
7
R 1 5
1
2
D N P
R 1 5 9
5 6 1 R 5 4 . 9
1
2
D N P
R 1 5 8
1
6 4 5 . 5 9 1 R
1
1
1
2
1
2
2
1
Figure 2. Controller Application Schematic
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NCP81141
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
8
7
6
5
1
2
3
8
7
6
5
1
2
3
1
1
1
2
Figure 3. Power Stage Typical Schematic
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NCP81141
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ENABLE
1
2
3
4
5
6
7
ILIM
VR_HOT
SDIO
IOUT
CSCOMP
CSSUM
CSREF
IMAX
NCP81141
ALERT
SCLK
TAB: GROUND
VR_RDY
VRMP
PVCC
8
9
10
11
12
13
14
Figure 4. NCP81141 Pin Configurations
NCP81141 SINGLE ROW PIN DESCRIPTIONS
Pin No.
Symbol
ENABLE
VR_HOT#
SDIO
Description
1
2
3
4
5
6
7
Logic input. Logic high enables both outputs and logic low disables both outputs
Thermal logic output for over temperature
Serial VID data interface
ALERT#
SCLK
Serial VID ALERT#
Serial VID clock
VR_RDY
VRMP
Open drain output. High indicates that the output is regulating
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used
to control the ramp of PWM slope
8
BST
HG
High−Side bootstrap supply for phase 1
High side gate driver output for phase 1
Current return for high side gate driver 1
Power Ground for gate driver
9
10
11
12
13
14
SW
PGND
LG
Low−Side gate driver output for phase 1
Temp Sense input for the single phase converter
TSENSE
VBOOT
An input pin to adjust the boot−up voltage. During start up it is used to program VBOOT with a
resistor to ground
15
16
17
18
19
20
21
PVCC
IMAX
Power Supply for gate driver, recommended decoupling 2.2 mF
Imax Input Pin. During start up it is used to program IMAX with a resistor to ground
Total output current sense amplifier reference voltage input
Inverting input of total current sense amplifier
CSREF
CSSUM
CSCOMP
IOUT
Output of total current sense amplifier
Total output current monitor
ILIM
Over current shutdown threshold setting. Resistor to CSCOMP to set threshold
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NCP81141
NCP81141 SINGLE ROW PIN DESCRIPTIONS
Pin No.
22
Symbol
ROSC
COMP
FB
Description
A resistance from this pin to ground programs the oscillator frequency
Output of the error amplifier and the inverting input of the PWM comparator
Error amplifier voltage feedback
23
24
25
DIFFOUT
VSN
Output of the differential remote sense amplifier
26
Inverting input to differential remote sense amplifier
27
VSP
Non−inverting input to the differential remote sense amplifier
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
28
VCC
29
FLAG/GND
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NCP81141
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
COMP
CSCOMP
VSN
V
V
MIN
MAX
V
V
+ 0.3 V
−0.3 V
−0.3 V
CC
+ 0.3 V
CC
GND + 300 mV
GND – 300 mV
−0.3 V
DIFFOUT
VR_RDY
VCC
V
+ 0.3 V
+ 0.3 V
CC
CC
V
−0.3 V
6.5 V
−0.3 V
ROSC
V
CC
+ 0.3 V
−0.3 V
IOUT
2.0 V
−0.3 V
VRMP
+25 V
35 V
−0.3 V
SW
−5 V
40 V ≤ 50 ns
−10 V ≤ 200 ns
BST
35 V wrt/ GND 40 V ≤ 50 ns
wrt/GND
−0.3 V wrt/SW
6.5 V wrt/ SW
LG
V
CC
+ 0.3 V
−0.3 V
−5 V ≤ 200 ns
HG
BST + 0.3 V
−0.3 V wrt/ SW
−2 V ≤ 200 ns wrt/SW
All Other Pins
V
CC
+ 0.3 V
−0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Symbol
Typ
Unit
Thermal Characteristic
QFN Package (Note 1)
R
68
°C/W
q
JA
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
T
−40 to +125
−40 to +100
−40 to +150
1
°C
°C
°C
J
T
STG
Moisture Sensitivity Level
QFN Package
MSL
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
ERROR AMPLIFIER
Test Conditions
Min
Typ
Max
Unit
Input Bias Current
@ 1.3 V
−21
21
mA
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
20
25
dB
Open Loop Unity Gain Bandwidth
Slew Rate
CL = 20 pF to GND,
RL = 10 kW to GND
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
V/ms
DC Load = 10k to GND
Maximum Output Voltage
I
= 2.0 mA
3.5
V
V
SOURCE
I
= 2.0 mA
1
Minimum Output Voltage
SINK
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
VSP, CSREF = 1.3 V
−12
−0.3
−0.3
12
3.0
0.3
mA
V
VSP Input Voltage Range
VSN Input Voltage Range
V
CL = 20 pF to GND,
RL = 10 kW to GND
−3dB Bandwidth
10
MHz
V/V
VS+ to VS− = 0.5 to 1.3 V
Closed Loop DC gain
1.0
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos), (Note 3)
Input Bias Current
−300
−7.5
300
7.5
mV
nA
CSSUM = CSREF = 1 V
Open Loop Gain
80
10
dB
Current Sense Unity Gain Bandwidth
C = 20 pF to GND,
L
MHz
R = 10 kW to GND
L
INPUT SUPPLY
Supply Voltage Range
4.75
5.25
18
V
mA
mA
mA
mA
V
EN = high, PS0, PS1 Mode
EN = high, PS3 Mode
EN = high, PS4 Mode (@ 25°C)
EN = low
15
8.0
12
VCC Quiescent Current
200
50
VCC rising
4.5
4.1
UVLO Threshold
VCC falling
4.0
3.0
V
VCC UVLO Hysteresis
160
mV
V
VRMP rising
VRMP falling
UVLO Threshold
V
DAC SLEW RATE
Soft Start Slew Rate
Slew Rate Slow
Fast_SR/4
mV/ms
mV/ms
Fast_SR/2
Fast_SR/4
Fast_SR/8
Fast_SR/16
Slew Rate Fast
48
mV/ms
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
1.0
Unit
ENABLE INPUT
Enable High Input Leakage Current
Upper Threshold
External 1k pull−up to 3.3 V
mA
V
V
0.8
UPPER
LOWER
Lower Threshold
V
0.3
V
Total Hysteresis
V
– V
90
10
mV
UPPER
LOWER
IOUT OUTPUT
Input Referred Offset Voltage
Output Source Current
Current Gain
Ilimit to CSREF
Ilimit sink current = 80 mA
−5.5
9.75
5.5
850
mV
mA
(IOUT
) / (ILIMIT
),
10.25
CURRENT
CURRENT
R
= 20k, R
0.8 V, 1.25 V, 1.52 V
= 5.0k , DAC =
ILIM
IOUT
OSCILLATOR
Switching Frequency Range
ZERO CURRENT DETECT (ZCD)
ZCD threshold, DCM detection
250
1200
kHz
mV
V
SW wrt PGND
−0.5
2.9
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold During Soft
Start
CSREF
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP rising
VSP rising
350
400
50
440
mV
ns
Under Voltage Protection
VCC rising
250
255
300
300
5
350
325
mV
mV
ms
VCC falling
Under Voltage Delay
Ckt in development
OVERCURRENT PROTECTION
ILIM Threshold Current (OCP shutdown after
50 ms delay)
(PS0) Rlim = 20k
(PS0) Rlim = 20k
9.0
10
15
10
15
11.0
16.5
mA
mA
mA
mA
ILIM Threshold Current (immediate OCP
shutdown)
13.5
ILIM Threshold Current (OCP shutdown after
50 ms delay)
(PS1, PS2, PS3) Rlim = 20k
ILIM Threshold Current (immediate OCP
shutdown)
(PS1, PS2, PS3) Rlim = 20k, PS0
mode
VR_HOT#
Output Low Voltage
Output Leakage Current
TSENSE
I_
= −4 mA
0.3
1.0
V
VRHOT
High Impedance State
−1.0
mA
Alert# Assert Threshold
Alert# De−assert Threshold
VRHOT Assert Threshold
VRHOT Rising Threshold
TSENSE Bias Current
ADC
491
513
472
494
120
mV
mV
mV
mV
mA
115
0
125
2
Voltage Range
V
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
ADC
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time
−1.25
1.25
1
%
LSB
%
8−bit, no missing codes
1
30
90
ms
Round Robin
ms
VR_RDY,(Power Good) Output
Output Low Saturation Voltage
Rise Time
I
= 4 mA
0.3
V
VR_RDY
External pull−up of 1 kW to 3.3 V,
= 45 pF, DVo = 10% to 90%
100
10
ns
C
TOT
Fall Time
External pull−up of 1KW to 3.3V,
= 45 pF, DVo = 90% to 10%
ns
C
TOT
Output Voltage at Power−up
VR_RDY pulled up to 5 V via 2 kW
VR_RDY = 5.0 V
1.2
1.0
V
Output Leakage Current When High
VR_RDY Delay (rising)
−1.0
mA
ms
ms
DAC = TARGET to VR_RDY
From OCP or OVP
50
5
VR_RDY Delay (falling)
HIGH−SIDE MOSFET DRIVER
Pull−up Resistance, Sourcing Current
High Side Driver Sourcing Current
Pull−down Resistance, Sinking Current
High Side Driver Sinking Current
HG Rise Time
BST = PVCC
BST = PVCC
BST = PVCC
BST = PVCC
1.2
4.17
0.8
2.9
2.2
W
A
W
A
6.25
16
V
V
= 5 V, 3 nF load, BST−SW =
5 V
6.0
6.0
30
30
ns
CC
HG Fall Time
= 5 V, 3 nF load, BST−SW =
5 V
11
ns
CC
DRVH Turn−Off Propagation Delay tpdh
C
C
= 3 nF
= 3 nF
4.0
15
30
40
ns
ns
DRVH
LOAD
LOAD
HG Turn on Propagation Delay tpdl
30
1.9
1.9
DRVH
SW Pull−Down Resistance
SW to PGND
kW
kW
LG Pull−Down Resistance
HG to SWBST−SW = 0 V
LOW−SIDE MOSFET DRIVER
Pull−up Resistance, Sourcing Current
Low Side Driver Sourcing Current
Pull−down Resistance, Sinking Current
Low Side Driver Sinking Current
LG Rise Time
0.9
5.56
0.8
12.5
16
3.0
2.0
W
A
W
A
3 nF load
3 nF load
6.0
6.0
30
30
30
ns
ns
ns
LG Fall Time
11
LG Turn−On Propagation
C
= 3 nF
11
LOAD
Delay tpdh
DRVL
LG Pull−Down Resistance
PVCC Quiescent Current
LG to PGND, V = 5 V
1.9
kW
mA
CC
EN = L (Shutdown)
EN = H, no switching
1.0
490
3. Guaranteed by design or characterization data, not in production test.
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NCP81141
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
BOOTSTRAP RECTIFIER SWITCH
On Resistance
EN_L or EN = H with DRVL = H
5.0
9.0
22
W
3. Guaranteed by design or characterization data, not in production test.
tfDRVL
trDRVL
DRVL
tfDRVH
tpdhDRVH trDRVH
DRVH−SW
V
V
TH
TH
tpdhDRVL
SW
1V
Figure 5. Driver Timing Diagram
NOTE: Timing is referenced to the 90% and the 10% points, unless otherwise stated.
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NCP81141
STATE TRUTH TABLE
STATE
VR_RDY Pin
Error AMP Comp Pin
OVP & UVP
Method of Reset
POR
N/A
N/A
N/A
0 < VCC < UVLO
Disabled
EN < threshold
UVLO >threshold
Low
Low
Low
Low
Disabled
Disabled
Start up Delay &
Calibration
EN> threshold
UVLO>threshold
Soft Start
EN > threshold
UVLO >threshold
Low
Operational
Operational
Active /
No latch
Normal Operation
EN > threshold
High
Active /
Latching
N/A
UVLO >threshold
Over Voltage
Over Current
Low
Low
N/A
DAC + 150 mV
Last DAC Code
Disabled
Operational
V
OUT
= 0 V
Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1;
Clamped at 0.9 V
General
The NCP81141 is a single phase PWM controller with integrated driver, designed to meet the Intel VR12.6 specifications
with a serial SVID control interface. It is designed to work in notebook and desktop applications.
The NCP81141 has one internal Driver: DRV1. Internally, there is a single PWM signal: PWM1. DRV1 is driven by PWM1.
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NCP81141
Serial VID interface (SVID)
For SVID Interface communication details please contact Intel Inc.
BOOT VOLTAGE PROGRAMMING
The NCP81141 has a Vboot voltage that can be externally programmed. The Boot voltage for the NCP81141 is set using
VBOOT pin on power up. A 10uA current is sourced from the VBoot pin and the resulting voltage is measured. This is
compared with the thresholds in table below. This value is programmed on power up and cannot be changed after the initial
power up sequence is complete.
BOOT VOLTAGE TABLE
R
Vboot
0 V
30.1k
49.9k
69.8k
90.9k
1.65 V
1.70 V
1.75 V
REMOTE SENSE AMPLIFIER
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to
ǒ
Ǔ
ǒ
Ǔ
ǒ
Ǔ
VDIFOUT + VVSP * VVSN ) 1.3 V * VDAC ) VDROOP * VCSREF
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
REMOTE SENSE AMPLIFIER
The differential current-sense circuit diagram is shown in figure below. An internally-used signal Vcs, representing the
inductor current level, is the voltage difference between CSREF and CSCOMP. The output side of the inductor is used to create
a low impedance virtual ground. The current-sense amplifier actively filters and gains up the voltage applied across the inductor
to recover the voltage drop across the inductor’s DC resistance(DCR). RCS_NTC is placed close to the inductor and
compensate for the change in the DCR with temperature.
The DC gain in the current sending loop is
(
)
VCSREF * VSCOMP
VCS
VDCR
RCS
RCS3
GCS +
+
+
(
)
Iout DCR
(
(
)
)
RCS1 RCS_NTC
RCS1 ) RCS_NTC
RCS + RCS2 )
Figure 6. Differential Current−Sense Circuit diagram
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NCP81141
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high bandwidth transient performance. A standard type 3 compensation
circuit is normally used to compensate the system.
Current Sense Amplifier
The output current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and
CSREF. The output side of the inductor is used to create a low impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductor to recover the voltage drop across the inductor series resistance (DCR). Rth
is placed near the inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function
of the Rth NTC resistor and compensate for the change in the DCR with temperature.
Figure 7. Current Sense Amplifier
The DC gain equation for the current sensing:
Rcs1*Rth
Rcs2 ) Rcs1)Rth
ǒ * DCRǓ
* IoutTotal
VCSCOMP−CSREF + −
Rph
Set the gain by adjusting the value of the Rph resistor. The DC gain should be set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp.
This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain
of the amplifier should be set to provide ~100 mV across the current limit programming resistor at full load. The values of Rcs1
and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The
NTC should be placed close to the inductor.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
DCR@25° C
Fz +
2 * PI * LPhase
PROGRAMMING CURRENT LIMIT
The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors
the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the
current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current
limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on
the CSCOMP−CSREF voltage as shown below. Note the loadline is set at 50% of cscomp/csref differential.
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NCP81141
Rcs1*Rth
Rcs)
Rcs1)Rth
ǒ
Ǔ
2 *
* IoutLIMIT * DCR
ǒ
Ǔ
Rph
ǒ2 * VCSCOMP−CSREF@ILIMITǓ
RLIMIT
+
or RLIMIT +
10m
10m
PROGRAMMING IOUT
The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates
a 2 V signal on IOUT. A pull−up resistor from 5 V V can be used to offset the IOUT signal positive if needed.
CC
2.0 V * RLIMIT
RIOUT
+
Rcs1*Rth
Rcs2)
Rcs1)Rth
ǒ
* DCRǓ* 2
10 *
* IoutICC_MAX
ǒ
Ǔ
Rph
PROGRAMMING ICC_MAX
A resistor to Ground is monitored on startup and this sets the ICC_MAX value. 10 mA is sourced from these pins to generate
a voltage on the program resistor. The resistor value should be no less than 10k.
R * 10 mA * 64 A
ICC_MAX +
2 V
PROGRAMMING TSENSE
A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a
voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter.
A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification
table for the thermal sensing voltage thresholds and source current.
TSENSE
Rcomp1
0.0
Cfilter
0.1uF
Rcomp2
8.2K
t’RNTC
100k
AGND
AGND
Figure 8. TSENSE Circuit
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15
NCP81141
PRECISION OSCILLATOR
Switching frequency is programmed by a resistor Rosc to ground at the Rosc pin. The typical frequency range is from
500 kHz to 1.2 MHz. The FREQ pin provides approximately 2 V out and the source current is mirrored into the internal ramp
generator. The switching frequency can be found in figure below with a given Rosc. The frequency shown in the figure is under
condition of 10 A output current at VID = 1.8 V. The frequency has a variation over VID voltage and loading current, which
maintains similar output ripple voltage over different operation condition.
Figure 9. Operating Frequency vs. ROSC
The oscillator generates a triangular ramp that is 0.5 ~ 2.5 V in amplitude depending on the VRMP pin voltage to provide
input voltage feed forward compensation.
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16
NCP81141
Programming the Ramp Feed-Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed-forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 3.2 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when
the controller is disabled.
The PWM ramp time is changed according to the following
VRAMPpk + pkpp + 0.1 VVRMP
Figure 10. RPM Mode
Figure 11. Ramp Feed Forward & ROSC setup
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17
NCP81141
Programming DAC Feed−Forward Filter
The DAC feed−forward implementation is realized by having a filter on the VSN pin. Programming Rvsn sets the gain of
the DAC feed−forward and Cvsn provides the time constant to cancel the time constant of the system per the following
equations. Cout is the total output capacitance and Rout is the output impedance of the system.
Rvsn + Cout * Rout * 453.6 106
Rout * Cout
Cvsn +
Rvsn
Figure 12. DAC Feed−Forward Filter
Programming DROOP
The signals CSCOMP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop
to the output voltage.
ǒ
Ǔ
Droop + DCR * RCSńRph
Figure 13. Droop
Phase COMPARITOR
The noninverting input of the comparator for phase one is connected to the output of the error amplifier (COMP) and the
phase current (I *DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a
L
1.3 V offset. The operating input voltage range of the comparator is from 0 V to 3.0 V and the output of the comparator generates
the PWM signal which is applied to the input of the internal driver.
During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty
cycle is still calculated by approximately Vout/Vin.
Protection Features
UNDERVOLTAGE LOCKOUT
There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81141
monitors the VCC Shunt supply. The gate driver monitors both the gate driver V and the BST voltage.
CC
SOFT START
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table.
OVER CURRENT LATCH−OFF PROTECTION
The NCP81141 compares a programmable current−limit set point to the voltage from the output of the current−summing
amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external
resistor connected between ILIM and CSCOMP is then compared to the internal current limit current I . If the current
CL
generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (ICL), an internal
latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150%
load current) after which the outputs will remain disabled until the V voltage or EN is toggled.
CC
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18
NCP81141
The voltage swing seen on CSCOMP cannot go below ground. This limits the voltage drop across the DCR. The over−current
limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equation:
ǒ
Ǔ * 2
ILIM * DCR * RCSńRPH
RILIM
+
ICL
Where ICL = 10 mA.
Figure 14. Current Limit
UNDER VOLTAGE MONITOR
The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300 mV
below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.
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19
NCP81141
OVER VOLTAGE PROTECTION
The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output
voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the DAC will be ramped down slowly. At the
same time, the high side gate driver is turned off and the low side gate driver is turned on until the voltage falls to 100 mV. The
part will stay in this mode until the V voltage or EN is toggled. During start up, the OVP threshold is set to 2.9 V. This allows
CC
the controller to start up without false triggering the OVP.
Figure 15. OVP Behavior at Startup
Figure 16. OVP During Normal Operation Mode
During start up, the OVP threshold is set to 2.2 V. This allows the controller to start up without false triggering the OVP.
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20
NCP81141
ORDERING INFORMATION
Device
†
Package
Shipping
NCP81141MNTWG
QFN28
(Pb−Free)
4000 / Tape & Reel
4000 / Tape & Reel
NCP81141MNTXG
QFN28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Figure 17. Alternative Extended Soldering Footprint
ON Semiconductor claims no responsibility for damage or usage
beyond that of specific recommended soldering footprint
Intel is trademark of Intel Corporation in the U.S. and/or other countries.
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21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN28 4x4, 0.4P
CASE 485AR−01
ISSUE A
1
DATE 20 NOV 2009
SCALE 2:1
NOTES:
B
E
A
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
EXPOSED Cu
MOLD CMPD
0.20 REF
0.15
0.25
0.10
C
D
4.00 BSC
D2
E
E2
e
2.50
4.00 BSC
2.50
0.40 BSC
0.30 REF
2.70
DETAIL B
0.10
C
TOP VIEW
ALTERNATE
2.70
CONSTRUCTION
A
DETAIL B
K
L
L1
0.30
−−−
0.50
0.15
A3
0.10
0.08
C
C
GENERIC
MARKING DIAGRAM*
NOTE 4
A1
SEATING
PLANE
SIDE VIEW
D2
C
XXXXXX
XXXXXX
ALYWG
G
0.10
C
A
B
DETAIL A
K
8
XXXXX = Specific Device Code
0.10 C A
B
15
A
L
= Assembly Location
= Wafer Lot
28X L
Y
W
G
= Year
= Work Week
= Pb−Free Package
E2
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
1
PIN 1
INDICATOR
22
e
28X
b
RECOMMENDED
0.07 C A
B
MOUNTING FOOTPRINT
0.05
C
NOTE 3
BOTTOM VIEW
4.30
28X
2.71
0.62
1
2.71
4.30
PACKAGE
OUTLINE
28X
0.26
0.40
PITCH
DIMENSIONS: MILLIMETERS
98AON30349E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: QFN28 4X4, 0.4P
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON30349E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
A
RELEASED FOR PRODUCTION. REQ. BY M. LIN.
15 MAY 2008
20 NOV 2009
CHANGED DIMENSIONS D2, E2, K, L, MOUNTING FOOTPRINT AND MARKING
DIAGRAM INFORMATION. REQ. BY J. LIU.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
©
Semiconductor Components Industries, LLC, 2009
Case Outline Number:
November, 2009 − Rev. 01A
485AR
onsemi,
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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