NCP81147MNTXG [ONSEMI]
Precise Low Voltage Synchronous Buck Controller;
| 型号： | NCP81147MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | Precise Low Voltage Synchronous Buck Controller |
| 文件： | 总12页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81147
Precise Low Voltage
Synchronous Buck
Controller with Power
Saving Mode
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The NCP81147 is a simple single phase solution with differential
phase current sensing, power saving operation, and gate drivers to
provide accurately regulated power.
MARKING
DIAGRAMS
The adaptive non overlap gate drive and power saving operation
circuit provide a low switching loss and high efficiency solution for
server, notebook, and desktop systems. A high performance
operational error amplifier is provided to simplify compensation of the
system. The NCP81147 features also include soft−start sequence,
accurate overvoltage and over current protection, UVLO for VCC and
VCCP, and thermal shutdown.
81147
ALYWG
G
QFN16
CASE 485G
1
81147 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
Features
= Year
• High Performance Operational Error Amplifier
• Internal Soft−Start/Stop
= Work Week
= Pb−Free Package
•
0.5% Internal Voltage Accuracy, 0.8 V voltage reference
(Note: Microdot may be in either location)
• OCP accuracy, Four Re−entry Times Before Latch
• “Lossless” Differential Inductor Current Sensing
• Internal High Precision Current Sensing Amplifier
• Oscillator Frequency Range of 100 kHz − 1000 kHz
• 20 ns Adaptive FET Non−overlap Time of Internal Gate Driver
• 5.0 V to 12 V Operation
PIN CONNECTIONS
16
15
14
13
• Support 1.5 V to 19 V V
in
• V from 0.8 V to 3.3 V (5 V with 12 V
)
CC
1
2
3
4
12
11
10
9
out
VCCP
LG
CSN/VO
FBG
• Chip Enable through OSC pin
• Latched Over Voltage Protection (OVP)
• Internally Fixed OCP Threshold
LX
VSEN
FB
• Guaranteed Startup Into Pre−Charged Loads
• Thermally Compensated Current Monitoring
• Thermal Shutdown Protection
BOOT
5
6
7
8
• Integrated MOSFET Drivers
• Integrated BOOST Diode with internal R = 2.2 W
bst
• Automatic Power Saving Mode to Maximize Efficiency During Light
(Top View)
Load Operation
• Sync Function
• Remote Ground Sensing
• This is a Pb−Free Device*
ORDERING INFORMATION
Device
Package
Shipping
NCP81147MNTXG
QFN16 3000 / Tape & Reel
(Pb−Free)
Applications
• Desktop and Server Systems
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2016 − Rev. 1
NCP81147/D
NCP81147
6
15
2.2 W
BOOT
UG
4
5
Over Current
Detector
CSP
13
12
CDIFF
+
−
Current Sense
Amplifier
CSN/VO
LX
3
OSC
UVP
OVP
−
+
Control Logic,
Protection,
RAMP
Generator and
PWM Logic
COMP
FBG
8
VREF*75%
11
+
UVLO
Control
0.8V
Error Amplifier
−
VCCP
LG
1
2
FB
9
+
−
VREF*125%
VREF*50%
OVP,
UNLATCHED
−
+
10
14
VSEN
1.24V
ROSC/EN
Programmable
OSC
SYNC
GND
7
16
Figure 1. NCP81147 BLOCK DIAGRAM
PIN DESCRIPTIONS
Pin No.
Symbol
VCCP
LG
Description
Power supply for bottom gate MOSFET drivers
Bottom gate MOSFET driver pin
1
2
3
4
5
6
LX
Switch node
BOOT
UG
Supply rail for the floating top gate driver
Top gate MOSFET driver pin
PGOOD
Power Good. It is an open−drain output, set free after SS (with 3x clock delay) as long as the output
voltage monitored through VSEN is within specifications.
7
SYNC
Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to
this pin. Short to GND if not used.
8
COMP
FB
Output of the error amplifier
9
Inverting input to the error amplifier
10
11
12
13
14
15
16
VSEN
FBG
Output Voltage Sense
Remote Ground Sense
CSN/VO
CSP
Inductor differential sense inverting input
Inductor differential sense non−inverting input
Programs the switching frequency; EN: Pull−low to disable the device
Supply rail for the controller internal circuitry
Ground reference
ROSC/EN
VCC
GND
THERMAL PAD
Connects with the silicon substrate for good thermal contact with the PCB. Connect to GND plane.
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2
NCP81147
VCC
VCCP
VIN
PGOOD
SYNC
Q3
1
6
7
1
4
RSEN1
RS1
CSEN1
PGOOD
SYNC
VCCP
BOOT
RS2
RNTC1
13
12
CBOOT1
CSP
NCP81147
CSN/VO
LOUT1
5
3
2
VOUT
UG
LX
11
9
FBG
FB
RFB2
CFB2
Q4
1
8
COMP
COUT1
+
RF1
CF1
CH1
LG
RFB3
RVFB1
ENABLE
JP3
2
1
ETCH
R2
R1
Figure 2. Typical Application Circuit
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
VCC, VCCP
BOOT
V
V
Unit
V
MAX
MIN
Controller Power Supply Voltages to GND
Boost Supply Voltage Input
15
−0.3
−0.3
35V wrt/GND
40 V <100 ns
wrt/GND
V
15 wrt/LX
High−Side Driver Output
(Top Gate)
UG
35
−0.3 wrt/LX
−5 V < 200 ns
V
40 V ≤ 50 ns
wrt/GND
15 wrt/LX
Switching Node
(Bootstrap Supply Return)
LX
LG
35
−5
V
V
40 < 100 ns
−10 V < 200 ns
Low−Side Driver Output
(Bottom Gate)
15
−0.3
−5 V < 200 ns
All Other Pins
PGOOD
6
7
−0.3, −1 V < 1 ms
−0.3, −1 V < 1 ms
−0.3, −1 V < 1 ms
−0.3, −1 V < 1 ms
V
V
V
V
PGOOD
SYNC
SYNC
7
Current Sense Amplifier
CSP, CSN/VO with
10
V
CC
= 12 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.
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3
NCP81147
THERMAL INFORMATION
Rating
Symbol
Typ
60
Unit
°C/W
°C/W
°C
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Operating Junction Temperature Range
Operating Ambient Temperature Range
Maximum Storage Temperature Range
R
q
JA
JC
J
R
18
q
T
T
−40 to +125
−40 to +85
−55 to +150
1
°C
A
T
STG
°C
Moisture Sensitivity Level
QFN Package
MSL
−
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 85°C; 4.5 V < VCC < 13.2 V; C
= 0.1 mF
A
VCC
Parameter
SUPPLY OPERATING CONDITIONS
VCC Voltage Range
Test Conditions
Min
Typ
Max
Unit
4.5
4.5
13.2
13.2
10
V
VCCP Voltage Range
V
dV/dt on VCC (Note 1)
−10
−10
V/ms
V/ms
dV/dt on VCCP (Note 1)
10
VCC AND BOOT INPUT SUPPLY CURRENT
VCC Operating Current
V
= 5 V, EN = High
= 12 V, EN = High
5.0
mA
uA
CC
V
CC
VCC Supply Current
V
= 5 V, EN = Low
= 12 V, EN = Low
400
CC
CC
V
VCCP INPUT SUPPLY CURRENT
VCCP Operating Current
UG and LG Open
V
= 5 V, EN = High
= 12 V, EN = High
mA
CCP
V
CCP
3.5
5.0
VCCP Supply Current
V
V
= 5 V, EN = Low
= 12 V, EN = Low
200
mA
CCP
CCP
VCC SUPPLY VOLTAGE
VCC UVLO Start Threshold
VCC UVLO Hysteresis
V
Rising
4.50
4.2
V
CC
V
CC
Rising or Falling
300
200
mV
VCCP SUPPLY VOLTAGE
VCCP UVLO Start Threshold
VCCP UVLO Hysteresis
ERROR AMPLIFIER COMP
Open Loop DC Gain (Note 1)
Open Loop Unity Gain Bandwidth (Note 1)
Slew Rate (Note 1)
V
mV
120
18
dB
15
MHz
V/ms
COMP pin to GND with 100 pF load
8.0
VREF
Internal Reference Voltage
Output Voltage Accuracy
0.800
V
V
out
to FBG excluding external resistor divider
tolerance
−1.5
1.5
%
CURRENT SENSE AMPLIFIERS
Common Mode Input Voltage Range
(Note 1, GNG, output within 10mV)
V
V
≤ 7.5 V
−0.3
−0.3
3.5
5.5
V
V
CC
Common Mode Input Voltage Range
(Note 1, GNG, output within 10 mV)
> 7.5 V
CC
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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4
NCP81147
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 85°C; 4.5 V < VCC < 13.2 V; C
= 0.1 mF
A
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)
Switching Frequency Accuracy
R
open
−15
15
%
OSC
OSC Gain (Note 1)
10
kHz /
mA
Disable threshold
R
/EN pin, V
0.75
V
OSC
dis_th
MODULATORS (PWM Comparators)
Minimum Pulse Width
F
F
= 200 kHz, OSC open
= 200 kHz, OSC open
90
ns
ns
V
sw
Minimum Turn Off Time (LG on)
Magnitude of the PWM Ramp
Maximum Duty Cycle
250
350
1.50
450
95
sw
V
IN
= 5 V or 12 V
OSC/EN = OPEN
80
30
%
Minimum Skip mode frequency
In light load, maximum time for LG to turn on
after HG turns off
kHz
SOFT−START
Soft Start Time @ 200 kHz
SOFT−OFF
1024 clock cycles, OSC/EN open
5.12
120
ms
Soft OFF bleeding resistor
OVER CURRENT PROTECTION
First Over Current Threshold
Second Over Current Threshold
SYNC PIN
R
W
dis
CSP−CSN, 4xMasking
17
20
30
23
mV
mV
CSP−CSN, Immediate action
Synchronization Input
VIL, square wave
VIH, square wave
1.0
V
V
Synchronization Input
2.5
PROTECTION AND PGOOD
Output Voltage
Logic Low, Sinking 4 mA
0.4
140
80
60
50
1
V
%
%
%
ms
ms
OVP Threshold
VSEN rising above 1.25 * V
110
70
125
75
ref
UVP Threshold
VSEN falling below 0.75 * V
ref
Unlatched Overvoltage Threshold
Power Good High Delay (Note 1)
Power Good Low Delay (Note 1)
ZERO CURRENT DETECTION (LX Pin)
V
with respect to 0.5 V
40
50
th_disoff
ref
Blanking Time before Zero Current
Detection (Note 1)
Blanking Time after LG is < 1.0 V
40
20
ns
ns
Capture Time for LX Voltage (Note 1)
Time to capture LX voltage once LG is < 1.0 V
(must be within dead time limits)
Negative LX detection voltage
Positive LX detection voltage
V
150
0.2
3.0
300
0.5
450
1.0
3.7
mV
V
bdls
V
bdhs
Time for V adjustment and settling time
300 kHz
ms
th
(Note 1)
Initial Negative Current Detection
Threshold Voltage Set Point (Note 1)
LX−GND, Includes 2 mV Offset Range
1.0
0
mV
mV
V
th
adjustable Range (Note 1)
−16
15
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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5
NCP81147
ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 85°C; 4.5 V < VCC < 13.2 V; C
= 0.1 mF
A
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
HIGH SIDE DRIVER UG
R
R
Output Resistance, Sourcing
Output Resistance, Sinking
Transition Time
V
BOOT
− V = 12 V, C
= 3 nF, V =12 V
2.5
2.0
16
11
5
W
W
H_TG
H_TG
LX
load
CC
V
BOOT
− V = 12V, V =12 V
2.5
LX
CC
Tr
Tf
C
C
= 2 nF, V =12 V
ns
ns
ns
DRVH
DRVH
LOAD
LOAD
CC
Transition Time
= 2 nF, V =12 V
CC
Tpdh
Propagation Delay (Notes 1, 2)
Driving High, C
= 3 nF,
=12 V
15
30
DRVH
LOAD
CCP
V
CC
= 12 V, V
UG Internal Resistor to LX
Unbiased, BOOT − LX = 0
45
kW
LOW SIDE DRIVER LG
R
R
Output Resistance, Sourcing
Output Resistance, Sinking
Transition Time
V
= GND, C
= 3 nF, V =12 V
2.0
1.0
16
11
3.0
1.5
W
W
H_BG
L_BG
LX
load
CC
V
LX
= V , V =12 V
CC CC
Tr
Tf
C
= 3 nF, V =12 V
ns
ns
ns
DRVL
LOAD
LOAD
CC
Transition Time
C
= 3 nF, V =12 V
CC
DRVL
Tpdh
Propagation Delay (Notes 1, 2)
Driving High, C
= 3 nF, V = 12 V,
CCP
10
20
35
DRVL
LOAD
V
CCP
= 12 V
LX Internal Resistor to GND
45
kW
THERMAL SHUTDOWN
T
Thermal Shutdown (Note 1)
150
180
50
°C
°C
sd
T
sdhys
Thermal Shutdown Hysteresis
(Note 1)
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
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6
NCP81147
1V
1V
Figure 3. Gate Timing Diagram
Switching Frequency
Connecting a resistor from ROSC/EN to an external
of an internal ramp signal correspondingly with a fixed
delay time. The external signal has to sit within a 0-40%
frequency window above the local frequency configured by
voltage source V will configure the switching frequency.
pu
Normal range would be 100 kHz to 1 MHz. With no resistor
connected to the pin, the oscillator frequency is 200 kHz.
The switching frequency will follow the relationship:
the R
working properly.
resistor to allow the synchronization function
osc
Power Good
Vpu * 1.240
kHz
The PGOOD pin is an open drain connection with no
internal pullup resistor. An active high output signals the
normal operation of the converter. PGOOD is pulled low
during soft-start cycle, and if there is an overvoltage or
undervoltage fault. If the voltage on the VSEN pin is within
10% of Vref (0.8 V) then the PGOOD pin will not be pulled
low.
FSW + 200 kHz *
@ 10
(eq. 1)
ROSC
mA
When R
= infinity (no resistor connected), F
=
osc
sw
200 kHz; when V = ground, the frequency programmed
pu
will be higher than 200 kHz. Pulling R /EN pin to ground
osc
solidly with a less than 10 kW resistor will result in the part
being disabled.
Overvoltage Protection (OV)
Soft−Start
If the voltage on the VSEN pin exceeds the overvoltage
threshold (1000 mV or 125% Vref), the NCP81147 will latch
an overvoltage fault. During an overvoltage fault event the
UG pin will be pulled low, and the LG pin will stay high until
the voltage on the VSEN pin goes below 400 mV or 50%
Soft−Start will begin if VCC, VCCP are both above their
UVLO thresholds and EN pin is set free. IC initially waits
a fixed delay time and then ramps the reference in 5.12 ms
(1024 clock cycles when R
open) in closed−loop
osc
regulation. After soft−start, PGOOD signal will be released
with 3 clock cycles delay.
V , then a soft-bleeding resistor will be connected from
ref
switch node to ground to continuously discharge the output
voltage softly. To clear the overvoltage fault, toggling VCC
or EN is needed.
Protection active during soft−start:
• Overvoltage Protection always enabled;
• Undervoltage Protection is enabled after reference
voltage ramps up to 80% of the final value. During
soft−start, a UVP fault will initiate a complete soft
restart.
Undervoltage Protection (UV)
If the voltage on the FB pin falls below the undervoltage
threshold after the softstart cycle completes, the NCP81147
will latch an undervoltage fault. During an undervoltage
fault, both the UG and LG pins will be pulled low. Toggling
VCC power or EN will reset the undervoltage protection.
Synchronization Function
Synchronize through the SYNC pin. Synchronization
function allows different converters to share the same input
filter reducing the resulting RMS current and reducing the
need for total caps to sustain the load. Synchronized systems
also exhibit higher EMI noise immunity and better
regulation.
The device synchronizes to the Falling edge of the SYNC
pin external input signal (eg. high side gate signal, switch
node signal, distribution clock signal), and locks the phase
PreOVP Protection
If the NCP81147 is powered on but not enabled, the VSEN
pin will be monitored for preOVP condition. If the VSEN
exceeds the preset threshold, the device will force LG pin
high to protect the load. The PreOVP function will be
disabled when the device is enabled and the normal OV
function will operate instead.
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7
NCP81147
VPU
LG
BUFFER
VSEN
VTH
Figure 4. PreOVP circuit
Vin Detection
During the soft start after the VSEN pin exceeds 80% V ,
UV protection will be enabled; If a UV fault is triggered in
the softstart, it will restart SS after a fixed delay. The UV
protection is to avoid IC to startup without Vin or with
insufficient Vin voltage.
OCP2 will be tripped, the UG and LG will be pulled low and
latched immediately. Toggling VCC power or EN will reset
the Overcurrent protection.
The current sensing R/C network should be selected to
match the inductor time constant as below,
ref
L
(RCS1ńńRCS2) @ C +
DCR
(Notes: the actual RC network time constant may be
slightly higher)
Overcurrent Protection
NCP81147 measures the differential current sensing
signal through CSP and CSN/VO pin. There are two current
protection levels: OCP1 and OCP2. If the differential
voltage across pin CSP and CSN/VO is over 20 mV (but
below 30 mV) for four consecutive cycles, OCP1 will be
tripped. Both UG and LG will be forced to low to turn off the
high side and low side FETs, it is a latched condition; If the
differential voltage across pin CSP and CSN is over 30 mV,
Thus, OCP1 and OCP2 levels can be configured as,
20 mV
DCR
RCS1 ) RCS2
OCP1 +
OCP2 +
@
@
RCS2
30 mV
DCR
RCS1 ) RCS2
RCS2
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8
NCP81147
L
DCR
RS1
RS2
CS
CSP
CSN/VO
Figure 5. Differential Current Sense Network
Light Load Operation
this way, the ripple variation during transition between the
discontinuous and continuous current mode can be
minimized.
In the light load condition, NCP81147 will work in a diode
emulation mode with bottom gate turning off if the inductor
current is below zero. The system therefore works in
discontinuous conduction mode (DCM). The zero current
detection is done by sensing switch node and automatically
adjusted to minimize the low side FET body diode
conduction time (right after LG turns off) in diode emulation
mode.
If the load reduces further, COMP signal will be close or
below the internal ramp bottom triggering minimum on time
operation, the system will start skipping pulses, working in
a reduced frequency range. NCP81147 has an internal
ultrasonic timer to keep the device from working in an audio
frequency and below. This timer initiates after high side gate
off signal and expires after ~30 ms.
Voltage Feedback
The NCP81147 allow the output voltage to be adjusted
from 0.8 V to 5 V via an external resistor divider network
(R1, R2). The controller will regulate the output voltage to
maintain the FB pin voltage to 0.8 V reference voltage. The
relation between the resistor divider network and the output
voltage is as below;
0.8 V
Vout * 0.8 V
R2 + R1 @ ǒ
Ǔ
VOUT
Normally high side gate signal will reset this ultrasonic
timer repeatedly before it expires. In a very light load or load
release, if there is no high side gate pulses until the timer
expires, the low side MOSFET(s) will be forced to turn on
to discharge the output. Through properly compensated
network the comp signal will climb up to generate next burst
of switching pulses and the converter will regulate the
output voltage to its target level. This can last a few cycles
or continuously depending on the system load level.
In light load operation, if synchronization is enabled,
NCP81147 will also check the SYNC pin input signal cycle
by cycle. If the external sync signal is within the
synchronization frequency range, the NCP81147 will
interleave its switching pulses with it after a proper delay. In
R1
R2
VFB
Figure 6. Feedback Voltage
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9
NCP81147
Vin
POR_VCC
UVLO_VCC
VCC
1.24V
0.75V
OSC/EN
LG (Stays Low
until first PWM
pulse except in
case of a Fault)
UG
OVP
(125%V
)
ref
V
= 0.8 V
ref
80% V
rer
OCP/
Normal
shutdown
Vout.
FB
Vth_disoff
(50%V
)
ref
Softstop
UV monitor
SoftStart
Normal
1024cycle
~5ms@200kHzz
Pre-OVP valid
Figure 7. Start Up and Shutdown Timing Diagram
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10
NCP81147
PWR
ON
EN>Vdis_th
No
VCC> POR &
VCCDR> UVLO_VCCDR (16−
pin)
Yes
PreOVP detection
BG on
VSEN>OV Vth
VCC> POR &
VCCDR> U_VLO VCCDR
No
BOOT >UVLO_BOOT
Yes
Fosc detection
Soft Start ,
Normal Operation
OCP, OVP, UVP detection
UV (after Vout reaches UV
threshold in softstart)
OC
OV
4 times
reentry
UVP
OVP
OCP
TG OFF, BG
OFF
PGOOD=0
TG OFF, BG ON
PGOOD=0
After 4 times reentry for
1st threshod
or immediately over 2nd
threshold
No
Vout< Vth_disoff
TG OFF, BG
Yes
OFF
Vo discharge
mode
Yes
OVP
Vcc<UVLO_Vcc, Or
EN<Vdis_th Or
No
Boot<UVLO_Boot
No
Figure 8. State Diagram
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11
NCP81147
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
NOM MAX
A
0.90
0.03
1.00
0.05
2X
A3
0.10
C
EXPOSED Cu
MOLD CMPD
A3
b
D
0.20 REF
0.24
3.00 BSC
1.75
0.18
0.30
1.85
1.85
2X
0.10
C
TOP VIEW
D2 1.65
E
3.00 BSC
1.75
0.50 BSC
0.18 TYP
0.40
DETAIL B
A1
(A3)
E2 1.65
e
K
L
0.05
0.05
C
DETAIL B
ALTERNATE
A
C
0.30
0.50
0.15
CONSTRUCTIONS
L1 0.00
0.08
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
0.10
C
A
B
16X
0.58
DETAIL A
D2
PACKAGE
OUTLINE
16X
L
8
4
1
9
1
2X
1.84
2X
3.30
E2
16X
K
16X
0.30
16
16X b
e
0.10
0.05
C
C
A B
0.50
e/2
BOTTOM VIEW
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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