NCP81149MNTXG [ONSEMI]
单相稳压器，带 SVID 接口，适用于计算应用;
| 型号： | NCP81149MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 单相稳压器，带 SVID 接口，适用于计算应用 稳压器 |
| 文件： | 总18页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81149
Single-Phase Voltage
Regulator with SVID
Interface for Computing
Applications
www.onsemi.com
MARKING
High Switching Frequency, High
Efficiency, Integrated Power MOSFETs
DIAGRAM
The NCP81149, a single−phase synchronous buck regulator,
integrates power MOSFETs to provide a high−efficiency and
compact−footprint power management solution for new generation
computing CPUs. The device is able to deliver up to 14 A TDC output
current on an adjustable output with SVID interface. Operating in high
switching frequency up to 1.2 MHz allows employing small size
inductors and capacitors while maintaining high efficiency due to
integrated solution with high performance power MOSFETs.
Current−mode RPM control with feedforward from both input power
supply and output voltage ensures stable operation over wide
operation condition. The NCP81149 is in a QFN48 6 x 6 mm package.
1
NCP81149
AWLYYWWG
1
48
QFN48
CASE 485CJ
NCP81149 = Specific Device Code
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
Features
• Meets Intel® VR12.6 and VR12.6+ Specifications
• Support 11.5 W and 15 W ULT Platforms
• 4.5 V to 25 V Input Voltage Range
• Adjustable Output Voltage with SVID Interface
• Integrated Gate Driver and Power MOSFETs
• 0 V, 1.65 V, 1.7 V, 1.75 V Boot Up Voltage
• 500 kHz ~ 1.2 MHz Switching Frequency
• Current−Mode RPM Control
ORDERING INFORMATION
†
Device
NCP81149MNTXG
Package
Shipping
QFN48
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Adaptive Voltage Positioning (AVP)
• Programmable DVID Feed−Forward to Support Fast DVID
• Feedforward Operation for Input Supply Voltage and Output Voltage
• Output Over−Voltage and Under−Voltage Protections
• External Current Limitation Programming with Inductor Current
Sense
• QFN48, 6x6 mm, 0.4 mm Pitch Package
• This is a Pb−Free Device
Typical Applications
• Ultrabook Applications
• Notebook Applications
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
September, 2015 − Rev. 3
NCP81149/D
NCP81149
48
47
46
45
44
43
42
41
40
39
38
37
1
2
VRHOT#
IOUT 36
IMAX
SDIO
ALERT#
SCLK
GND
VRRDY
VIN
35
GND
49
3
TSENSE 34
VCCP 33
GND 32
4
5
6
VBOOT
GL
31
30
7
BST
8
SW 29
SW 28
SW 27
SW 26
SW 25
VIN
50
SW
51
9
GH
SW
10
11
VIN
12 VIN
13
14
15
16
17
18
19
20
21
22
23
24
Figure 1. Pin Configuration
(Top View)
VIN
BST
GH
VIN
PGND
VCCP
SW
VOUT
+5V
SW
GL
ILIM
VCC
GND
CSCOMP
EN
VRHOT#
SDIO
CSSUM
NCP81149
CSREF
ALERT#
SCLK
VBOOT
VRRDY
TSENSE
COMP
FB
DIFFOUT
IMAX
FREQ
IOUT
VSP
VSN
Figure 2. Typical Application Circuit
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2
NCP81149
VCC
P
BST
GH
VIN
SW
VIN
VCC
EN
UVLO
Gate Drive
VCCP
GND
PGND
GL
DAC
VSP−VSN
OCP
Control Logic
&
VRRD
Y
Protections
&
PWM
VR Ready
IMON
OCP
IOUT
ILIM
Current Measurement
and Limit
VRH
OT#
V
CS
CSREF
PWM
Control
CSR
EF
Thermal
Management
TSENSE
TSEN
SE
CSS
UM
FRE
Q
Frequency
&
VIN
DAC
V
DROOP
VBOOT
Detection
CSCOMP
CSC
OMP
VBO
OT
VSP−VSN
COMP
COM
P
VBOOT
IOUT
MUX
ADC
IMAX
Vref
IMAX
SDIO
FB
TSENSE
1.3V
DIFF
OUT
V
DROOP
VSP
VSN
SCL
K
Differential
Amplifier
SVID Interface
Registers
Vref
DAC
ALE
RT#
DAC
DVID
FeedForward
DAC
Figure 3. Functional Block Diagram
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3
NCP81149
PIN DESCRIPTION
Pin
1
Name
VRHOT#
SDIO
Type
Description
Logic Output
Logic Bidirectional
Logic Output
Logic Input
VR HOT. Logic low output represents over temperature.
Serial Data IO Port. Data port of SVID interface.
2
3
ALERT#
SCLK
ALERT. Open−drain output. Provides a logic low valid alert signal of SVID interface.
Serial Clock. Clock input of SVID interface.
4
5, 32,
49
GND
Analog Ground
Analog Ground. Ground of internal control circuits. Must be connected to the system
ground.
6
VRRDY
VIN
Logic Output
Power Input
Voltage Regulator Ready. Open−drain output. Provides a logic high valid power good
output signal, indicating the regulator’s output is in regulation window.
7,
11−17,
50
Power Supply Input. These pins are the power supply input pins of the device, which are
connected to drain of internal high−side power MOSFET. 22 mF or more ceramic
capacitors must bypass this input to power ground. The capacitors should be placed as
close as possible to these pins.
8
BST
Power
Bidirectional
Bootstrap. Provides bootstrap voltage for the high−side gate driver. A 0.1 mF ~ 1 mF
ceramic capacitor is required from this pin to SW (pin 10). A 1 W ~ 2 W resistor may be
employed in series with the BST cap to reduce switching noise and ringing when needed.
9
GH
SW
SW
Analog Output
Power Return
Power Output
Gate of High−Side MOSFET. Directly connected with the gate of the high−side power
MOSFET.
10
Switching Node. Provides a return path for integrated high−side gate driver. It is internally
connected to source of high−side MOSFET.
18,
25−29,
51
Switch Node. Pins to be connected to an external inductor. These pins are interconnection
between internal high−side MOSFET and low−side MOSFET.
19−24
PGND
GL
Power Ground
Analog Output
Power Ground. These pins are the power supply ground pins of the device, which are
connected to source of internal low−side power MOSFET. Must be connected to the
system ground.
30
Gate of Low−Side MOSFET. Directly connected with the gate of the low−side power
MOSFET.
31
33
VBOOT
VCCP
Analog Input
Boot−Up Voltage. A resistor from this pin to ground programs boot−up voltage.
Analog Power
Voltage Supply of Gate Driver. Power supply input pin of internal gate driver. A 4.7 mF or
larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as
close as possible to this pin.
34
35
36
TSENSE
IMAX
Analog
Temperature Sense. An external temperature sense network is connected to this pin.
Current Maximum. A resistor from this pin to ground programs IMAX.
Analog Input
Analog Output
IOUT
OUT Current Monitor. Provides output signal representing output current by connecting a
resistor from this pin to ground. Shorting this pin to ground disables IMON function.
37
ILIM
Analog Output
Limit of Current. A resistor from this pin to CSCOMP programs over−current threshold with
inductor current sense.
38
39
40
41
42
43
44
45
CSCOMP
CSSUM
CSREF
FREQ
Analog Output
Analog Input
Analog Input
Analog Input
Analog
Current Sense COMP. Output pin of current sense amplifier.
Current Sense SUM. Inverting input of current sense amplifier.
Current Sense Reference. Non−Inverting input of current sense amplifier.
Frequency. A resistor from this pin to ground programs switching frequency.
Compensation. Output pin of error amplifier.
COMP
FB
Analog Input
Analog Output
Analog Input
Feedback. Inverting input to error amplifier.
DIFFOUT
VSN
Differential Amplifier Output. Output pin of differential voltage sense amplifier.
Voltage Sense Negative Input. Inverting input of differential voltage sense amplifier. It is
also used for DVID feed forward function with an external resistor.
46
VSP
Analog Input
Voltage Sense Positive Input. Non−inverting input of differential voltage sense amplifier.
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4
NCP81149
PIN DESCRIPTION
Pin
Name
Type
Description
47
VCC
Analog Power
Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger
ceramic capacitor bypasses this input to ground. This capacitor should be placed as close
as possible to this pin.
48
EN
Logic Input
Enable. Logic high enables the device and logic low makes the device in standby mode.
MAXIMUM RATINGS
Value
Min
Max
30
Rating
Symbol
Unit
Power Supply Voltage to PGND
Switch Node to PGND
V
V
VIN
SW
V
30
V
V
V
Analog Supply Voltage to GND
BST to PGND
V
V
−0.3
−0.3
6.5
CC, CCP
BST_PGND
33
38 (<50 ns)
BST to SW
GH to SW
BST_SW
GH
−0.3
6.5
V
V
−0.3
−2 (<200 ns)
BST + 0.3
GL to GND
GL
−0.3
−2 (<200 ns)
V
CCP
+ 0.3
V
VSN to GND
IOUT
VSN
IOUT
PGND
−0.3
−0.3
−0.3
−0.3
0.3
V
V
2.5
0.3
PGND to GND
Other Pins
V
V
+ 0.3
V
CC
Latch up Current: (Note 1)
All pins, except digital pins
Digital pins
I
LU
mA
−100
−10
100
10
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
T
T
−40
−40
−55
150
100
150
°C
°C
J
A
T
STG
°C
Thermal Resistance Junction to Board (Note 2)
Thermal Resistance Junction to Ambient (Note 2)
R
R
8.2
°C/W
°C/W
W
θ
θ
JB
JA
D
21.8
4.59
3
Power Dissipation at T = 25°C (Note 3)
P
A
Moisture Sensitivity Level (Note 4)
MSL
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 class II.
2. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and
2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors etc.)
3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on T
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
= 125°C and R
= 21.8°C/W.
θ
JMAX
JA
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NCP81149
ELECTRICAL CHARACTERISTICS
(V = 8.4 V, V = V
= 5 V, V = 1.8 V, typical values are referenced to T = 25°C, Min and Max values are referenced to T from
OUT J J
IN
CC
CCP
−40°C to 100°C. unless otherwise noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Supply Voltage V Range
(Note 5)
(Note 5)
(Note 5)
V
8.4
5
V
V
V
IN
IN
Supply Voltage V Range
V
CC
4.75
4.75
5.25
5.25
CC
Supply Voltage V
Range
V
CCP
5
CCP
SUPPLY VOLTAGE MONITOR
V
UVLO
Falling Threshold
Hysteresis
V
3.25
650
3.5
−
V
mV
V
3.0
IN
INUV−
INHYS
CCUV−
CCUV+
CCHYS
V
V
CC
UVLO
Falling Threshold
Rising Threshold
Hysteresis
V
V
3.8
−
4.08
4.34
260
−
4.5
−
V
V
−
mV
SUPPLY CURRENT
Quiescent Supply Current
V
IN
EN high, no load, PS0,1,2 Modes
EN high, no load, PS3 Mode
EN high, PS4 Mode (Note 6)
I
Q
−
−
−
1.5
1.5
−
3
3
1
mA
mA
mA
(Power MOSFETs)
V
V
Shutdown Current
EN low (Note 6)
I
−
−
1
mA
IN
SD
Quiescent Supply Current
EN high, no load, PS0,1,2 Modes
EN high, no load, PS3 Mode
EN high, PS4 Mode (Note 6)
I
−
−
−
8.0
7.5
170
12
12
194
mA
mA
mA
CC
QCC
(Controller)
V
V
Shutdown Current
EN low (Note 6)
I
−
−
100
mA
CC
SDCC
Quiescent Supply Current
EN high, no load, PS0,1,2 Modes
EN high, no load, PS3 Mode
EN high, PS4 Mode (Note 6)
I
−
−
−
0.7
0.7
−
1.25
1.25
2
mA
mA
mA
CCP
QCCP
(Gate Driver)
V
Shutdown Current
EN low
(Note 5)
Default
I
−
−
2
mA
CCP
SDCCP
OUTPUT VOLTAGE
Output Voltage Range
DVID
V
OUT
0
−
2.3
V
Fast Slew Rate
Soft Start Slew Rate
Slow Slew Rate
FSR
48
mV/ms
mV/ms
mV/ms
SSSR
SSR
FSR/4
FSR/2
FSR/4
(default)
FSR/8
FSR/16
DIFFERENTIAL VOLTAGE−SENSE AMPLIFIER
DC Gain
VSP−VSN = 0.5 V to 2.3 V
GAIN_DVA
BW_DVA
1.0
10
V/V
CL = 20 pF to GND, RL = 10 kW to
GND (Note 5)
−3dB Gain Bandwidth
MHz
VSP Input Voltage Range
VSN Input Voltage Range
(Note 5)
(Note 5)
VSP
VSN
−0.3
−0.3
−
−
3.0
0.3
V
V
I
I
−15
−100
15
100
mA
nA
VSP
VSN
Input Bias Current
VSP,CSREF = 1.3 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design, not tested in production.
6. T = 25°C.
J
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6
NCP81149
ELECTRICAL CHARACTERISTICS (continued)
(V = 8.4 V, V = V = 5 V, V = 1.8 V, typical values are referenced to T = 25°C, Min and Max values are referenced to T from
IN
CC
CCP
OUT
J
J
−40°C to 100°C. unless otherwise noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
DIFFERENTIAL CURRENT−SENSE AMPLIFIER
DC Gain
(Note 5)
GAIN_DCA
BW_DCA
80
10
−
dB
MHz
mV
CL = 20 pF to GND, RL = 10 kW to
GND (Note 5)
−3dB Gain Bandwidth
Input Offset Voltage
Input Bias Current
V
−300
300
OS_CS
I
−7.5
−10
7.5
10
nA
mA
CSSUM
CSSUM = CSREF = 1 V
I
CSREF
ERROR AMPLIFIER
DC Gain
CL = 20 pF to GND, RL = 10 kW to
GND (Note 5)
GAIN_EA
BW_EA
SR_EA
80
20
25
dB
Unity Gain Bandwidth
Slew Rate
CL = 20 pF to GND, RL = 10 kW to
GND (Note 5)
MHz
V/ms
DV = 100 mV, G = −10 V/V,
in
DV = 1.5 V – 2.5 V,
out
CL = 20 pF to GND, RL = 10 kW to
GND (Note 5)
Output Voltage Swing
Isource_EA = 2 mA
Isink_EA = 2 mA
Vmax_EA
Vmin_EA
3.5
−
−
−
−
1
V
V
FB Voltage
V
1.3
V
FB
FB
Input Bias Current
V
FB
= 1.3 V
I
−1.5
1.5
mA
SWITCHING FREQUENCY
Normal Operation Frequency
(Note 5)
FSW
500
1200
2.05
kHz
V
(Programmed by a resistor at FREQ
pin)
FREQ Output Voltage
CONTROL LOGIC
VFREQ
1.95
2.0
ENABLE Input High Voltage
ENABLE Input Low Voltage
ENABLE Input Hysteresis
ENABLE Input Bias Current
VR_HOT#
VEN_H
VEN_L
0.8
−
−
−
−
0.3
−
V
V
VEN_HYS
IEN_BIAS
−
300
mV
mA
−
1.0
Output Low Voltage
I_VRHOT# = −4 mA
−
−
−
0.3
1.0
V
High Impedance State, VRHOT# =
3.3 V
Output Leakage Current
−1.0
mA
TSENSE
Alert# Assert Threshold
Alert# De−assert Threshold
VR_HOT# Assert Threshold
VR_HOT# De−assert Threshold
TSENSE Bias Current
491
513
472
494
120
mV
mV
mV
mV
mA
VTSENSE = 0.4 V
112
128
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design, not tested in production.
6. T = 25°C.
J
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7
NCP81149
ELECTRICAL CHARACTERISTICS (continued)
(V = 8.4 V, V = V = 5 V, V = 1.8 V, typical values are referenced to T = 25°C, Min and Max values are referenced to T from
IN
CC
CCP
OUT
J
J
−40°C to 100°C. unless otherwise noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
10
Max
Unit
mA
VBOOT
Sensing Current
VVBOOT = GND
IMAX
Sensing Current
VIMAX = GND
10
mA
ADC
Voltage Range
0
2.0
1
V
%
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time
Round Robin
−1
8−bit
1
LSB
%
1
30
90
ms
ms
VR_READY (VRRDY Output)
Rise Time
External 1 kW pull−up to 3.3 V,
CTOT = 45 pF, DVo = 10% to 90%
100
10
ns
ns
Fall Time
External 1 kW pull−up to 3.3 V,
CTOT = 45 pF, DVo = 90% to 10%
Output Voltage at Power−Up
VR_READY Delay (Rising)
VR_READY Delay (Falling)
VRRDY Pin Low Voltage
Pulled up to 5 V via 2 kW
DAC = Target to VR_READY
From OCP or OVP
−
−
50
5
1.0
V
ms
ms
Voltage at VRRDY pin with 4mA sink
current
VPG_L
PG_LK
−
−
−
0.3
V
VRRDY Pin Leakage Current
VRRDY = 5 V
−1.0
1.0
mA
OVER VOLTAGE PROTECTION
Absolute Over Voltage Threshold
During Soft−Start
2.8
2.9
3.0
V
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP rising
350
400
50
425
mV
ns
VSP rising to GH low
UNDER VOLTAGE PROTECTION
Under Voltage Threshold Below DAC
Under−voltage Delay
VSP falling
250
300
5
350
mV
ms
OVER CURRENT PROTECTION
ILIM Threshold Current
(OCP shutdown after 50 ms delay)
I
8.5
10.0
15.0
12.0
18.0
mA
mA
LIMTH_SLOW
ILIM Threshold Current
I
12.0
LIMTH_FAST
(immediate OCP shutdown)
IOUT OUTPUT
Current Gain
(IOUTCURRENT) / (ILIMCURRENT);
RILIM = 20 kW; RIOUT = 5.0 kW;
DAC = 0.8 V, 1.25 V, 1.52 V
9.5
10
10.5
5.5
A/A
Input Referred Offset Voltage
Output Source Current
ILIM − CSREF
−5.5
−
mV
ILIM sink current = 80 mA
800
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design, not tested in production.
6. T = 25°C.
J
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8
NCP81149
ELECTRICAL CHARACTERISTICS (continued)
(V = 8.4 V, V = V = 5 V, V = 1.8 V, typical values are referenced to T = 25°C, Min and Max values are referenced to T from
IN
CC
CCP
OUT
J
J
−40°C to 100°C. unless otherwise noted.)
Characteristics
Test Conditions
Symbol
Min
−
Typ
8.0
4.0
Max
−
Unit
mW
mW
HIGH−SIDE MOSFET
Drain−to−Source ON Resistance
LOW−SIDE MOSFET
V
V
= 4.5 V, I = 10 A
R
ON_H
GS
D
Drain−to−Source ON Resistance
HIGH−SIDE GATE DRIVE
Pull−High Drive ON Resistance
Pull−Low Drive ON Resistance
GH Propagation Delay Time
LOW−SIDE GATE DRIVE
Pull−High Drive ON Resistance
Pull−Low Drive ON Resistance
GL Propagation Delay Time
SW to PGND RESISTANCE
SW to PGND Pull−Down Resistance
BOOTSTRAP RECTIFIER SWITCH
On Resistance
= 4.5 V, I = 10 A
R
−
−
GS
D
ON_L
V
V
– V
– V
= 5 V
= 5 V
R
DRV_HH
−
−
1.2
0.8
15
2.9
2.2
W
W
BST
SW
R
BST
SW
DRV_HL
From GL falling to GH rising
T
GH_d
ns
V
V
– V
– V
= 5 V
= 5 V
R
DRV_LH
−
−
0.9
0.4
10
3.0
W
W
CCP
PGND
R
1.25
CCP
PGND
DRV_LL
From GH falling to GL rising
T
GL_d
ns
(Note 5)
R
−
5
1.88
13
−
kW
SW
EN = L or EN = H and DRVL = H
R
22
W
on_BST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design, not tested in production.
6. T = 25°C.
J
TGL_f
TGL_r
GL
TGH_f
TGH_d
TGH_r
GH to SW
VTH
VTH
TGL_d
SW
1.0V
NOTE: Timing is referenced to the 90% and 10% points, unless otherwise noted.
Figure 4. Timing Diagram of Gate Drivers
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NCP81149
Table 1. STATE TRUTH TABLE
STATE
OVP
Error AMP Comp
Pin
& UVP
VR_RDY Pin
Method of Reset
POR
N/A
N/A
N/A
0 < VCC < UVLO
Disabled
EN < threshold
UVLO > threshold
Low
Low
Low
High
Low
Disabled
Start up Delay & Calibration
EN > threshold
Low
Disabled
UVLO > threshold
Soft Start
EN > threshold
UVLO > threshold
Operational
Operational
Active /
No latch
Normal Operation
EN > threshold
Active / Latching
N/A
UVLO > threshold
Over Voltage
Over Current
Low
Low
N/A
DAC + 400 mV
Last DAC Code
Disabled
Operational
V
OUT
= 0 V
Low: if
Reg34h:bit0=0;
High:if
Clamped at 0.9 V
Reg34h:bit0=1
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10
NCP81149
DETAILED DESCRIPTION
General
Serial VID interface (SVID)
The NCP81149, a single−phase synchronous buck
For SVID Interface communication details please contact
Intel Inc.
regulator, integrates power MOSFETs to provide a
high−efficiency and compact−footprint power management
solution for new generation computing CPUs. The device is
able to deliver up to 14 A TDC output current on an
adjustable output with SVID interface. Operating in high
switching frequency up to 1.2 MHz allows employing small
size inductors and capacitors while maintaining high
efficiency due to integrated solution with high performance
power MOSFETs. Current−mode RPM control with
feedforward from both input power supply and output
voltage ensures stable operation over wide operation
condition.
Boot Voltage
The NCP81149 has a Vboot voltage can be externally
programmed by a resistor connected to the VBOOT pin. A
10 mA current is sourced from the VBOOT pin and the
resulting voltage is measured. Table 2 shows the boot
voltage configuration. This value is set on power up and
cannot be changed after the initial power up sequence is
complete.
Table 2. BOOT VOLTAGE CONFIGURATION
Resistance at Vboot Pin
Boot Voltage
0 V
30.1k
49.9k
69.8k
90.9k
1.65 V
1.70 V
1.75 V
Current−Mode RPM Operation
Switching Frequency
The NCP81149 operates with the current−mode
Ramp−Pulse−Modulation (RPM) scheme in PS0/1/2/3
operation modes. In forced CCM mode, the inductor current
is always continuous and the device operates in quasi−fixed
switching frequency, which has a typical value programmed
by users through a resistor at pin FREQ. In auto CCM/DCM
mode, the inductor current is continuous and the device
operates in quasi−fixed switching frequency in medium and
heavy load range, while the inductor current becomes
discontinuous and the device automatically operates in PFM
mode with an adaptive fixed on time and variable switching
frequency in light load range.
Switching frequency is programmed by a resistor RFREQ
to ground at the FREQ pin. The typical frequency range is
from 500 kHz to 1.2 MHz. The FREQ pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp generator. The switching frequency
can be found in Figure 5 with a given RFREQ. The
frequency shown in Figure 5 is under condition of 10 A
output current at VID = 1.7 V. The frequency has a variation
over VID voltage and loading current, which maintains
similar output ripple voltage over different operation
condition. Figure 6 shows frequency variations over the
VID voltage range.
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11
NCP81149
Figure 5. Switching Frequency vs. RFREQ
Figure 6. Switching Frequency vs. VID Voltage
Remote Voltage Sense
remote sense amplifier is a sum of the error voltage (between
the output VSP−VSN and the DAC), a load−line voltage
VDROOP, and a 1.3 V DC bias.
A high performance differential amplifier is provided to
accurately sense the output voltage of the regulator. The
VSP and VSN inputs should be connected to the regulator’s
output voltage sense points. The output (DIFOUT) of the
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12
NCP81149
(eq. 1)
+ 0.5 @ ǒV
CSCOMPǓ
(eq. 2)
V
+ 0.5 @ V
* V
CSREF
DROOP
CS
+ ǒV
VSNǓ) ǒ1.3 V * V Ǔ) V
V
* V
DIFOUT
VSP
DAC DROOP
The DIFOUT signal then goes through a compensation
network and into the inverting input (FB pin) of an error
amplifier. The non−inverting input of the error amplifier is
connected to the same 1.3 V used for the differential sense
amplifier output bias.
The VDROOP voltage is zero for non DC load line
applications. In applications with a DC load line, the
VDROOP voltage is a half of the voltage difference between
the CSCOMP pin and the CSREF pin.
ICCMAX
35
36
37
ICCMAX
&
IOUT
&
Vcs
VDROOP
IOUT
ILIM
0.5
ILIM
SW
L
DCR
IOUT
CSCOMP
VOUT
38
Rcs3
CSSUM
CSREF
39
40
Current
Sense
Figure 7. Differential Current−Sense Circuit Diagram
Differential Current Sense
thus usually they should not need to be changed. The gain
Gcs can be adjusted by the value change of the Rcs3 resistor.
The internal Vcs voltage should be set to the output voltage
droop in applications with a DC load line requirement. In no
droop applications, the gain Gcs should be set to provide
about 100mV across the current limit programming resistor
at full load.
In order to recover the inductor DCR voltage drop current
signal, the pole frequency in the CSCOMP filter should be
set equal to the zero from the output inductor, that means
The differential current−sense circuit diagram is shown in
Figure 7. An internally−used voltage signal Vcs,
representing the inductor current level, is the voltage
difference between CSREF and CSCOMP. The output side
of the inductor is used to create a low impedance virtual
ground. The current−sense amplifier actively filters and
gains up the voltage applied across the inductor to recover
the voltage drop across the inductor’s DC resistance (DCR).
RCS_NTC is placed close to the inductor to sense the
temperature. This allows the filter time constant and gain to
be a function of the Rth_NTC resistor and compensate for
the change in the DCR with temperature. The DC gain in the
current sensing loop is
L
C
) C
+
CS2
(eq. 5)
CS1
DCR @ R
CS
Ccs1 and Ccs2 are in parallel to allow for a fine tuning of
the time constant using commonly available values.
In applications with a droop voltage VDROOP, the DC
load line LL can be obtained by
V
V
* V
R
CS
CS
CSREF
I
CSCOMP
(eq. 3)
G
+
+
+
CS
V
@ DCR
R
CS3
DCR
OUT
0.5 @ ǒV
CSCOMPǓ
* V
Where
V
DROOP
CSREF
I
LL +
+
R
@ R
I
CS1
CS_NTC
OUT
OUT
(eq. 6)
(eq. 4)
R
+ R
)
CS
CS2
R
) R
CS_NTC
R
CS1
CS
+ 0.5 @
@ DCR
The values of Rcs1 and Rcs2 are set based on a 220k NTC
thermistor and the temperature effect of the inductor and
R
CS3
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13
NCP81149
Over Current Protection
ground such that a load equal to ICCMAX generates a 2 V
The NCP81149 provides two different types of current
limit protection. Current limits are programmed with a
resistor RILIM between the CSCOMP pin and the ILIM pin.
The current from the ILIM pin to this resistor is then
compared to two internal currents (10 mA and 15 mA)
corresponding to two different current limit thresholds ILIM
and ILIM_Fast (150% of ILIM level). If the ILIM pin
current exceeds the 10 mA level, an internal latch−off timer
starts. The controller shuts down if the fault is not removed
after 50 ms. If the current into the pin exceeds 15 mA the
controller will shut down immediately. To recover from an
OCP fault the EN pin must be cycled low.
signal on IOUT. A pull−up resistor to 5 V V can be used
to offset the IOUT signal positive if needed.
CC
2
R
+
@ R
ILIM
IOUT
10 @ V @ICC_MAX
CS
1
(eq. 9)
+
@ R
ILIM
R
CS
5 @ R
@ ICC_MAX @ DCR
CS3
Input UVLO Protection
NCP81149 monitors supply voltages at the VCC pin and
the VIN pins in order to provide under voltage protection. If
either supply drops below its threshold, the controller will
shut down the outputs. Upon recovery of the supplies, the
controller reenters its startup sequence, and soft start begins.
The value of RILIM can be designed using the following
equation with a required over current protection threshold
ILIM and a known current−sense network.
Output Under−Voltage Protection
(eq. 7)
V
CS@ILIM
RCS
The output voltage is monitored by a dedicated
differential amplifier. If the output falls below target by
more than “Under Voltage Threshold below DAC−Droop”,
the UVL comparator sends the VR_RDY signal low.
RILIM
+
+
@ ILIM_PK @ DCR @ 105
10m
RCS3
ǒ
Ǔ
VIN * VOUT @ VOUT
RCS
+
@
I
)
@ DCR @ 105
ǒ
Ǔ
LIM
RCS3
2 @ L @ FSW @ VIN
Output Over−Voltage Protection
During normal operation the output voltage is monitored
at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by “Over Voltage Threshold above
DAC”, GH will be forced low, and GL will go high. After the
OVP trips, the DAC ramps slowly down to zero to avoid a
negative output voltage spike during shutdown. If the
DAC+OVP Threshold drops below the output, GL will
again go high, and will toggle between low and high as the
output voltage follows the DAC+OVP Threshold down.
When the DAC gets to zero, the GH will be held low and the
GL will remain high. To reset the part, the EN pin must be
cycled low. During soft−start, the OVP threshold is set to
2.9 V. This allows the controller to start up without false
triggering the OVP.
ICC_MAX
A resistor to ground is monitored on startup and this sets
the ICCmax value. A 10 mA current is sourced from this pin
to generate a voltage on the program resistor. The resistor
value can be determined from the below equation. The
resistor value should be no less than 10k.
R
@ 10m @ 64
ICCMAX
−4
ICC_MAX +
+ R
@ 3.2 @ 10
ICCMAX
2
(eq. 8)
IOUT
The IOUT pin sources a current equal to the ILIM sink
current gained by the IOUT Current Gain (10 typ.). The
voltage of the IOUT pin is monitored by the internal A/D
converter and should be scaled with an external resistor to
( a ) During Start Up
(a) Normal Operation Mode
Figure 8. Function of Over Voltage Protection
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14
NCP81149
Temperature Sense and Thermal Alert
voltage to internal thresholds and assert ALERT# or
VRHOT# once it trips the thresholds. The DC voltage at
TSENSE pin can be calculated by
The NCP81149 provides an external temperature sense
and a thermal alert in normal operation mode. The
temperature sense and thermal alert circuit diagram is shown
in Figure 9. A precision current ITSENSE is sourced out the
output of the TSENSE pin to generate a voltage across the
temperature sense network, which consists of a NTC
thermistor R_NTC(100kOhm typ.), two resistors
R_COMP1 (0 W typ.) and R_COMP2 (8.2 kW typ.), and a
filter capacitor C_Filter (0.1 mF typ.). The voltage on the
temperature sense input is sampled by the internal A/D
converter and then digitally converted to temperature and
stored in SVID register 17h. Usually the thermistor is placed
close to a hot spot like inductor or NCP81149 itself. A 100k
R
@ R
NTC_T
COMP2
V
+ I
@
ǒ
R )
COMP1
Ǔ
TSENSE
TENSE
R
) R
NTC_T
COMP2
(eq. 10)
RNTC_T is the resistance of R_NTC at an absolute
temperature T, which is obtained by
1
1
B @ ǒ Ǔ
R
+ R
@ exp
NTC_T0
*
ǒ Ǔ
NTC_T
T
T
0
(eq. 11)
where R
is a known resistance of R_NTC at an
NTC_T0
NTC
thermistor
similar
to
the
Murata
absolute temperature T , and B is the B−constant of R_NTC.
0
NCP15WF104D03RC should be used. The NCP81149 also
monitors the voltage at the TSENSE pin and compares the
TSENSE
34
Thermal
Management
VRHOT#
VRHOT#
1
3.3V
ALERT#
ALERT#
3
Figure 9. Temperature Sense and Thermal Alert Circuit Diagram
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15
NCP81149
LAYOUT GUIDELINES
Electrical Layout Considerations
• Current Sense: Careful layout for current sensing is
critical for jitter minimization, accurate current
limiting, and IOUT reporting. The filter cap from
CSCOMP to CSREF should be close to the controller.
The temperature compensating thermistor should be
placed as close as possible to the inductor. The wiring
path should be kept as short as possible and well away
from the switch node.
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Power Paths: Use wide and short traces for power paths
(such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance and high−frequency loop area. It is
also good for efficiency improvement.
• Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to VIN and PGND pins.
• Compensation Network: The small feedback cap from
COMP to FB should be as close to the controller as
possible. Keep the FB traces short to minimize their
capacitance to ground.
• SVID Bus: For SVID Interface communication details
please contact Intel Inc.
• VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC and VCCP pins. The
filter resistor at VCC pin should be not higher than
2.2 W to prevent large voltage drop.
• Switching Node: SW node should be a copper pour, but
compact because it is also a noise source.
• Bootstrap: The bootstrap cap and an option resistor
need to be very close and directly connected between
pin 8 (BST) and pin 10 (SW). No need to externally
connect pin 10 to SW node because it has been
internally connected to other SW pins.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. Directly connect GND pin to the exposed
pad and then connect to GND ground plane through
vias.
• Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
• Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN48 6x6, 0.4P
CASE 485CJ
ISSUE A
DATE 09 AUG 2012
1
48
SCALE 2:1
EXPOSED Cu
MOLD CMPD
NOTES:
D
A B
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
PIN ONE
REFERENCE
DETAIL B
ALTERNATE
CONSTRUCTION
5. POSITIONAL TOLERANCE APPLIES TO ALL THREE EXPOSED
PADS IN BOTH X AND Y AXIS.
E
L
L
MILLIMETERS
2X
2X
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
−−−
0.15
C
L1
0.20 REF
DETAIL A
0.15
0.25
0.15
C
TOP VIEW
ALTERNATE TERMINAL
CONSTRUCTIONS
D
6.00 BSC
D2
D3
D4
D5
E
E2
E3
E4
e
G3
G4
H2
H3
H4
L
4.53
1.64
2.42
4.58
4.73
1.84
2.62
4.78
A
(A3)
DETAIL B
0.10
C
C
L2
6.00 BSC
1.86
2.41
2.30
2.06
2.61
2.50
0.08
5
A1
45
SEATING
PLANE
SIDE VIEW
D2
NOTE 4
C
0.40 BSC
DETAIL C
1.45 BSC
1.06 BSC
1.40 BSC
1.19 BSC
1.10 BSC
D4
D3
DETAIL A
13
G3
13
G4
25
DETAIL C
0.25
−−−
0.45
0.15
25
E3
E4
L1
L2
H4
H2
0.15 REF
GENERIC
MARKING DIAGRAM*
E2
NOTE 5
1
H3
1
M
0.10
C A B
1
48
37
48X
XXXXXXXXX
XXXXXXXXX
AWLYYWWG
48X
b
0.10
L
48
37
e
M
C
C
A B
e/2
BOTTOM VIEW
D5
0.05 M
NOTE 3
SUPPLEMENTAL
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
XXXXX = Specific Device Code
6.30
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
48X
0.58
WL
YY
WW
G
4.81
48X
0.25
2.09
2.54
*This information is generic. Please refer
to device data sheet for actual part
marking.
4.80 6.30
0.40
PITCH
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.91
2.66
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON80730E
QFN48, 6x6, 0.4MM PITCH
PAGE 1 OF 1
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