NCP81151B [ONSEMI]
Compatible Synchronous Buck MOSFET Driver;
| 型号： | NCP81151B |
| 厂家： | 
ONSEMI |
| 描述： | Compatible Synchronous Buck MOSFET Driver |
| 文件： | 总9页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81151B
VR12.5 Compatible
Synchronous Buck MOSFET
Driver
The NCP81151B is a high performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. It can drive up to 3 nF
load with a 25 ns propagation delay and 20 ns transition time.
Adaptive anti−cross−conduction and power saving operation circuit
can provide a low switching loss and high efficiency solution for
notebook systems.
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MARKING
DIAGRAM
1
1
CPMG
The UVLO function guarantees the outputs are low when the supply
voltage is low.
DFN8
G
CASE 506AA
Features
CP = Specific Device Code
• Faster Rise and Fall Times
M
G
= Date Code
= Pb−Free Package
• Adaptive Anti−Cross−Conduction Circuit
• Zero Cross Detection function
• Output Disable Control Turns Off Both MOSFETs
• Undervoltage Lockout
(Note: Microdot may be in either location)
PINOUT DIAGRAM
• Power Saving Operation Under Light Load Conditions
1
8
BST
DRVH
SW
• Direct Interface to NCP6131 and Other Compatible PWM
Controllers
2
3
4
PWM
EN
7
6
5
FLAG
9
• Thermally Enhanced Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
GND
VCC
DRVL
Typical Applications
• Power Management Solutions for Notebook Systems
ORDERING INFORMATION
†
Device
NCP81151BMNTBG
Package
Shipping
DFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
December, 2015 − Rev. 0
NCP81151B/D
NCP81151B
BST
VCC
DRVH
PWM
Logic
SW
Anti−Cross
Conduction
VCC
DRVL
EN
ZCD
Detection
UVLO
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin No.
Symbol
Description
1
BST
PWM
EN
Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and
the SW pin.
2
3
Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode
Emulation Enabled, High = High Side FET Enabled.
Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input:
EN = High to enable the gate driver;
EN = Low to disable the driver;
EN = Mid to go into diode mode (both high and low side gate drive signals are low)
4
5
6
7
8
9
VCC
DRVL
GND
SW
Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.
Low side gate drive output. Connect to the gate of low side MOSFET.
Bias and reference ground. All signals are referenced to this node.
Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.
High side gate drive output. Connect to the gate of high side MOSFET.
DRVH
FLAG
Thermal flag. There is no electrical connection to the IC. Connect to ground plane.
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2
NCP81151B
APPLICATION CIRCUIT
5V_POWER
VIN
TP1
TP2
+
C4
R164
0.0
Q1
NTMFS4821N
0.027uF
C1
4.7uF
C2
4.7uF
C3 CE9
4.7uF 390uF
R1
1.02
R142
0.0
NCP81151B
TP3
R143
0.0
VREG_SW1_HG
VREG_SW1_OUT
BST HG
PWM SW
EN GND
TP4
PWM
TP5
VCCP
L
235nH
TP7
DRON
TP6
R3
2.2
Q9 Q10
NTMFS4851N NTMFS4851N
VREG_SW1_LG
VCC LG
PAD
CSN11
CSP11
JP13_ETCH
JP14_ETCH
TP8
C5
1uF
C6
2700pF
Figure 2. Application Circuit
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3
NCP81151B
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Symbol
Pin Name
V
MAX
V
MIN
V
CC
Main Supply Voltage Input
6.5 V
−0.3 V
BST
Bootstrap Supply Voltage
35 V wrt/ GND
40 V v 50 ns wrt/ GND
6.5 V wrt/ SW
−0.3 V wrt/SW
7.7 V < 50 ns wrt/ SW
SW
Switching Node (Bootstrap Supply Return)
High Side Driver Output
35 V
40 V v 50 ns
−5 V
−10 V (200 ns)
DRVH
DRVL
BST + 0.3 V
−0.3 V wrt/SW
−2 V (< 200 ns) wrt/SW
Low Side Driver Output
V
+ 0.3 V
−0.3 V DC
CC
−5 V (< 200 ns)
PWM
EN
DRVH and DRVL Control Input
Enable Pin
6.5 V
−0.3 V
−0.3 V
0 V
6.5 V
0 V
GND
Ground
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to AGND unless noted otherwise.
THERMAL INFORMATION
Symbol
Parameter
Thermal Characteristic QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Value
119
Unit
°C/W
°C
R
q
T
T
JA
−40 to 150
−40 to +100
−55 to +150
1
J
°C
A
T
STG
°C
MSL
Moisture Sensitivity Level − QFN Package
*The maximum package power dissipation must be observed.
2
1. 1 in Cu, 1 oz. thickness.
2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM.
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4
NCP81151B
NCP81151B ELECTRICAL CHARACTERISTICS (−40°C < T < +100°C; 4.5 V < V < 5.5 V, 4.5 V < BST−SWN < 5.5 V,
A
CC
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
VCC Operation Voltage
4.5
5.5
V
UNDERVOLTAGE LOCKOUT
VCC Start Threshold
3.8
4.35
200
4.5
V
VCC UVLO Hysteresis
150
250
mV
SUPPLY CURRENT
Shutdown Mode
Normal Mode
I
I
I
+ I , EN = GND
11
20
mA
mA
mA
CC
CC
CC
BST
+ I , EN = 5 V, PWM = OSC
BST
4.7
0.9
Standby Current
+ I , EN = HIGH, PWM = LOW,
BST
No loading on DRVH & DRVL
Standby Current
I
+ I , EN = HIGH, PWM = HIGH,
1.1
0.4
mA
V
CC
BST
No loading on DRVH & DRVL
BOOTSTRAP DIODE
Forward Voltage
V
= 5 V, forward bias current = 2 mA
0.1
0.6
CC
PWM INPUT
PWM Input High
3.4
1.3
V
V
PWM Mid−State
2.7
0.7
PWM Input Low
V
ZCD Blanking Timer
350
ns
HIGH SIDE DRIVER
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time trDRVH
DRVH Fall Time tfDRVH
DRVH Turn−Off Propagation Delay tpdlDRVH
V
V
V
V
−V
= 5 V
= 5 V
0.9
0.7
16
1.7
1.7
25
18
30
W
W
BST SW
−V
BST SW
= 5 V, 3 nF load, V
−V
BST SW
= 5 V
=5 V
ns
ns
ns
CC
CC
11
= 5 V, 3 nF load, V
−V
BST SW
10
10
C
C
= 3 nF
= 3 nF
LOAD
LOAD
DRVH Turn−On Propagation Delay tpdhDRVH
40
ns
SW Pulldown Resistance
SW to PGND
DRVH to SW, BST−SW = 0 V
45
45
kW
kW
DRVH Pulldown Resistance
LOW SIDE DRIVER
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time trDRVL
0.9
0.4
16
1.7
0.8
25
W
W
ns
C
C
C
C
= 3 nF
= 3 nF
= 3 nF
= 3 nF
LOAD
LOAD
LOAD
LOAD
DRVL Fall Time tfDRVL
11
15
30
25
ns
ns
ns
kW
DRVL Turn−Off Propagation Delay tpdlDRVL
DRVL Turn−On Propagation Delay tpdhDRVL
DRVL Pulldown Resistance
10
5.0
DRVL to PGND, V = PGND
45
CC
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5
NCP81151B
NCP81151B ELECTRICAL CHARACTERISTICS (−40°C < T < +100°C; 4.5 V < V < 5.5 V, 4.5 V < BST−SWN < 5.5 V,
A
CC
4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
EN INPUT
Input Voltage High
3.3
V
V
Input Voltage Mid
1.35
1.8
0.6
1.0
40
Input Voltage Low
V
Input bias current
−1.0
mA
ns
Propagation Delay Time
SW NODE
20
SW Node Leakage Current
Zero Cross Detection Threshold Voltage
20
mA
−6.0
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCP81151B
Table 1. DECODER TRUTH TABLE
Input
ZCD
DRVL
Low
DRVH
High
Low
PWM High (Enable High)
PWM Mid (Enable High)
PWM Mid (Enable High)
PWM Low (Enable High)
Enable at Mid
ZCD Reset
Positive Current Through the Inductor
High
Low
Zero Current Through the Inductor
Low
ZCD Reset
X
High
Low
Low
Low
1V
1V
Figure 3.
PWM
DRVH−SW
DRVL
IL
Figure 4. Timing Diagram
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7
NCP81151B
APPLICATION INFORMATION
The NCP81151B gate driver is a single phase MOSFET
high after the tpdhDRVH delay. When PWM is set low, the
driver will monitor the gate voltage of the high side
MOSFET. When the DRVH−SWN voltage falls below the
top gate drive threshold, DRVL will be set to high after the
tpdhDRVL delay.
driver designed for driving N−channel MOSFETs in a
synchronous buck converter topology. The NCP81151B is
designed to work with ON Semiconductor’s NCP6131
multi−phase controller. This gate driver is optimized for
notebook applications.
Layout Guidelines
The layout for a DC−DC converter is very important. The
bootstrap and VCC bypass capacitors should be placed close
to the driver IC.
Undervoltage Lockout
DRVH and DRVL are held low until VCC reaches 4.5 V
during startup. The PWM signal will control the gate status
when VCC threshold is exceeded.
Connect the GND pin to a local ground plane. The ground
plane can provide a good return path for gate drives and
reduce the ground noise. The thermal slug should be tied to
the ground plane for good heat dissipation. To minimize the
ground loop for the low side MOSFET, the driver GND pin
should be close to the low−side MOSFET source pin. The
gate drive trace should be routed to minimize its length. The
minimum width is 20 mils.
Three−State EN Signal
When EN is set to the mid state, both DRVH and DRVL
are set low, to force diode mode operation.
PWM Input and Zero Cross Detect (ZCD)
The PWM input, along with EN and ZCD, control the state
of DRVH and DRVL.
When PWM is set high, DRVH will be set high after the
adaptive non−overlap delay. When PWM is set low, DRVL
will be set high after the adaptive non−overlap delay.
When PWM is set to the mid state, DRVH will be set low,
and after the adaptive non−overlap delay, DRVL will be set
high. DRVL remains high during the ZCD blanking time.
When the timer has expired, the SW pin will be monitored
for zero cross detection. After the detection, DRVL will be
set low.
Gate Driver Power Loss Calculation
The gate driver power loss consists of the gate drive loss
and quiescent power loss.
The equation below can be used to calculate the power
dissipation of the gate driver. QGMF is the total gate charge
for each main MOSFET and QGSF is the total gate charge for
each synchronous MOSFET.
PDRV
+
fSW
ǒ
Ǔ
ƪ
ƫ
(eq. 1)
Adaptive Non−overlap
nMF QGMF ) nSF QGSF ) ICC VCC
2 n
Adaptive dead time control is used to avoid shoot−through
damage of the power MOSFETs. When the PWM signal
pulls high, DRVL will be set low and the driver will monitor
the gate voltage of the low side MOSFET. When the DRVL
voltage falls below the gate threshold, DRVH will be set to
Also shown is the standby dissipation factor (ICC x VCC)
of the driver.
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8
NCP81151B
PACKAGE DIMENSIONS
DFN8 2x2
CASE 506AA
ISSUE E
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
OPTIONAL
CONSTRUCTIONS
E
MILLIMETERS
2X
0.15
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
2X
0.15
C
TOP VIEW
0.20
0.30
1.30
D
2.00 BSC
D2
E
1.10
2.00 BSC
A
C
DETAIL B
0.10
0.08
C
C
DETAIL B
OPTIONAL
CONSTRUCTION
E2
e
0.70
0.50 BSC
0.90
0.30 REF
0.25
−−−
K
L
L1
0.35
0.10
(A3)
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
D2
8X
0.50
8X
L
1.30
4
1
PACKAGE
OUTLINE
E2
0.90
2.30
5
8
K
8X b
e/2
1
0.10
0.05
C
C
A
B
e
8X
0.30
NOTE 3
0.50
PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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For additional information, please contact your local
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NCP81151B/D
相关型号：
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