NCP81152 [ONSEMI]
Synchronous Buck Dual MOSFET Driver;
| 型号： | NCP81152 |
| 厂家： | 
ONSEMI |
| 描述： | Synchronous Buck Dual MOSFET Driver |
| 文件： | 总8页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81152
Synchronous Buck Dual
MOSFET Driver
The NCP81152 is a high−performance dual MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Two drivers are
co−packaged into a 2.5 mm x 3.5 mm QFN16 package that greatly
reduces the footprint compared to two discrete drivers. Adaptive
anti−cross−conduction circuitry and power saving operation provides
a low−switching−loss and high−efficiency solution for notebook
systems. The under−voltage lockout function guarantees the outputs
are low when the supply voltage is low.
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1
QFN16
MN SUFFIX
CASE 485AW
Features
• Adaptive Anti−Cross−Conduction Circuit
• Integrated Bootstrap Diode
MARKING DIAGRAM
• Zero Cross Detection
81152
ALYWG
G
• Floating Top Driver Accommodates Boost Voltages up to 35 V
• Output Disable Control Turns Off Both MOSFETs
• Under−voltage Lockout
• Power Saving Operation Under Light Load Conditions
• Thermally Enhanced Package
• These are Pb−Free Devices
81152 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
(Note: Microdot may be in either location)
• Vcore Power for Notebook Systems
• Power Systems for DDR and Graphics
PIN CONNECTIONS
1
16
PWM1
EN1
SW1
GND1
DRVL1
DRVH2
SW2
VCC1
BST2
PWM2
EN2
GND2
(Top View)
ORDERING INFORMATION
†
Device
NCP81152MNTWG
Package
Shipping
QFN16
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
January, 2015 − Rev. 2
NCP81152/D
NCP81152
BST1
VCC1
DRVH1
Logic
PWM1
SW1
Anti−Cross
Conduction
VCC1
DRVL1
EN1
Zero
Cross
Detection
UVLO
VCC2
BST2
DRVH2
PWM2
Logic
SW2
Anti−Cross
Conduction
VCC2
DRVL2
Zero
EN2
Cross
Detection
UVLO
Figure 1. Block Diagram
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NCP81152
Table 1. PIN DESCRIPTIONS
Pin No.
Symbol
Description
1, 5
BST1, BST2
Floating bootstrap supply pin for high−side gate driver. Connect the bootstrap capacitor between this pin
and the SW pin.
2, 6
3, 7
PWM1, PWM2
EN1, EN2
Control input. The PWM signal has three states:
PWM = High enables the high−side FET;
PWM = Mid enables zero cross detection;
PWM = Low enables the low−side FET.
Logic input. Three−state logic input:
EN = High enables the driver;
EN = Mid goes into diode braking mode (both high−side and low−side gate drive signals are low);
EN = Low disables the driver.
4, 8
9, 13
10, 14
11, 15
12, 16
17
VCC1, VCC2
DRVL1, DRVL2
GND1, GND2
SW1, SW2
Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.
Low−side gate drive output. Connect to the gate of the low−side MOSFET.
Bias and reference ground. All signals are referenced to this node.
Switch node. Connect this pin to the source of the high−side MOSFET and drain of the low−side MOSFET.
High−side gate drive output. Connect to the gate of the high−side MOSFET.
Thermal flag. There is no electrical connection to the IC. Connect to ground plane.
DRVH1, DRVH2
FLAG
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
VCC1, VCC2
BST1, BST2
Pin Name
V
V
MIN
MAX
Main Supply Voltage Input
Bootstrap Supply Voltage
6.5 V
−0.3 V
35 V wrt/ GND
40 V ≤ 50 ns wrt/ GND
6.5 V wrt/ SW
−0.3 V wrt/SW
SW1, SW2
Switching Node
(Bootstrap Supply Return)
35 V
40 V ≤ 50 ns
−5 V
−10 V (200 ns)
DRVH1, DRVH2
DRVL1, DRVL2
High Side Driver Output
BST+0.3 V
−0.3 V wrt/SW
−2 V (<200 ns) wrt/SW
Low Side Driver Output
VCC+0.3 V
−0.3 V DC
−5 V (<200 ns)
PWM1, PWM2
EN1, EN2
DRVH and DRVL Control Input
Enable Pin
6.5 V
6.5 V
0 V
−0.3 V
−0.3 V
0 V
GND1, GND2
Ground
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to AGND unless noted otherwise.
Table 3. THERMAL INFORMATION
Parameter
Thermal Characteristic (Note 1)
Symbol
Value
29
Unit
°C/W
°C
R
q
JA
Operating Junction Temperature Range
Operating Ambient Temperature Range
T
J
−40 to +150
−40 to +100
−55 to +150
1
T
A
°C
Maximum Storage Temperature Range
T
STG
°C
Moisture Sensitivity Level − QFN Package
*The maximum package power dissipation must be observed.
MSL
2
1. 1 in Cu., 1 oz. thickness.
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NCP81152
Table 4. NCP81152 DRIVER ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < +100°C; VCC = 4.5 V ~ 5.5 V; BST−SW = 4.5 V ~ 5.5 V; BST = 4.5 V ~ 30 V; SWN = 0 V ~ 21 V.
A
Parameter
SUPPLY VOLTAGE
Test Conditions
Min
Typ
Max
Units
VCC1, VCC2 Operation Voltage
UNDERVOLTAGE LOCKOUT (VCC1, VCC2)
Start Threshold
4.5
5.5
V
3.8
4.35
200
4.5
V
Hysteresis
150
250
mV
SUPPLY CURRENT
Normal Mode
I
+ I
CC2
+ I
BST1
+ I
BST2
9.4
mA
CC1
EN1, EN2 = 5 V,
PWM1 & PWM2 oscillating at 100 kHz,
= 3 nF
C
LOAD
Shutdown Mode
I
+ I
CC2
+ I
BST1
+ I
BST2
22
40
mA
CC1
EN1, EN2 = Gnd
+ I + I
BST1
Standby Current 1
I
+ I
BST2
1.8
mA
CC1
CC2
EN1, EN2 = Logic High,
PWM1, PWM2 = Logic Low,
No loading on DRVH1/2 & DRVL1/2
Standby Current 2
I
+ I
+ I
+ I
BST2
2.2
0.4
mA
CC1
CC2
BST1
EN1, EN2 = Logic High,
PWM1, PWM2 = Logic High,
No loading on DRVH1/2 & DRVL1/2
BOOTSTRAP DIODE
Forward Voltage
VCC = 5 V, forward bias current = 2 mA
0.1
0.6
V
PWM INPUT
Input High
3.4
1.3
V
V
Mid−State
2.45
0.7
Input Low
V
ZCD blanking timer
350
ns
HIGH SIDE DRIVER (DRVH1, DRVH2)
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
BST − SW = 5 V
0.9
0.7
16
1.7
1.7
25
18
30
40
W
W
BST − SW = 5 V
Rise Time, tr
VCC = 5 V, 3 nF load, BST − SW = 5 V
VCC = 5 V, 3 nF load, BST − SW = 5 V
ns
ns
ns
ns
kW
kW
DRVH
DRVH
Fall Time, tf
11
Turn−Off Propagation Delay, tpdlDRVH
Turn−On Propagation Delay, tpdhDRVH
SW Pull−Down Resistance
C
C
= 3 nF
= 3 nF
10
10
LOAD
LOAD
SW to PGND
45
45
DRVH Pull−Down Resistance
DRVH to SW, V
−V
= 0 V
BST SW
LOW SIDE DRIVER (DRVL1, DRVL2)
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
0.9
0.4
16
1.7
0.8
25
15
30
25
W
W
Rise Time, tr
C
C
C
C
= 3 nF
= 3 nF
= 3 nF
= 3 nF
ns
ns
ns
ns
kW
DRVH
DRVH
LOAD
LOAD
LOAD
LOAD
Fall Time, tf
11
Turn−Off Propagation Delay, tpdlDRVH
Turn−On Propagation Delay, tpdhDRVH
DRVL Pull−Down Resistance
10
5
DRVL to PGND, VCC = PGND
45
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NCP81152
Table 4. NCP81152 DRIVER ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < +100°C; VCC = 4.5 V ~ 5.5 V; BST−SW = 4.5 V ~ 5.5 V; BST = 4.5 V ~ 30 V; SWN = 0 V ~ 21 V.
A
Parameter
ENABLE INPUT (EN1, EN2)
Input High
Test Conditions
Min
Typ
Max
Units
3.3
V
V
Mid−State
1.35
1.8
0.6
1
Input Low
V
Normal Mode Bias Current
Propagation Delay Time
SWITCH NODE (SW1, SW2)
SW Leakage Current
Zero Cross Detection Threshold Voltage
−1
mA
ns
20
−6
40
20
mA
SW to −20 mV, ramp slowly until BG goes off
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 5. PWM/EN TRUTH TABLE
PWM INPUT
PWM High
PWM Mid
ZCD
DRVL
Low
DRVH
High
Low
ZCD Reset
Positive current through the inductor
High
Low
PWM Mid
Zero or negative current through the inductor
Low
PWM Low
Enable at Mid
ZCD Reset
X
High
Low
Low
Low
PWM
DRVL
tpdl
tf
DRVL
DRVL
90%
90%
10%
1 V
10%
tr
DRVL
tf
tpdl
DRVH
DRVH
tpdh
tr
DRVH
DRVH
90%
90%
10%
tpdh
10%
1 V
DRVH−
SW
DRVL
Figure 2. Timing Diagram
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NCP81152
PWM
DRVH−SW
DRVL
IL
Figure 3. Logic Diagram
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6
NCP81152
Application Information
The NCP81152 is a high−performance dual MOSFET
voltage supply for the low−side driver is internally
connected to the VCC and GND pins.
gate driver optimized to drive the gates of both high−side
and low−side power MOSFETs in a synchronous buck
converter. Two drivers are co−packaged into a 2.5 mm x 3.5
mm QFN16 package that greatly reduces the footprint
compared to two discrete drivers.
High−Side Driver
The high−side driver is designed to drive a floating
low−R
N−channel MOSFET. The gate voltage for the
DS(on)
high−side driver is developed by a bootstrap circuit
referenced to the SW pin.
Undervoltage Lockout
DRVH and DRVL are low until VCC reaches the VCC
UVLO threshold, typically 4.35 V. When VCC reaches this
threshold, the PWM signal controls the states of DRVH and
DRVL. There is a 200 mV hysteresis on VCC UVLO. There
are pull−down resistors on DRVH, DRVL and SW that
prevent the gates of the MOSFETs from accumulating
enough charge to turn on when the driver is powered off.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor. When the NCP81152 is
starting up, the SW pin is held at ground, allowing the
bootstrap capacitor to charge up to VCC through the
bootstrap diode. When the PWM input is driven high, the
high−side driver turns on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin rises. When the high−side
MOSFET fully turns on, SW settles to VIN and BST settles
to VIN + VCC (excluding parasitic ringing).
Three−State EN Signal
Placing EN into a logic−high or logic−low turns the driver
on and off, respectively, as long as VCC is greater than the
UVLO threshold. The EN threshold limits are specified in
the electrical characteristics table in this datasheet. Setting
the EN voltage to a mid−state level pulls both DRVH and
DRVL low.
Setting EN to the mid−state level can be used for body
diode braking to quickly reduce the inductor current. By
turning the LS FET off and having the current conduct
through the LS FET body diode, the voltage at the switch
node is at a greater negative potential compared to having
the LS FET on. This greater negative potential on switch
node allows there to be a greater voltage across the output
inductor, since the opposite terminal of the inductor is
connected to the converter output voltage. The larger
voltage across the inductor causes there to be a greater
inductor current slew rate, allowing the current to decrease
at a faster rate.
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (C ) and an integrated diode to provide current
BST
to the high−side driver. A multi−layer ceramic capacitor
(MLCC) with a value greater than 100 nF should be used for
C
.
BST
Thermal Considerations
As power in the NCP81152 increases, it may be necessary
to provide thermal relief. The maximum power dissipation
supported by the device depends upon board design and
layout. Mounting pad configuration on the PCB, the board
material, and the ambient temperature affect the rate of
junction temperature rise for the part. When the NCP81152
has good thermal conductivity through the PCB, the
junction temperature is relatively low with high power
applications. The maximum dissipation the NCP81152 can
handle is given by:
PWM Input and Zero Cross Detect (ZCD)
The PWM input, along with EN and ZCD, controls the
state of DRVH and DRVL. When PWM is set high, DRVH
is set high after the adaptive non−overlap delay. When PWM
is set low, DRVL is set high after the adaptive non−overlap
delay.
ƪT
ƫ
J(MAX) * TA
(eq. 1)
PD(MAX)
+
RqJA
Since T is not recommended to exceed 150°C, the
NCP81152, soldered on to a 645 mm copper area, using
J
2
When PWM is set to the mid−state, DRVH is set low, and
after the adaptive non−overlap delay, DRVL is set high.
DRVL remains high until the ZCD blanking time expires.
When the timer expires, the voltage on the SW pin is
monitored for zero cross detection (whether it has crossed
the ZCD threshold voltage). After zero cross is detected,
DRVL is set low.
1 oz. copper and FR4, can dissipate up to 4.3 W when the
ambient temperature (T ) is 25°C. The power dissipated by
A
the NCP81152 can be calculated from the following
equation:
ƪ
(eq. ƫ2)
PD [ VCC @ (nHS @ QgHS ) nLS @ QgLS) @ f ) Istandby
Where n and n are the number of high−side and
HS
LS
Low−Side Driver
The low−side driver is designed to drive
ground−referenced low−R N−channel MOSFET. The
low−side FETs, respectively, Qg and Qg are the gate
HS
LS
a
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
DS(on)
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NCP81152
PACKAGE DIMENSIONS
QFN16, 2.5x3.5, 0.5P
CASE 485AW
ISSUE O
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
0.20
0.30
0.15
C
2X
D
2.50 BSC
D2
E
0.85
1.15
3.50 BSC
2X
0.15
C
E2
e
1.85
2.15
TOP VIEW
DETAIL B
0.50 BSC
ALTERNATE
K
0.20
0.35
---
---
0.45
0.15
A
CONSTRUCTIONS
L
DETAIL B
(A3)
A1
L1
0.10
0.08
C
C
16X
NOTE 4
SEATING
PLANE
C
SIDE VIEW
SOLDERING FOOTPRINT*
0.15 C A B
D2
3.80
2.10
K
16X L
8
10
0.15 C A B
0.50
PITCH
DETAIL A
2.80 1.10
E2
16X
b
1
0.10 C A B
2
PACKAGE
OUTLINE
15
16X
0.30
16X
0.60
0.05
C
NOTE 3
1
e
DIMENSIONS: MILLIMETERS
e/2
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NCP81152/D
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