NCP81561MNTXG [ONSEMI]
Single-Phase Voltage Regulator for Computing Applications;
| 型号： | NCP81561MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | Single-Phase Voltage Regulator for Computing Applications |
| 文件： | 总12页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Single-Phase Voltage
Regulator for Computing
Applications
QFN20
CASE 485EE
MARKING DIAGRAMS
NCP81561
The NCP81561 is a high−performance, low−bias current,
single−phase regulator with integrated power MOSFET driver.
Operating in high switching frequency up to 600 kHz allows
employing small size inductor and capacitors. The controller makes
use of onsemi’s patented high performance RPM operation. RPM
control maximizes transient response while allowing for smooth
transitions between discontinuous−frequency−scaling operation and
continuous−mode full−power operation. The NCP81561 has an
ultra−low offset current monitor amplifier with programmable offset
compensation for high−accuracy current monitoring.
81561
AWLYWW
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
WW
= Work Week
Features
• Auto DCM Operation
ORDERING INFORMATION
†
Device
NCP81561MNTXG
Package
Shipping
• High Performance RPM Control System
• 2−Bit VID Selects 0 V and Three Preset Voltages
QFN20
(Pb−Free)
4000 / Tape
& Reel
• Ultra Low Offset I
Monitor with DCR Current Sense
OUT
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Differential Remote Output Voltage Sensing
• Soft Transient Control Reduces Inrush Current and Audio Noise
• Dynamic VID Feed−forward
• Externally Programmable Droop Gain
• Automatic Power Saving Mode
• Input Supply Voltage Feed−forward Control
• Built−in Over−voltage, Under−voltage and Pin Programmable
Over−current Protection
• Power Good Output
• Zero Droop Capable
• Ultrasonic Operation
• Programmable Operating Frequency
• QFN20 4 mm x 4 mm Package
Applications
• Notebooks, Desktops & Servers
• I/O Supplies
• System Power Supplies
• Graphic Cards
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
May, 2022 − Rev. 0
NCP81561/D
NCP81561
VFF
ZCD
COMPARATOR
EN
UVLO
&
VCC
ENABLE
−t°
CSN
NTC
RS
ILIMIT
−gm
CSP
UVP
RCS
MONITOR
IOUT
R
ISET
Droop Function
OVP
MONITOR
DAC
VSP
VSN
VOUT+
−gm
VOUT−
VFF
VRMP
PVCC
RPM TRIGGER
AND
PWM CONTROL
FUNCTION
DACFF
Function
COMP
VIN
COMP
CLAMP
HG
BST
PGOOD
VOUT+
GATE
DRIVER
SW
VREF
DAC
VID0
VID1
2 BIT
VID
VOUT−
LG
PGND
DOSC
VREF
−
OCP
ILIMIT
+
ILIMIT
Figure 1. Block Diagram
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2
NCP81561
Figure 2. Pin Configuration
Table 1. PIN DESCRIPTION
Pin
1
Name
EN
Description
Logic control to enable the part.
2
VID0
Logic input for reference voltage selector. Use in conjunction with the VID1 pin to select among
four set−point reference voltages.
3
VID1
Logic input for reference voltage selector. Use in conjunction with the VID0 pin to select among
four set−point reference voltages.
4
5
PGOOD
VRMP
Power good indicator of the output voltage. Open−drain output
Feed−forward input of Vin for the ramp slope compensation. The voltage on this pin is used to
control of the ramp of PWM slope. This pin should be filtered to GND using a 10 nF capacitor and
connected to Vin via a 1 kW resistor.
6
7
BST
HG
Provides bootstrap voltage for the HS gate driver. A cap is required from this pin to SW.
Gate driver output for the top N−channel MOSFET.
8
SW
Switching node between the external top MOSFET and bottom MOSFET
Gate driver output for bottom N−channel MOSFET.
9
LG
10
PVCC
Power supply for MOSFET gate drivers. Place a 4.7 mF or larger ceramic capacitor between this
pin and PGND.
11
12
13
14
15
16
17
18
19
20
PGND
DOSC
ILIM
Power ground for MOSFET gate drive
Select the switching frequency by connecting a resistor from this pin to ground.
Current−limit programming
VSP
Differential output voltage sense positive
Differential output voltage sense negative
Compensation return for single phase regulator
Differential current sense negative
VSN
COMP
CSN
CSP
Differential current sense positive
IOUT
VCC
IOUT gain programming
Power supply input pin of control circuits. A 1 mF or larger ceramic capacitor bypasses this input
to ground, placed close to the controller
21
GND
Analog ground. Bottom thermal pad.
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3
NCP81561
Table 2. ABSOLUTE MAXIMUM RATINGS
Value
Min
Max
Rating
Symbol
Unit
Switch node to PGND
V
SW
−0.3
−7 (< 5 ns)
30
V
33 (< 40 ns)
VCC to GND
PVCC to PGND
VRMP to PGND
BST to PGND
BST to SW
V
−0.3
−0.3
−0.3
−0.3
−0.3
6
6
V
V
V
V
V
CC
PV
CC
V
RMP
25
33
BST_PGND
BST_SW
6
7 (< 100 ns)
HG to SW
LG to GND
HG
LG
−0.3
−2 (<200 ns)
BST + 0.3
V
V
−0.3
PV + 0.3
CC
−2 (<200 ns)
VSN to GND
PGND to GND
Other Pins
VSN
−0.3
−0.3
−0.3
0.3
0.3
V
V
PGND
V
+ 0.3
V
CC
Latch Up Current: (Note 1)
− All pins, except digital pins
− Digital pins
I
LU
mA
−100
−10
100
10
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
T
−40
−40
−40
125
100
150
°C
°C
°C
J
T
A
T
STG
MSL
HBM
CDM
1
ESD Human Body Model
2000
1000
V
V
ESD Charged device model
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 Class II.
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Resistance Junction to Board
Thermal Resistance Junction to Ambient
Symbol
Value
8.2
Unit
°C/W
°C/W
Rθ
Rθ
JB
JA
21.8
Table 4. RECOMMENDED OPERATING RANGES
Parameter
Symbol
Min
4.75
4.75
Max
5.25
5.25
Unit
V
VCC Voltage Range
V
CC
PVCC Voltage Range
PV
V
CC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCP81561
Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
BIAS SUPPLY
Test Condition
Min
Typ
Max
Unit
VCC Quiescent Current
VCC UVLO Threshold
EN = high
8
12
mA
mA
mA
V
EN = high, VID[0..1] = 00
EN = low
70
400
VCC rising
4.6
VCC falling
3.9
3
V
VCC UVLO Hysteresis
VRMP UVLO Threshold
150
mV
V
VIN rising
VIN falling
4.25
V
VRMP UVLO Hysteresis
DRIVE SUPPLY
870
2
mV
PVCC Quiescent Current
ENABLE INPUT
EN = low
mA
Enable High Input Leakage Current
Upper Threshold
Enable = 0
−1.0
0
1.0
0.3
mA
V
0.8
Lower Threshold
V
Enable Hysteresis
300
200
mV
ms
Enable Delay Time
Measure time from Enable transitioning
HI, to PGOOD high
500
OSCILLATOR
Switching Frequency Range
270
360
540
−10
300
400
600
330
440
660
10
kHz
%
RDOSC = 2 kW 1%
RDOSC = 6 kW 1%
RDOSC = 15 kW 1%
Switching Frequency Accuracy
PGOOD OUTPUT
Output Low Saturation Voltage
Rise Time
I
= 4 mA
0.3
V
PGOOD
External pull−up of 1 KW to 3.3 V, C
= 45 pF, ΔVo = 10% to 90%
150
ns
TOT
Fall Time
External pull−up of 1 KW to 3.3 V, C
= 45 pF, ΔVo = 90% to 10%
150
ns
TOT
Output Voltage at Power−up
Output Leakage Current When High
Power Good Startup Delay
PGOOD pulled up to 5 V via 2 kW
1.2
1.0
1.9
V
PGOOD = 5.0 V
−1.0
mA
ms
Measured from VCC > VCC
1.2
UVLO(rising)
to PGOOD rising, with EN = High
2−Bit VID
VID0, VID1 High Threshold Voltage
VID0, VID1 Low Threshold Voltage
VID0, VID1 Input Bias Current
VID0, VID1 Pull Down Current
VID Delay time
0.72
V
V
0.34
1
nA
mA
ns
2.5
200
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5
NCP81561
Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
Test Condition
Min
Typ
Max
Unit
2−Bit VID
VOUT
VID1 = 0, VID0 = 0
0.00
1.10
1.65
1.80
24
V
VID1 = 0, VID0 = 1
VID1 = 1, VID0 = 0
VID1 = 1, VID0 = 1
VID UP
1.07
1.60
1.75
1.13
1.70
1.85
V
V
V
VOUT Slew Rate
mV/ms
VID Down
24
DIFFERENTIAL VOLTAGE SENSE AMPLIFIER
Input Bias Current
VSP Input Voltage Range
VSN Input Voltage Range
gm
VID0,1 = 0 V, VOUT = 0 V
−2
2
mA
V
2
−0.15
0.15
1.95
V
VSP = 1.65 V, VSN = 0 V
1.29
1.6
73
mS
dB
MHz
mA
mA
Open loop Gain
−3 dB Bandwidth
Source Current
Sink Current
Load = 1 nF in series with 1 kW in
parallel with 10 pF to ground
15
Input Differential −200 mV
280
280
Input Differential 200 mV
IOUT
Analog Gain Accuracy
Gm
0 V < CSP − CSN < 0.1 V
−5
5
%
mS
nA
0.95
−150
1.0
1.05
150
IOUT Offset Current
0 V < VOUT < 2.5 V
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Overvoltage Threshold
Over Voltage Delay
VCSN − VGND
2.4
2.5
200
400
290
25
2.6
V
CSN rising to LG high
CSN rising to PGOOD low
VSP−GND falling
ns
Over Voltage PGOOD Delay
Under Voltage Threshold
Under Voltage Hysteresis
Under Voltage Blanking Delay
DROOP
ns
200
400
mV
mV
ms
VSP−GND falling/rising
VSP−GND falling to PGOOD falling
5
Gm
0.94
1.0
60
1.04
1.6
mS
mA
dB
Offset Accuracy
−1.6
Common mode rejection
OVERCURRENT PROTECTION
ILIM Threshold
CSP input at 1.1 V, 1.65 V and 1.8 V
1.275
1.3
280
1.0
1.325
V
ILIM Delay
ns
ILIM Gain
I
/(CSP−CSN) CSP−CSN = 20 mV
mS
ILIM
CSP−CSN ZCD COMPARATOR
Offset Accuracy
−1.75
−0.25
1.25
mV
HIGH−SIDE GATE DRIVE
Pull−High Drive On Resistance
V
– V
DRV_HH
= 5 V
= 5 V
1
2.5
2.0
W
W
BST
SW
R
Pull−Low Drive On Resistance
V
BST
– V
0.8
SW
R
DRV_HG
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6
NCP81561
Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −40°C < T < 100°C; 4.75 V < V < 5.25 V; C = 0.1 mF
VCC
A
CC
Parameter
HIGH−SIDE GATE DRIVE
HG Propagation Delay Time
Test Condition
Min
Typ
Max
Unit
From LG falling to HG rising
7
4
13
30
ns
T
HG_d
HG Rise Time
THG_R
THG_F
27
20
ns
ns
HG Fall Time
9
HG Pulldown Resistance
LOW−SIDE GATE DRIVE
Pull−High Drive On Resistance
V
– V
= 0 V
300
kW
BST
SW
PV – V
R
= 5 V
0.9
0.6
8
2.5
1.25
20
W
W
CC
PGND
DRV_LH
Pull−Low Drive On Resistance
PV – V
R
= 5 V
CC
PGND
DRV_LL
LG Propagation Delay Time
From HG falling to LG rising
2
ns
T
LG_d
LG Rise Time
TLG_R
TLG_F
18
12
27
25
ns
ns
LG Fall Time
SW to PGND RESISTANCE
SW to PGND Pull−Down Resistance
BOOTSTRAP RECTIFIER SWITCH
Output Low Resistance
R
2
kW
SW
EN=L or EN=H and LG=H
R
5
13
21
W
on_BST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design, not tested in production.
Figure 3. Driver Timing Diagram
NOTE: Timing is referenced to the 90% and the 10% points, unless otherwise stated.
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7
NCP81561
General
Differential Current Feedback Amplifier
The NCP81561 is a single phase controller with a built in
The NCP81561 controller has a low offset, differential
amplifier to sense output inductor current. An external low
pass filter can be used to superimpose a reconstruction of the
AC inductor current onto the DC current signal sensed
across the inductor. The low pass filter time constant should
match the inductor L/DCR time constant by setting the filter
pole frequency equal to the zero of the output inductor. This
makes the filter AC output mimic the product of AC inductor
current and DCR, with the same gain as the filter DC output.
It is best to perform fine tuning of the filter pole during
transient testing.
gate driver. The controller makes use of a digitally enhanced
high performance current mode RPM control method that
provides excellent transient response while minimizing
transient aliasing. The average operating frequency is
digitally stabilized to remove frequency drift under all
continuous mode operating conditions. At light load the
NCP81561 automatically transitions into DCM operation to
save power.
Switching Frequency Programming
A fixed precision oscillator is provided. The actual
switching frequency is set at 300 kHz, 400 kHz or 600 kHz
by the resistor on the DOSC pin. The resistor and frequency
can be referred to in the table below.
DCR@25° C
(eq. 2)
FZ
FP
+
+
2 @ p @ L
1
ǒ Ǔ
PH@ Rth)RCS
R
2 @ p @ ǒ Ǔ@ CCS
R
PH)Rth)RCS
DOSC Resistor
2 kW
6 kW
15 kW
Switching Frequency
300 kHz
400 kHz
600 kHz
Forming the low pass filter with an NTC thermistor (Rth)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
After the NCP81561 is enabled, but before the soft−start
ramp up, the oscillator frequency is detected on the DOSC
pin. A current is sourced out of the DOSC pin, and at the end
of the detection time, the voltage on the DOSC pin is
measured and use to set the switching frequency.
with temperature. The values of R and R are set based
PH
CS
on the effect of temperature on both the thermistor and
inductor. The CSP and CSN pins are high impedance inputs,
but it is recommended that the low pass filter resistance not
exceed 10 kW in order to avoid offset due to leakage current.
It is also recommended that the voltage sense element
(inductor DCR) be no less than 0.5 mW for sufficient current
accuracy. Recommended values for the external filter
components are:
Remote Sense Error Amplifier
A high performance, high input impedance, true
differential transconductance amplifier is provided to
accurately sense the regulator output voltage and provide
high bandwidth transient performance. The VSP and VSN
inputs should be connected to the regulator’s output voltage
sense points through filter networks describe in the Droop
Compensation and DAC Feedforward Compensation
sections. The remote sense error amplifier outputs a current
proportional to the difference between the output voltage
and the DAC voltage:
L
CCS
+
(eq. 3)
ǒ
Ǔ
R
PH@ Rth)RCS
PH)Rth)RCS
@ DCR
R
For an NTC with an Rth of 100 kW at 25°C and a typical
Beta of 4300, an R = 7.68 kW and an R = 13.8 kW
PH
CS
provide the optimum DCR compensation in the temperature
range of 0°C to 75°C.
Using 2 parallel capacitors in the low pass filter allows
fine tuning of the pole frequency using commonly available
capacitor values.
ƪ
ǒ
Ǔƫ
I
COMP + gm @ VDAC * VVSP * VVSN
(eq. 1)
This current is applied to a standard Type II compensation
network.
VR Voltage Compensation
The DC gain equation for the current sense amplifier
output is:
The Remote Sense Amplifier outputs a current that is
applied to a Type II compensation network formed by
external tuning components CLF, RZ and CHF.
Rth ) RCS
PH ) Rth ) RCS
VCURR
+
@ Iout @ DCR
(eq. 4)
R
DAC
VSN
VSN
gm
VSP
VSP
COMP
RZ
CHF
CLF
Figure 4. Voltage Compensation
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8
NCP81561
RPH
RCS
+
CSP
CSN
CURRENT
SENSE AMP
Av=1
_
TO
INDUCTOR
t
CCS
Rth
COMP
CURR
PWM
GENERATOR
Figure 5. Current Feedback Amplifier
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
voltage V
, proportional to load current. This
DROOP
characteristic can reduce the output capacitance required to
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
In the NCP81561, a loadline is produced by adding a signal
proportional to output load current (V
voltage feedback signal – thereby satisfying the voltage
regulator at an output voltage reduced proportional to load
2−Bit VID Interface
Intel® proprietary. Contact Intel Corporation for details
on 2−Bit VID interface.
) to the output
DROOP
Loadline Programming (DROOP)
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases by a
current. V
is developed across a resistance between
DROOP
the VSP pin and the output voltage sense point.
VSN
VSP
RDRP
VSP
CSNS
To
VOUT+
CDRP
gm
RPH
+
CSP
CSN
CURRENT
Av=1
SENSE AMP
_
RCS
To
t
CCS
Rth
Figure 6. Droop Programming
Rth ) RCS
PH ) Rth ) RCS
V
DROOP + RDRP @ gm @
@ IOUT @ DCR
(eq. 5)
R
Programming IOUT
The loadline is programmed by choosing R
such that
DRP
The IOUT pin sources a current in proportion to the ILIM
sink current. The voltage on the IOUT pin should be scaled
with an external resistor to ground.
the ratio of voltage produced across R
is equal to the desired loadline.
to output current
DRP
R
PH ) Rth ) RCS
Rth ) RCS
Loadline
RDRP
+
@
(eq. 6)
gm @ DCR
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NCP81561
RPH
RCS
+
_
CSP
CURRENT
SENSE AMP
Av=1
CSN
TO
INDUCTOR
t
CCS
Rth
gm
IOUT
CURRENT
MONITOR
RIOUT
IOUT
Figure 7. VIOUT Programming
2.5 V
Rth)RCS
PH)Rth)RCS
RIOUT
+
(eq. 7)
gm @
@ IccMax @ DCR
R
Programming the DAC Feed-Forward Filter
The NCP81561 outputs a pulse of current from the VSN
pin upon each increment of the internal DAC when the 2−bit
VID is programmed to a higher voltage. A parallel RC
network inserted into the path from VSN to the output
voltage return sense point, VSS_SENSE, causes these
current pulses to temporarily decrease the voltage between
VSP and VSN. This causes the output voltage during a VID
change to be regulated slightly higher, in order to
compensate for the response of the Droop function to the
inductor current flowing into the charging output capacitors.
RFF sets the gain of the DAC feed-forward and CFF
provides the time constant to cancel the time constant of the
system per the following equations. C
capacitance of the system.
is the total output
OUT
DAC Feed-Forward Current
DAC
Feed-Forward
DAC
DAC
C
FF
To VOUT−
+
VSN
VSP
VSN
VSP
+
gm
R
FF
C
S
SNS
−
Figure 8. DAC Feed−Forward
Loadline @ COUT
1.35 @ 10*9
200
RFF
CFF
+
(nF)
(eq. 8)
RFF
+
(W)
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10
NCP81561
Programming the Current Limit
current limit resistor based on the equation shown below. A
capacitor can be placed in parallel with the programming
resistor to slightly delay activation of the latch if some
tolerance of short overcurrent events is desired.
The current limit threshold is programmed with a resistor
(R ) from the ILIM pin to ground. The current limit
ILIM
latches the single−phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold. Set the value of the
RPH
CSP
+
CURRENT
Av=1
CSN
RCS
SENSE AMP
_
TO
INDUCTOR
t
CCS
Rth
gm
ILIM
OVERCURRENT
PROGRAMMING
RILIM
OVERCURRENT
COMPARATORS
OCP
OCP REF
Figure 9. ILIM Programming
When an OVP fault occurs, the HG driver is turned off and
the LG driver is turned on to discharge the output. The
internal output voltage control DAC also begins to ramp
down at a rate of 1.6 mv/ms. The LG driver turns off when
VCSN drops below the dac voltage and continues to pulse
on so that VOUT tracks the internal DAC voltage down to
0 V. To exit an OVP fault condition, the EN pin must be
toggled low or the controller must be power cycled. OVP is
disabled during VID changes and when VOUT = 0 V.
1.3 V
Rth)RCS
PH)Rth)RCS
RILIM
+
(eq. 9)
gm @
@ IoutLimit @ DCR
R
Ultrasonic Mode
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
Input Under−Voltage Protection
The controller is protected against under−voltage on the
VCC and VRMP pins.
Over Current Protection (OCP)
The current limit is set with a resistor between the ILIM
pin and ground. The voltage on this pin is compared to the
Under Voltage Protection
ILIM threshold voltage (V ). If the voltage at the ILIM pin
CL
Under voltage protection will shut off the output similar
to OCP to protect against short circuits. The threshold is
specified in the parametric spec tables and is not adjustable.
exceeds the threshold voltage, the controller shuts down
immediately. To recover from an OCP fault, the EN pin or
V
CC
voltage must be cycled low. A 10 nf filter capacitor
must be added between the ILIM pin and GND (in parallel
with the ILIM resistor), to reduce the chance of spurious
overcurrent trips.
Over Voltage Protection (OVP)
The NCP81561 has an absolute OVP feature which
generates an OVP fault when the voltage on the CSN pin
(VCSN) pin exceeds 2.5 V.
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
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11
NCP81561
PACKAGE DIMENSIONS
QFN20 4x4, 0.5P
CASE 485EE
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
A
B
D
A3
EXPOSED Cu
MOLD CMPD
PIN ONE
REFERENCE
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
A1
2X
MILLIMETERS
DETAIL B
DIM MIN
MAX
1.00
0.05
0.10
C
C
ALTERNATE
A
A1
A3
b
0.80
0.00
CONSTRUCTIONS
2X
0.20 REF
0.10
0.25
0.35
TOP VIEW
L
L
D
4.00 BSC
D2
E
2.75
2.85
4.00 BSC
DETAIL B
A3
A
L1
E2
e
2.75
2.85
0.10
C
C
0.50 BSC
L
0.25
0.00
0.35
0.15
DETAIL A
L1
ALTERNATE
0.08
TERMINAL CONSTRUCTIONS
SEATING
PLANE
NOTE 4
A1
C
SIDE VIEW
SOLDERING FOOTPRINT*
D2
DETAIL A
20X L
4.30
6
20X
0.50
11
2.95
E2
1
1
20
20X b
e
2.95
4.30
0.10 C A B
0.05
C
NOTE 3
BOTTOM VIEW
PKG
OUTLINE
20X
0.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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