NCV7428MWL5R2G [ONSEMI]
System Basis Chip with Integrated LIN and Voltage Regulator;
| 型号： | NCV7428MWL5R2G |
| 厂家： | 
ONSEMI |
| 描述： | System Basis Chip with Integrated LIN and Voltage Regulator 电信 光电二极管 电信集成电路 |
| 文件： | 总19页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7428
System Basis Chip with
Integrated LIN and Voltage
Regulator
Description
NCV7428 is a System Basis Chip (SBC) integrating functions
typically found in automotive Electronic Control Units (ECUs).
NCV7428 provides and monitors the low−voltage power supply for
the application microcontroller and other loads and includes a LIN
transceiver.
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1
1
Features
SOIC−8
DFN8
• Control Logic
D SUFFIX
CASE 751AZ
MW SUFFIX
CASE 506DG
♦ Ensures safe power−up sequence and the correct reaction to
different supply conditions
♦ Controls mode transitions including the power management and
bus wakeup treatment
♦ Generates reset
MARKING DIAGRAMS
8
1
1
NV7428xx
• 3.3 V or 5 V V
Supply depending on the Version from a
Low−drop Voltage Regulator
OUT
NV7428xx
ALYW G
ALYWG
G
G
♦ Can deliver up to 70 mA with accuracy of 2%
♦ Supplies typically the ECU’s microcontroller
♦ Undervoltage detector with a reset output to the supplied
microcontroller
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• LIN Transceiver
♦ LIN2.x and J2602 compliant
♦ TxD dominant timeout protection
♦ Transceiver mode controlled by dedicated input pin
(Note: Microdot may be in either location)
• Protection and Monitoring Functions
♦ Thermal shutdown protection
♦ Load dump protection (45 V)
PIN ASSIGNMENT
♦ LIN Bus pin protected against transients in an automotive
environment
8
7
6
5
1
2
3
4
V
V
S
OUT
♦ ESD protection level for LIN and V > 8 kV
S
EN
GND
LIN
RSTN
TxD
• Wettable Flank Package for Enhanced Optical Inspection
Quality
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
RxD
(Top View)
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 17 of this data sheet.
Typical Applications
• Automotive
• Industrial Networks
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2016 − Rev. 5
NCV7428/D
NCV7428
Block Diagram
VOUT
VS
NCV7428
REF
V−reg
OSC
VOUT
VS
VOUT
Undervoltage
Detection
RSTN
EN
Thermal
Shutdown
Control Logic
VS
Wakeup
Detection
VOUT
LIN Wakeup
RxD
TxD
Receiver
LIN
LIN Active
VOUT
Driver &
Slope
Control
Timeout
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
Pin Type
Pin Function
1
2
V
Battery supply input
Principle power supply of the device
Input of the LIN block enable signal
S
EN
LV LIN enable input;
internal pull−down
3
4
5
6
7
GND
LIN
Ground connection
LIN bus interface
Ground connection
LIN bus line
RxD
TxD
LV digital output; push−pull
Output of data received on LIN bus
Input of the data to be transmitted from LIN bus
System reset
LV digital input; internal pull−up
RSTN
LV digital output;
open drain; internal pull−up
8
V
LV supply output
Exposed Pad
Output of the 5 V or 3.3 V/70 mA low−drop regulator (for the MCU)
Connect to GND or leave floating
OUT
EP
EP
NOTE: (LV = Low Voltage; HV = High Voltage)
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NCV7428
Application Information
(MASTER)
(SLAVE)
ECU1
ECU2
DREV
DREV
CVS
CVOUT
CVS
CVOUT
VBAT
VBAT
VCC
VCC
VS
VOUT
VS
VOUT
DPU_LIN
RSTN
EN
RSTN
EN
RPU_LIN
MCU
MCU
LIN
TxD
RxD
LIN
TxD
RxD
LIN
LIN
CLIN_M
CLIN_S
GND
GND
GND
GND
GND
GND
KL30
LIN−BUS
KL31
Figure 2. Example Application Diagram
External Components
Overview of external components from application schematic in Figure 2 is given in Table 2 together with their recommended
or required values.
Table 2. EXTERNAL COMPONENTS OVERVIEW
Component
Name
Description
Value
Note
D
Reverse polarity protection diode
parameters application−specific;
e.g. 0.5 A / 50 V
required values and types
REV
depend on the V
load
OUT
and the application needs
C
Filtering capacitor for the battery input
recommended >100 nF ceramic
VS
C
Voltage regulator output filtering and
stabilization capacitor
> 1.8 mF, ESR < 7 W
VOUT
D
R
Master node Pull−up diode on LIN line
Master node Pull−up resistor on LIN line
Filtering capacitor on LIN line (Master node)
required only for master
LIN node
PU_LIN
PU_LIN
1 kW nominal, ≥500 mW
C
typically 1 nF
optional; is function of the
entire LIN network
LIN_M
C
Filtering capacitor on LIN line (Slave node)
Pull−up resistor at RSTN pin
typically 100 pF – 220 pF
optional; is function of the
entire LIN network
LIN_S
R
recommended 10 kW nominal
optional; depends on
application needs
PU_RSTN
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NCV7428
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−45
−0.3
−0.3
−40
−40
−55
Max
45
6
Units
V
V
S
Maximum DC voltage at V pin
S
V
OUT
Maximum voltage at V
pin
V
OUT
V
LIN
Maximum voltage at LIN bus pin
45
45
V
V
Maximum voltage at digital input pins (TxD, EN)
Maximum voltage at digital output pins (RxD, RSTN)
Ambient temperature range
V
Dig_IO_inputs
V
V
+0.3
OUT
V
Dig_IO_outputs
T
AMB
+125
+170
+150
°C
°C
°C
kV
T
J
Junction temperature range
T
STG
Storage temperature range
V
ESD
System ESD at pins VS, LIN as per IEC 61000−4−2: 330 W / 150 pF
≥
14
(Verified by external test house)
Human body model at pins VS, LIN stressed towards GND with 1500 W / 100 pF
Human body model at all pins as per JESD22−A114 / AEC−Q100−002
Charge device model at all pins as per JESD22−C101 / AEC−Q100−011
Machine model; (200 pF; 0.75 mH; 10 W) as per JESD22−A115 / AEC−Q100−003
≥
8
4
kV
kV
V
≥
≥
500
200
V
MSL
Moisture Sensitivity Level
SOIC
DFN
2
1
−
T
SLD
Lead temperature Soldering − Reflow (SMD styles only), Pb−Free (Note 1)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. OPERATING RANGES
Symbol
Parameter
Min
5.5
4
Max
28
Units
V
V
S
VS operating voltage for parametric operation (Note 2)
VS operating voltage for limited operation (Note 2)
28
V
V
Regulated voltage at V
Regulated voltage at V
supply output for 5 V versions
supply output for 3.3 V versions
4.9
3.234
70
0
5.1
V
OUT5
OUT
OUT
V
OUT33
I
VOUT
3.366
V
Current delivered by the V
regulator
mA
V
OUT
V
Operating voltage at LIN bus pin
V
S
LIN
Dig_IO_inputs
V
Operating voltage at digital input pins (TxD, EN)
Operating voltage at digital output pins (RxD, RSTN)
0
5.5
V
V
0
V
OUT
V
Dig_IO_outputs
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Below 5.5 V at V pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time
S
specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 28 V at V pin, LIN communication is
S
operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 28 V, LIN pull−up resistor
must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.
Table 5. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
R
R
125
75
°C/W
°C/W
q
q
JA
JA
Thermal Characteristics, DFN−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
R
R
133
55
°C/W
°C/W
q
q
JA
JA
3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
4. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
5. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.
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NCV7428
Definitions
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 4, unless stated
otherwise. All voltages are referenced to GND (Pin 3). Positive currents flow into the respective pin.
Table 6. DC CHARACTERISTICS (V = 5.5 V to 28 V; T = −40°C to +150°C; Bus Load = 500 W (V to LIN); unless otherwise
S
J
S
specified. Typical values are given at V = 12 V and T = 25°C, unless otherwise specified.)
S
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY MONITORING
V
V
threshold for the power−up
V
V
V
V
rising
falling
3.3
2.2
4
3
V
V
V
V
V
V
S_PORH
S
S
of the circuit
V threshold for the Shutdown
S
V
S_PORL
S
of the circuit
V
V
OUT
monitoring threshold
falling
4.55
2.97
4.75
3.135
OUT_RES_5
OUT
OUT
NV7428−5
V
V
OUT
monitoring threshold
falling
OUT_RES_33
NV7428−3
V
V
OUT
monitoring threshold
0.1
OUT_RES_hys5
hysteresis for NV7428−5
V
V
OUT
monitoring threshold
0.06
OUT_RES_hys33
hysteresis for NV7428−3
CURRENT CONSUMPTION
I
V
V
supply current
LIN Active, LIN bus recessive
Standby mode; LIN Wakeup,
1.8
40
mA
VS_LIN_Active_rec
S
I
supply current (Note 8)
25
12
mA
VS_LIN_Wakeup
S
LIN bus recessive; I
= 0 mA
VOUT
V
S
= 13.5 V, T < 105°C
J
I
V
S
supply current (Note 8)
Sleep mode; LIN Wakeup, LIN bus
recessive; V off, V < 0.5 V
25
mA
VS_Sleep
OUT
OUT
V
S
= 13.5 V, T < 105°C
J
V
OUT
REGULATOR
V
V
regulator output voltage
V
0 < I
regulator active,
4.9
3.234
4.85
3.201
70
5
5.1
V
V
V
V
OUT_5
OUT
OUT
(Note 6)
< 70 mA, Static
VOUT
regulation, V = 5.5 V to 28 V
S
V
V
OUT
regulator output voltage
V regulator active,
OUT
0 < I
regulation, V = 4.5 V to 28 V
3.3
5
3.366
5.15
OUT_33
(Note 6)
< 70 mA, Static
VOUT
S
V
V
OUT
regulator output voltage
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
OUT_5_EMC
under EMC (Note 8)
V
V
OUT
regulator output voltage
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
3.3
120
3.399
OUT_33_EMC
under EMC (Note 8)
I
V
OUT
current limitation
V regulator active;
OUT
current flowing to V
350
0.55
400
mA
V
LIM_VOUT
load
OUT
V
I
Drop−out voltage between V
and V
5.5 V < V < 40 V;
S
DROP_VOUT
SINK_VOUT
S
I
= 70 mA
OUT
VOUT
V
OUT
sink current
V
OUT
regulator active, current
100
1.8
240
10
mA
mF
flowing into the V
pin
OUT
C
V
OUT
regulator filtering
Equivalent series resistance < 7 W
VOUT
capacitance (Note 9)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used V
and V
needs to be taken into account.
OUT_5_EMC
OUT_33_EMC
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10.The voltage drop in Normal mode between LIN and V pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
S
at the switch is negligible. See Figure 1.
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NCV7428
Table 6. DC CHARACTERISTICS (V = 5.5 V to 28 V; T = −40°C to +150°C; Bus Load = 500 W (V to LIN); unless otherwise
S
J
S
specified. Typical values are given at V = 12 V and T = 25°C, unless otherwise specified.)
S
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LIN TRANSMITTER
V
LIN dominant output voltage
LIN dominant output voltage
LIN recessive output voltage
Short circuit current limitation
Internal Pull−up Resistance
Capacitance at pin LIN (Note 8)
TxD = Low; V = 7.3 V
1.2
2.0
V
V
LIN_dom_LoSup
S
V
TxD = Low; V = 18 V
S
LIN_dom_HiSup
V
TxD = High; I
= 10 mA (Note 10)
V
S
– 1.5
V
S
V
LIN_REC
LIN
I
V
LIN
= V = 18 V
40
20
200
47
mA
kW
pF
LIN_lim
S
R
LIN Normal or Receive−only mode
33
20
slave
C
30
LIN
LIN Receiver
V
Bus voltage for Dominant state
Bus voltage for Recessive state
Receiver threshold
0.4
V
V
V
bus_dom
S
S
S
V
0.6
0.4
bus_rec
V
LIN bus going from Recessive to
Dominant
0.6
0.6
rec_dom
V
Receiver threshold
LIN bus going from Dominant to
Recessive
0.4
V
S
rec_rec
V
Receiver center voltage
Receiver hysteresis
(V
+ V
)/2
0.475
0.05
−1
0.525
0.175
V
V
rec_cnt
rec_dom
rec_rec
S
V
V
− V
rec_hys
rec_rec rec_dom
S
I
LIN output current,
Bus in dominant state
LIN Active Mode, Driver Off;
V = 12 V, V = 0 V
S
mA
mA
mA
LIN_off_dom
LIN
I
LIN output current,
Bus in dominant state
LIN Wakeup Mode;
V = 12 V, V = 0 V
S
−20
−15
−2
1
LIN_off_dom_wake
LIN
I
LIN output current,
Driver Off; V < 18 V;
S
LIN_off_rec
Bus in recessive state
V
S
V
S
V
S
< V
< 18 V
LIN
I
LIN current with missing GND
= GND = 12 V; 0 < V
< 18 V
−1
1
5
mA
LIN_no_GND
LIN
I
LIN current with missing V
= GND = 0 V; 0 < V < 18 V
LIN
mA
LIN_no_VBB
S
PIN EN
V
Low−level input voltage
High−level input voltage
−0.3
2
0.8
5.5
V
V
IL_EN
IH_EN
V
R
Pull−down resistance to GND
55
100
185
kW
pulldown_EN
PIN TxD
V
Low−level input voltage
High−level input voltage
−0.3
2
0.8
5.5
185
1
V
V
IL_TxD
IH_TxD
V
R
Pull−up resistance to V
55
−1
100
0
kW
mA
pullup_TxD
OUT
I
Leakage current
V
TxD
= V
= 5.5 V
leak_TxD
OUT
PIN RSTN
I
Low−level output driving current
Low−level output voltage
V
V
= 4 V to 28 V; V
= 0.4 V
RSTN
4
30
mA
OL_RSTN
S
V
= 2 V to 4 V; V
= 0 V to
0.1
V
OUT
OL_RSTN
S
OUT
5.5 V; I
= 100 mA
RSTN
V
S
< 2 V; V
= 1 V to 5.5 V;
0.1
V
OUT
OUT
I
= 100 mA
RSTN
R
Pull−up resistance to V
55
100
185
kW
pullup_RSTN
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used V
and V
needs to be taken into account.
OUT_5_EMC
OUT_33_EMC
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10.The voltage drop in Normal mode between LIN and V pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
S
at the switch is negligible. See Figure 1.
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NCV7428
Table 6. DC CHARACTERISTICS (V = 5.5 V to 28 V; T = −40°C to +150°C; Bus Load = 500 W (V to LIN); unless otherwise
S
J
S
specified. Typical values are given at V = 12 V and T = 25°C, unless otherwise specified.)
S
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PIN RSTN
V
V
level guaranteeing Low level
Shutdown mode; Low level guar-
2
V
S_DigOut_Low
S
at RSTN pin
anteed for V > V
S S_DigOut_Low
PIN RxD
I
Low−level output driving current
High−level output driving current
V
V
= 0.4 V
0.4
mA
mA
OL_RXD
RxD
I
= V
− 0.4 V
−0.16
200
OH_RXD
RXD
OUT
THERMAL SHUTDOWN
Junction temperature for ther-
T
J_SD
160
180
10
°C
°C
mal Shutdown
T
Thermal Shutdown hysteresis
J_SD_hys
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used V
and V
needs to be taken into account.
OUT_5_EMC
OUT_33_EMC
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10.The voltage drop in Normal mode between LIN and V pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
S
at the switch is negligible. See Figure 1.
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NCV7428
Table 7. AC CHARACTERISTICS (V = 5.5 V to 28 V; T = −40°C to +150°C; unless otherwise specified. For the transmitter
S
J
parameters, the following bus loads are considered: L1 = 1 kW / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF)
Symbol
LIN TRANSMITTER
D1
Parameter
Conditions
Min
Typ
Max
Unit
Duty Cycle 1 =
/ (2 x t
TH
TH
= 0.744 x V
REC(max)
= 0.581 x V
DOM(max) S
0.396
0.5
S
t
)
BIT
BUS_REC(min)
t
V
= 50 ms
= 7 V to 18 V
BIT
S
D2
D3
D4
Duty Cycle 2 =
/ (2 x t
TH
TH
= 0.422 x V
0.5
0.417
0.5
0.581
0.5
REC(min)
= 0.284 x V
DOM(min) S
= 50 ms
S
t
)
BUS_REC(max)
BIT
t
BIT
V
S
= 7.6 V to 18 V
Duty Cycle 3 =
/ (2 x t
TH
TH
= 0.778 x V
S
REC(max)
= 0.616 x V
DOM(max) S
t
)
BUS_REC(min)
BIT
t
= 96 ms
BIT
V
S
= 7 V to 18 V
Duty Cycle 4 =
/ (2 x t
TH
TH
= 0.389 x V
0.590
REC(min)
= 0.251 x V
DOM(min) S
S
t
)
BUS_REC(max)
BIT
t
V
= 96 ms
= 7.6 V to 18 V
BIT
S
t
LIN falling edge normal slope
Normal Mode; V = 12 V
22.5
22.5
4
ms
ms
ms
ms
ms
ms
fallNS
S
t
LIN rising edge normal slope
Normal Mode; V = 12 V
S
riseNS
t
LIN slope symmetry normal slope
LIN falling edge low slope (Note 12)
LIN rising edge low slope (Note 12)
Normal Mode; V = 12 V
−4
0
symNS
S
t
Normal Mode; V = 12 V
45
fallLS
S
t
Normal Mode; V = 12 V
45
riseLS
tx_prop_down
S
t
Propagation Delay of TxD to LIN.
TxD high to low
(Note 11)
10
t
Propagation Delay of TxD to LIN.
TxD low to high
(Note 11)
10
24
ms
tx_prop_up
t
TxD dominant timeout
TxD = Low; LIN dominant
timeout enabled
7
13
ms
TxD_timeout
LIN RECEIVER
t
Propagation delay of receiver falling
edge
0.1
0.1
−2
6
6
ms
ms
ms
ms
rec_prop_down
t
Propagation delay of receiver rising
edge
rec_prop_up
t
Propagation delay symmetry
T
T
−
2
rec_sym
rec_prop_down
rec_prop_up
t
Dominant duration for wakeup
LIN in wakeup mode
30
80
150
LIN_wake
MODE TRANSITIONS AND TIMEOUTS
t
Input signal synchronization delay
5
15
25
40
55
ms
ms
synch
synch_action
t
Delay from the asynchronous input
pin change to the system state
change
11
t
Low power mode selection delay
RSTN pulse extension
17
2
30
5
55
10
55
ms
ms
ms
modsel_set
t
reset
VOUT_RES_filt
t
Undervoltage detection filter time
11
25
11. Values based on design and characterization. Not tested in production.
12.For low slope versions only (NV7428L5 and NV7428L3)
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NCV7428
Functional Description
VS Supply Input
LIN Operating Modes
V pin of NCV7428 is typically connected to the car
battery through a reverse−protection diode and can be
exposed to all relevant automotive disturbances (ISO7637
In LIN Active mode the transceiver can transmit and
receive data via LIN bus with speed up to 20 kBaud for
normal slope mode and 10 kBaud/s for low slope version.
The transmit data stream of the LIN protocol is present on
the TxD pin and converted by the transmitter into a LIN bus
signal with controlled slew rate to minimize EMC emission.
The receiver consists of the comparator that has a threshold
with hysteresis in respect to the supply voltage and an input
filter to remove bus noise. The LIN output is pulled HIGH
via an internal pull−up resistor (typ. 30 kW). For master
applications, it is needed to put an external resistor (typ.
S
pulses, system ESD ...). V supplies mainly the integrated
S
LIN transceiver. Filtering capacitors should be connected
between V and GND.
S
During power−up of the battery supply, V pin must reach
S
V
level in order for the circuit to become functional
S_PORH
– the internal state machine is initiated and the V
OUT
regulator is activated. The circuit remains functional until
V falls back below V
level, when the device enters
S
S_PORL
the Shutdown mode.
1 kW) with a serial diode between LIN and V . The mode
S
selection is done by EN = High.
VOUT Low−drop Voltage Regulator
The application low−voltage supply is provided by an
integrated low−drop voltage regulator delivering a 5 V or
The transmission is only initiated with the TxD falling
edge in LIN Active mode. Entering this mode with TxD
already Low will not lead to transmitting bus Dominant
signal.
When leaving Normal mode (EN pin falling edge), the
transmitter is deactivated immediately.
The LIN Wakeup mode can be entered if the EN pin is
Low. The LIN receiver stays active to be able to detect a
remote wake−up via bus. The LIN transmitter is disabled
and the slave internal termination resistor of 30 kW between
3.3 V output V
. It is able to deliver up to 70 mA with
OUT
given precision and is primarily intended to supply the
application microcontroller unit (MCU) and related 5 V or
3.3 V loads (e.g. its own MCU−related digital inputs/
outputs). An external capacitor needs to be connected on
V
OUT
pin in order to ensure the regulator’s stability and to
filter the disturbances caused by the connected loads.
All low−voltage digital pins are related to V
.
OUT
LIN and V is disconnected in order to minimize current
S
consumption. Only a pull−up current source between Vs and
LIN is active. The valid LIN wakeup event causes driving
RxD Low until EN pin is pulled High.
A Wakeup pattern that is initiated in LIN Active mode and
ends in LIN Wakeup mode is also considered a valid Wakeup
event.
The LIN Wakeup mode is also forced if the device enters
to the Sleep operating mode.
The LIN Off mode provides extreme low current
consumption, LIN transceiver is fully deactivated. Pin RxD
LIN Transceiver
NCV7428 integrates on−chip LIN transceiver interface
between physical LIN bus and the LIN protocol controller.
This LIN physical layer is compatible to LIN2.x and
J2602 specifications.
NCV7428 LIN2.2 compliant physical layer can be
combined on the network with all previous LIN physical
layers.
NCV7428 LIN transceiver consists of a transmitter,
receiver and wakeup detector. The LIN transceiver can be
connected to the bus line via LIN pin, and to the digital
control through pins TxD and RxD. The functional mode of
the LIN transceiver depends on the operating mode and on
EN pin state – see Figure 3. The LIN transceiver is supplied
stays High (as long as V
on TxD is ignored.
is provided) and logical level
OUT
The bus pin is internally pulled to V with a current source
S
(thus limiting V consumption in case of a permanent LIN
S
short to GND).
This mode is entered when NCV7428 is in Shutdown
directly from the V pin.
S
mode (V < V
) or in Thermal Shutdown mode (T >
S
S_PORL
J
T
).
J_SD
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9
NCV7428
LIN Mode
LIN Off
LIN Wakeup
LIN Active
Bus Pin
Pull−up
W
30 k Resistor
Current Source
recessive
LIN
dominant
TxD
RxD
EN
tTxD_timeout
LIN Wakeup
detected
LIN Active
mode set
Figure 3. LIN Modes
< tLIN_wake
tLIN_wake
recessive
LIN
dominant
RxD
EN
LIN Wakeup
detected
LIN Active
mode restored
Figure 4. LIN Wakeup Detection
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10
NCV7428
Operating Modes
The principal operating modes of NCV7428 are shown in Figure 5 and described in the following paragraphs.
Any mode
(except for shutdown)
Any mode
VS < VS_PORL
TJ > TJ_SD
THERMAL
SHUTDOWN
SHUTDOWN
−VOUT: off
−VOUT: off
VS power−up
−RSTN: Low
−RSTN: Low
−LIN: Wakeup mode
−RxD: Low after Wakeup/
pulled to VOUT otherwise
−LIN: Off mode
−RxD: pulled to V
OUT
VS > VS_PORH
and TJ < TJ_SD
TJ < TJ_SD
RESET
−VOUT: on
−RSTN: Low
−LIN: Wakeup mode
−RxD: Low after Wakeup/
High otherwise
STANDBY
NORMAL
EN= 1
−VOUT: on
−RSTN: High
−LIN: Wakeup mode
−RxD: Low after Wakeup/
High otherwise
−VOUT: on
−RSTN: High
−LIN: Active mode
−RxD: Received LIN Data
EN= 0
and
TxD = 1
LIN_EN= 0
and
TxD = 0
LIN wakeup
or
EN = 1
SLEEP
−VOUT: off
−RSTN: Low
−LIN: Wakeup mode
−RxD: pulled to V
OUT
Figure 5. Operating Modes
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11
NCV7428
Shutdown Mode
Normal Mode
The Shutdown mode is a passive state, in which all
NCV7428 resources are inactive. The Shutdown mode
provides a defined starting point for the circuit in case of
supply undervoltage, thermal Shutdown or the first supply
connection.
Normal mode is entered from Standby mode after a host
request – driving EN pin High (Figure 9), or if EN pin is
High when leaving Reset mode – t
(Figure 8).
time elapsed
reset
LIN transceiver is in Active mode. V
RSTN remains High.
is kept on. Pin
OUT
On−chip power−supply V
is switched off and the LIN
OUT
pin remains passive so that it does not disturb the
communication of other nodes connected to the LIN bus.
Standby Mode
Standby mode is entered from Normal mode after host
request – EN pin falling edge followed by TxD pin High.
RxD pin stays pulled to V . No wakeups can be detected.
OUT
RSTN pin is forced Low – RSTN Low level is guaranteed
for V supply above V
TxD is sampled t
+ t
after EN edge (Figure 9).
synch
modesel
.
S_DigOut_Low
S
Standby mode is also entered if EN pin is Low when leaving
Reset mode – t time elapsed (Figure 7).
The Shutdown mode is entered asynchronously whenever
the V level falls below the power−on−reset level V
reset
.
S_PORL
S
LIN transceiver is in Wakeup mode – RxD pin is latched
Low after valid Wakeup recognition until Normal mode is
The Shutdown mode is left only when the V supply
S
exceeds the high power−on−reset level V
while
S_PORH
requested. V
is kept active. Pin RSTN remains High.
OUT
junction temperature is below T
. When exiting the
J_SD
Shutdown mode, NCV7428 always enters the Reset mode.
Sleep Mode
Sleep mode can be only entered from Normal mode after
a host request – EN pin falling edge followed by TxD pin
RESET Mode
The Reset mode is a transient mode providing a defined
RSTN pulse for the application microcontroller.
Low. TxD is sampled t
(Figure 10).
+ t
after EN pin edge
synch
modesel
V
OUT
supply is kept active. The LIN pin is passive so that
V
OUT
regulator is switched off, LIN transceiver is in the
it does not disturb the communication of other nodes
connected to the bus. RxD pin is High if no wakeup was
detected, RxD Low level indicates pending LIN wakeup.
Pin RSTN is forced Low.
Reset mode will be entered as a consequence of one of the
following events:
• Shutdown mode is exited
• Thermal Shutdown mode is exited
Wakeup mode.
If LIN wakeup is detected or EN goes High, Reset mode
is entered. LIN wakeup is signaled by RxD, which remains
Low until Normal mode is restored (EN is High).
Thermal Shutdown
The device junction temperature is monitored in order to
avoid permanent degradation or damage of the chip.
Junction temperature exceeding the Shutdown level T
• V
voltage falls below V
level
J_SD
OUT
OUT_RES
puts the chip into Thermal Shutdown mode.
• LIN wakeup or EN = High was detected in Sleep mode
In Thermal Shutdown mode, V
regulator is switched
OUT
Normally, the Reset mode is left when V voltage is
OUT
off. LIN transceiver is in Wakeup mode and can detect bus
Wakeup. RxD pin stays pulled to V or is driven Low
above V
threshold and defined time t
elapses.
OUT_RES
reset
OUT
The RSTN pin is internally released to High and the chip
then goes to the Normal or Standby mode, depending on EN
state.
after valid Wakeup recognition. RSTN pin is pulled low. The
mode is automatically left only when the junction cools
down below the T
threshold.
J_SD
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12
NCV7428
VS
VS
VOUT
tVOUT_RES_filt
tVOUT_RES_filt tVOUT_RES_filt
< tVOUT_RES_filt
VOUT
VOUT_RES
VS_PORH
treset
treset
RSTN
EN
Operating
mode
Shutdown
Reset
Standby
Reset
Standby
Figure 6. VOUT Regulator Voltage Monitoring
EN
ignored
TxD
ignored
RxD
LIN wakeup indication
treset
RSTN
Operating
mode
Reset
Standby
RSTN pulse released
EN sampled
VOUT > VOUT_RES
Figure 7. Operating Modes, Transition from Reset to Standby Mode
www.onsemi.com
13
NCV7428
ignored
EN
TxD
RxD
ignored
LIN wakeup indication
treset
tsynch_action
RSTN
Operating
mode
Reset
Normal
RSTN pulse released
EN sampled
Mode change
LIN wakeup flag cleared
VOUT > VOUT_RES
Figure 8. Operating Modes, Transition from Reset to Normal Mode
EN
TxD
RxD
ignored
ignored
LIN wakeup indication
RSTN
Operating
mode
Normal
Standby
Normal
tsynch
tmodsel_set
tsynch_action
LIN transmission blocked
TxD sampling
Figure 9. Operating Modes, Transition from Normal to Standby Mode
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14
NCV7428
EN
TxD
RxD
ignored
ignored
LIN wakeup
indication
VOUT OFF
RSTN
Operating
mode
Normal
Sleep
Reset
tsynch
tmodsel_set
tsynch_action
LIN transmission blocked
TxD sampling
Figure 10. Operating Modes, Transition from Normal to Sleep Mode
tBIT
tBIT
TxD
LIN
50%
t
tBUS_dom(max)
tBUS_rec(min)
THREC(max)
THDOM(max)
Thresholds of
receiving node 1
THREC(min)
THDOM(min)
Thresholds of
receiving node 2
t
tBUS_dom(min)
tBUS_rec(max)
Figure 11. Definition of LIN Duty Cycle Parameters
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15
NCV7428
LIN
100%
60%
40%
60%
40%
0%
t
tfall
trise
Figure 12. Definition of LIN Edge Parameters
TxD
tBIT
tBIT
50%
t
LIN
VS
60% VS
40% VS
t
ttx_prop_down
ttx_prop_up
Figure 13. Definition of LIN Transmitter Timing Parameters
LIN
VS
60% VS
40% VS
t
t
trec_prop_down
trec_prop_up
RxD
50%
Figure 14. Definition of LIN Receiver Timing Parameters
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16
NCV7428
ORDERING INFORMATION
Part Number
†
Description
Marking
NV7428−5
NV7428−3
Package
Shipping
NCV7428D15R2G
LIN transceiver with 5 V regulator
LIN transceiver with 3.3 V regulator
NCV7428D13R2G
SOIC−8
(Pb−Free)
NCV7428D1L5R2G
LIN transceiver with 5 V regulator,
low slope LIN
3000 / Tape & Reel
NV7428L5
NV7428L3
NCV7428D1L3R2G
LIN transceiver with 3.3 V regulator,
low slope LIN
NCV7428MW5R2G
NCV7428MW3R2G
NCV7428MWL5R2G
LIN transceiver with 5 V regulator
LIN transceiver with 3.3 V regulator
NV7428−5
NV7428−3
DFN8
Wettable Flanks
(Pb−Free)
LIN transceiver with 5 V regulator,
low slope LIN
3000 / Tape & Reel
NV7428L5
NV7428L3
NCV7428MWL3R2G
LIN transceiver with 3.3 V regulator,
low slope LIN
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
NCV7428
PACKAGE DIMENSIONS
SOIC 8
CASE 751AZ
ISSUE B
NOTES 4&5
0.10 C D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
455CHAMFER
D
NOTE 6
h
D
A
2X
H
8
5
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
0.10 C D
NOTES 4&5
E
E1
L2
SEATING
L
C
PLANE
DETAIL A
1
4
0.20 C D
8X b
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
B
M
0.25
C A-B D
NOTE 6
MILLIMETERS
TOP VIEW
NOTES 3&7
DIM MIN
MAX
1.75
0.25
---
DETAIL A
A
A1
A2
b
---
0.10
1.25
0.31
0.10
A2
NOcTE 7
0.10 C
0.51
0.25
c
D
4.90 BSC
A
E
6.00 BSC
3.90 BSC
1.27 BSC
e
END VIEW
SEATING
PLANE
E1
e
C
A1
SIDE VIEW
NOTE 8
h
0.25
0.40
0.41
1.27
L
L2
0.25 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.76
8X
1.52
7.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
NCV7428
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506DG
ISSUE A
L
NOTES:
A
B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
MILLIMETERS
E
PIN ONE
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
REFERENCE
A
2X
A3
b
0.20 REF
0.10
C
0.25
0.35
D
3.00 BSC
D2 2.30
2.50
2X
0.10
C
C
TOP VIEW
E
3.00 BSC
E2 1.50
1.70
A
e
K
L
0.65 BSC
0.30 TYP
0.35 0.45
A3
0.05
0.05
C
RECOMMENDED
SEATING
PLANE
NOTE 4
C
A1
SIDE VIEW
D2
SOLDERING FOOTPRINT*
8X
0.60
2.56
DETAIL A
1
4
8X
L
3.30
1.70
E2
K
1
8
5
08.4X0
8X b
e/2
0.65
PITCH
0.10 C A B
DIMENSIONS: MILLIMETERS
e
NOTE 3
C
0.05
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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