NCV7429DE5R2G_技术文档

NCV7429

System Basis Chip with

LIN, LS and HS Switches

Description

The NCV7429 is a monolithic LIN System-Basis-Chip with

enhanced feature set useful in Automotive Body Control systems.

Besides the LIN bus interface the IC features a 5 V voltage regulator,

high-side and low-side switches to control LEDs and relays, and

supervision functionality like a window watchdog. This allows

a highly integrated solution by replacing external discrete components

while maintaining the system flexibility. As a consequence, the board

space and ECU weight can be minimized.

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TSSOP−20 EP

CASE 948AB

Features

MARKING DIAGRAM

• Main Supply Functional Operating Range from 5 V to 28 V

• Main Supply Parametrical Operating Range 6 V to 18 V

• LIN Physical Layer According to ISO 17987−4 (backwards

compatible to LIN 1.3, LIN 2.x) and SAE J2602

• Power Management Through Operating Modes: Normal, Standby,

Sleep and Flash

NV74

29−5

ALYWG

G

• Software Development Mode for Software Debugging

• Low Drop Voltage Regulator VR1: 5 V/150 mA, 2%

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

• One Wake-up Input, e.g. for Contact Monitoring

• Wake-up Logic with Cyclic Contact Monitoring

• Wake-up Source Recognition

• Independent PWM Functionality for All Outputs

(Integrated PWM Registers)

(Note: Microdot may be in either location)

PIN ASSIGNMENT

• Window Watchdog with Programmable Times

• 2x Low-side Driver (typ. 1.5 W) with Over-load Protection

and Active Clamp; e.g. for Relays

• 3x High-side Driver (typ. 5 W) with Over- and Under-load Detection;

e.g. for LED’s and Switches

1

20

GND1

SWDM

NRES

VR1

LS2

LS1

GND2

LIN

VS

VS_OUT

OUT1

OUT2

OUT3/FSO

WU

TxDL

RxDL/INTN

SDI

NCV7429

(Top View)

• 24-bit SPI Interface

• Protection against Short Circuit, Over-voltage and Over-temperature

• TSSOP−20 EP Package

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

SDO

SCLK

CSN

• These Devices are Pb-Free, Halogen Free/BFR Free and are

ORDERING INFORMATION

RoHS Compliant

†

Device

Package

Shipping

Typical Applications

NCV7429DE5R2G TSSOP−20

(Pb-Free)

2500 / Tape &

Reel

• De-centralized Door Electronic Systems

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

1

Publication Order Number:

March, 2017 − Rev. 0

NCV7429/D

NCV7429

BLOCK DIAGRAM

16

15

NCV7429

VS

19

LS1

LS2

Low−Side

4

VR1

5 V / 150 mA

Protection:

Short circuit

Open load

Over−temperature

Under/over voltage

20

Low−Side

3

NRES

Watchdog

Logic

VS_OUT

CONTROL_0

CONTROL_1

CONTROL_2

CONTROL_3

10

9

High−Side

14

13

12

11

CSN

SCLK

SDI

OUT1

STATUS _0

STATUS _1

STATUS _2

7

VS_OUT

PWM_1/2

PWM_3

8

High−Side

SDO

OUT2

ROM

SPI

VS_OUT

2

High−Side

SWDM

OUT3/FSO

WU

VS_OUT

Timer1/2

PWM

VS

Local

wakeup

detector

5

6

TxDL

LIN

RxDL/INTN

17

1

18

Figure 1. Block Diagram

Table 1. PIN DESCRIPTION

Pin No.

Pin Name

GND1

Pin Type

Description

1

2

Ground

Ground connection

SWDM

HV Digital Input with

Pull-down

Software development mode entry input

3

NRES

Digital Open-drain Output

with Internal Pull-up

Reset signal to the MCU

2%, 150 mA

4

5

6

7

8

VR1

TxDL

5 V Regulator Output

Digital Input with Pull-up

Digital Push-pull Output

Digital Input with Pull-down

Transmitter data input of the LIN transceiver

Receiver output of the LIN transceiver/Interrupt output

SPI data input

RxDL/INTN

SDI

SDO

Digital Push-pull Output,

Tristate

SPI data output

9

SCLK

CSN

Digital Input with Pull-down

Digital Input with Pull-up

HV Input

SPI clock input

10

11

12

13

SPI chip select input

WU

Voltage-sense input (threshold typ. VS_OUT/2), switched pull-up/down

Resistive loads, Ron 5 W typ, Ilim > 140 mA / FSO output

Resistive loads, Ron 5 W typ, Ilim > 140 mA

OUT3/FSO

OUT2

HS Driver

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2

NCV7429

Table 1. PIN DESCRIPTION (continued)

Pin No.

14

Pin Name

OUT1

VS_OUT

VS

Pin Type

Description

HS Driver

Resistive loads, Ron 5/20 W typ, Ilim > 140/35 mA, two configurations

Power-supply of the high-side drivers OUT1−3 and WU input

Principle power-supply of the device

15

Battery Supply Input

LIN Bus Interface

Ground

16

17

LIN

LIN bus pin, low in dominant state

18

GND2

LS1

Ground connection

19

LS Driver

Low-side Driver, Ron 1.5 W typ, Ilim > 250 mA, active clamp to ground

Substrate; Exposed pad has to be connected to both GND pins

20

LS2

LS Driver

Exposed

Pad

Ground

APPLICATION INFORMATION

Cbuf_VSOUT

KL30

VBAT

Cbuf_VS

+12 V

(100nF)

VBAT

16

15

NCV7429

lift1

lift2

(1k)

VS

19

LS1

LS2

Low−Side

4

VR1

5 V / 150 mA

Protection:

Short circuit

Open load

Over −temperature

Under/over voltage

RELAY

M

20

Low−Side

Cload_VR1

(2.2uF)

3

NRES

Watchdog

Logic

VS_OUT

CONTROL_0

CONTROL_1

CONTROL_2

CONTROL_3

out1

High−Side

10

9

14

13

12

11

CSN

SCLK

SDI

OUT1

STATUS _0

STATUS_1

STATUS _2

MCU

(10−22nF)

OUT2

7

VS_OUT

PWM_1/2

PWM_3

out2

out3

High−Side

8

SDO

ROM

SPI

(10−22nF)

VS_OUT

2

High−Side

SWDM

OUT3/FSO

VS_OUT

Timer1/2

PWM

(10−22nF)

WU

VS

Local

wakeup

detector

wake

5

6

TxDL

SWITCHES

(1−10k)

(10nF)

LIN

RxDL/INTN

17

1

18

Cload_LIN

(220pF)

LIN

LIN BUS

Figure 2. Example Application Diagram

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3

NCV7429

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min

Max

Unit

Vmax_VS,

Power Supply Voltage

−0.3

40

V

Vmax_VS_OUT

Vmax_WU

Vmax_OUT1−3

Vmax_LS1/2

Wake Pin Voltage Range

−0.3

VS_OUT + 0.3

40

V

High-side Output OUT1−3 Voltage Range

LS1/2 Pin Voltage Range DC

(Voltage Internally Limited during Flyback)

Wmax_LS1/2

Imax_LS1/2

Maximum LS1/2 Clamping Energy

Maximum LS1/2 Pin Current

36

mJ

mA

500

Maximum LS1/2 Pin Current, Transient or without VS and

VS_OUT Supply

−120

Vmax_LIN

Vmax_VR1

Vmax_digIO

DC Voltage on LIN Pin

−40

−0.3

40

V

Stabilized Supply Voltage, Logic Supply

min(5.5, VS + 0.3)

VR1 + 0.3

DC Voltage at Digital Pins (NRES, TxDL, RxDL/INTN, SDI,

SDO, SCLK, CSN)

Vmax_SWDM

DC Voltage at SWDM Input

All Pins

−0.3

−2

40

+2

+4

+6

V

ESD Human Body

Model Following

EIA−JESD22

kV

Pin LIN to GND

−4

(100 pF, 1500 W)

Pins OUT1−3, LS1/2 to GND

−4

ESD Following IEC

61000−4−2

(150pF, 330W)

Valid for Pins VS, VS_OUT, LIN, OUT1−3, WU

−6

kV

− VS, VS_OUT pins with reverse-protection and filtering

capacitor

− OUT1−3 pins with parallel capacitor 10 nF

− WU pin stressed through a serial resistor > 10 kW

ESD Charged

Device Model

Following

All Pins

−500

−750

+500

+750

V

Corner Pins

JESD22−C101/AE

C−Q100−011

T

Junction Temperature

−40

−55

+170

°C

j_mr

T

Storage Temperature Range

+150

2

stg

MSL

Moisture Sensitivity Level (max. 260°C Processing)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 3. THERMAL CHARACTERISTICS

Symbol

Parameter

Value

Unit

Thermal Characteristics

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient, 1S0P PCB (Note 1)

Thermal Resistance, Junction-to-Ambient, 2S2P PCB (Note 2)

R

8.3

70

40

q

JC

q

JA

q

JA

°C/W

1. Value based on test board according to JESD51−3 standard, signal layer with 10% trace coverage.

2. Value based on test board according to JESD51−7 standard, signal layers with 20% trace coverage, inner planes with 90% coverage.

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4

NCV7429

Table 4. RECOMMENDED OPERATING RANGES

Symbol

Parameter

Min

Max

Unit

Vop_VS_par,

Power Supply Voltage for Valid Parameter Specifications

6

18

V

Vop_VS_OUT_par

Vop_VS_func,

Power Supply for Correct Functional Behavior

5

28

V

Vop_VS_OUT_func

Vop_WU

Vop_OUT1−3

Vop_LS1/2

Wake Pin Voltage Range

0

VS_OUT

V

High-side Output OUT1−3 Voltage Range

LS1/2 Pin Voltage Range DC

(voltage internally limited during flyback)

Vop_LIN

Vop_VR1

Vop_digIO

LIN Pin Voltage Range

0

4.9

0

VS

5.1

V

Stabilized Supply Voltage, Logic Supply

DC Voltage at Digital Pins (NRES, TxDL, RxDL/INTN, SDI,

SDO, SCLK, CSN)

VR1

Vop_SWDM

DC Voltage at SWDM Input

Junction Temperature

0

VS

V

T

j_op

−40

+150

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 5. ELECTRICAL CHARACTERISTICS

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

s

s_out

j

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VS SUPPLY

VS, VS_OUT

Supply Voltage

Functional, Voltage Regulators with

Deteriorated Performance

5

28

V

Parameter Specification

VS Rising

6

18

4.1

3.0

5.8

0.5

22

VS_PORH

VS_PORL

VS POR Threshold

3.4

2.1

5.1

0.1

20

V

VS POR Threshold

VS Falling

VS_OUT_UV

VS_OUT UV-threshold Voltage

VS Falling

V

VS_OUT_UV_hyst Undervoltage Hysteresis

VS_OUT_OV VS_OUT OV-threshold Voltage

VS_OUT_OV_hyst Overvoltage Hysteresis

V

VS Rising

V

0.3

0.5

0.6

0.8

1.1

V

I_VS_norm

VS Consumption in Normal Mode

Normal mode,

mA

VR1 on (not loaded),

bus communication off,

TxDL not active

I_VS_stby

VS Consumption in Standby Mode Standby mode,

28

15

60

30

mA

(Static Sense)

VS = 12 V, VR1 on (not loaded),

no LIM bus communication,

no wake-up request pending,

WU wakeup disabled,

T = 85°C (Note 3)

j

I_VS_sleep

VS Consumption in Sleep Mode

(Static Sense)

Sleep mode,

VS = 12 V, VR1 off,

no LIM bus communication,

no wake-up request pending,

WU wakeup disabled,

T = 85°C (Note 3)

j

I_VS_add_VR1

I_VS_add_LS

VR1 Current Consumption from VS Normal/Standby mode,

VR1 loaded

0.005 ·

I_VR1

mA

Added LSx Drivers Current

Consumption from VS

N = 1 – 2 … number of LSx drivers

active

15 +

20·N

110

mA

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5

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

VS SUPPLY

Parameter

Conditions

Min

Typ

Max

Unit

I_VS_add_WU

Added WU Comparator Current

Consumption from VS

0.6

2

mA

VS_OUT SUPPLY

I_VSOUT_norm

VS_OUT Consumption in Normal

Mode

Normal mode,

OUT1−3 off, floating

15

0

30

2

mA

I_VSOUT_stby

VS_OUT Consumption in Standby Standby mode, OUT1−3 off,

Mode

floating, WU wakeup disabled, WU

pin floating

I_VSOUT_sleep

VS_OUT Consumption in Sleep

Mode

Sleep mode, OUT1−3 off, floating,

WU wakeup disabled, WU pin

floating

0

2

90

120

8

mA

I_VSOUT_add_OUT Added OUTx Drivers Current

Consumption from VS_OUT

Normal mode, OUTx = floating,

N = 1 – 3 … number of OUTx

drivers active

15 x N

Standby/Sleep mode, OUTx =

floating, N = 1 – 3 … number of

OUTx drivers active

15 +

15 x N

I_VSOUT_add_WU Added WU Comparator Current

Consumption from VS_OUT

WU pin floating

4

VS + VS_OUT SUPPLY COMBINED CONSUMPTIONS

I_stby_cs

VS + VS_OUT Consumption in

Standby Mode

(with Cyclic Sense)

Standby mode,

(Note 4)

mA

VS = VS_OUT = 12 V, VR1 on

(not loaded), OUTx floating,

driven by Timer1/2,

bus communication off,

No wake-up request pending,

T = 25°C (Note 3)

j

I_sleep_cs

I_FailSafe

VS + VS_OUT Consumption in

Sleep Mode

(with Cyclic Sense)

Sleep mode,

(Note 5)

mA

VS = VS_OUT = 12 V, VR1 off,

OUTx floating, driven by Timer1/2,

bus communication off,

No wake-up request pending,

T = 25°C (Note 3)

j

VS + VS_OUT Consumption in

Fail-safe Mode

Fail-safe mode,

OUTx floating, OUT3/FSO on

50

100

3. Guaranteed by design.

4. Cyclic-sense Standby mode VS + VS_OUT consumption:

I_standby_cs (typ.) = I_VS_standby + I_VSOUT_sleep + I_VS_standby_cs_add

I_stdby_cs_add (typ.) = 24.5 mA + (28 mA S Tx_TON / Tx_TPER)

5. Cyclic-sense Sleep mode VS + VS_OUT consumption:

I_sleep_cs (typ.) = I_VS_sleep + I_VSOUT_sleep + I_VS_sleep_cs_add

I_sleep_cs_add (typ.) = 25.5 mA + (28 mA S Tx_TON / Tx_TPER)

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NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOLTAGE REGULATOR VR1

V_VR1

Regulator Output Voltage

0 mA ≤ I(VR1) ≤ 150 mA,

6 V ≤ VS ≤ 28 V,

Cload_LIN ≥ 82 pF

4.9

5

5.1

V

Under EMC exposure (Note 6, 7)

Cload_LIN < 82 pF

4.85

5

5.15

V

Iout_VR1

Ilim_VR1

Regulator Output Current

Regulator Current Limitation

Regulator Sink Current

Dropout Voltage

Maximum VR1 load current

Maximum VR1 short current

V(VR1) = 5.2 V

150

600

mA

V

240

100

Isink_VR1

Vdrop_VR1

I(VR1) = 60 mA, VS = 5 V

I(VR1) = 60 mA, VS = 4.5 V

I(VR1) = 30 mA, VS = 4.5 V

1 mA ≤ I(VR1) ≤ 30 mA

I(VR1) ≤ 5 mA

0.25

0.3

0.4

0.5

0.4

30

0.2

Loadreg_VR1

Linereg_VR1

Cload_VR1

Load Regulation

Line Regulation

−30

1

mV

mF

30

VR1 Load Capacitor

ESR < 200 mW, ceramic capacitor

2.2

recommended

Icmp_VR1_rise

Icmp_VR1_fall

Icmp_VR1_hys

Tfilt_VR1_Icmp

Vfail_VR1

Current Comp. Rising Threshold

Current Comp. Falling Threshold

Current Comp. Hysteresis

Current Comp. Filter Time

VR1 Fail Threshold

VR1 consumption increasing

VR1 consumption decreasing

0.8

0.6

2

1.4

0.5

16

2

3.1

2.1

mA

ms

V

VR1 forced, VR1 decreasing

VR1 starting-up

1.85

2.25

Tfail_VR1

VR1 Fail Blanking Time

5

ms

s

Tshort_VR1

Ttsd_VR1

VR1 Short Blanking Time

34

40

1

46

VR1 Deactivation Time after Ther-

mal Shutdown 2

0.85

1.15

Toff_VR1

VR1 Off Time after 8 Watchdog

Failures

170

200

230

ms

VR1 UNDER-VOLTAGE DETECTOR

VR1_RES1

VR1 Reset Threshold 1 (Default)

SPI VR1_RES.x = 00,

VR1 voltage falling

4.45

4.2

3.8

3.6

4.65

4.4

4

4.8

4.6

4.2

4

V

VR1_RES2

VR1 Reset Threshold 2

VR1 Reset Threshold 3

VR1 Reset Threshold 4

SPI VR1_RES.x = 01,

VR1 voltage falling

VR1_RES3

SPI VR1_RES.x = 10,

VR1 voltage falling

V

VR1_RES4

SPI VR1_RES.x = 11,

VR1 voltage falling

3.8

V

Tdel_VR1_RES

Tfilt_VR1_RES

Reaction Delay between VR1 Un-

dervoltage and NRES Low Pulse

40

ms

VR1 Undervoltage Filter Time

16

6. Based on characterization, Guaranteed by design.

7. DPI EMC coupled to LIN pin, Clin not used. Tested according to LIN Conformance Test Specification Package for LIN 2.1, October 10th,

2008.

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7

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

5

Max

Unit

HIGH-SIDE OUTPUTS OUT1−3

Ron_OUT1_norm

Ron_OUT1_high

Ron_OUT2−3

On-Resistance to VS_OUT,

“Normal-ohmic” Configuration

T = 25°C, I(OUT1) = −60 mA

W

j

T = 150°C, I(OUT1) = −60 mA

13

52

j

On-Resistance to VS_OUT,

“High-ohmic” Configuration

T = 25°C, I(OUT1) = −6 mA

20

W

j

T = 150°C, I(OUT1) = −6 mA

W

j

On-Resistance to VS_OUT

T = 25°C, I(OUT2−3) = −60 mA

5

W

j

T = 150°C, I(OUT2−3) = −60 mA

j

13

W

Ilim_OUT1_norm

Output Current Limitation to

Ground, “Normal-ohmic” Configura-

tion

V(OUT1) = 0 V

−330

−82

−235

−140

mA

Ilim_OUT1_high

Output Current Limitation to

−58

−35

mA

Ground, “High-ohmic” Configuration

Ilim_OUT2−3

Output Current Limitation to Ground V(OUT2−3) = 0 V

−330

−6.5

−235

−3.5

−140

−0.8

mA

Iuld_OUT1_norm

OUT1 Underload Threshold,

“Normal-ohmic” Configuration

Iuld_OUT1_high

OUT1 Underload Threshold,

“High-ohmic” Configuration

−1.5

−0.87

−3.5

−0.2

−0.8

mA

Iuld_OUT1−3

Ileak_OUT1−3

Slew_OUT1−3

OUT2−3 Underload Threshold

−6.5

−3

mA

Output Leakage Current

Slew Rate of OUT1−3

VS_OUT = 28 V, V(OUT1−3) = 0 V

VS_OUT = 13.2 V,

140 mA resistive load

0.2

0.5

80

0.8

95

V/ms

Tblank_ULD_OUT1−3 Underload Detection Blanking De-

lay

OUT1−3 switched on

65

ms

Tfilt_ULD_OUT1−3 Underload Detection Filter Time

Tfilt_OLD_OUT1−3 Overload Shutdown Filter Time

LOW-SIDE RELAY OUTPUTS LS1/2

50

60

75

ms

Ron_LS1/2

On-Resistance to Ground

T = 25°C, I(LS1/2) = 100 mA

1.5

3

W

j

T = 125°C, I(LS1/2) = 100 mA

3.7

j

(Note 8)

Ilim_LS1/2

Output Current Limitation

LS1/2 = VS_OUT

LS1/2 = VS_OUT > 18 V

I(LS1/2) = 100 mA

LS1/2 = VS_OUT = 16 V

250

200

40

340

290

500

450

50

3

mA

V

Vclamp_LS1/2

Ileak_LS1/2

Slew_LS1/2

Output Clamp Voltage

Output Leakage Current

Slew Rate of LS1/2

mA

VS_OUT = 13.2 V,

100 mA resistive load

0.2

50

2

4

V/ms

Tfilt_OLD_LS1/2

WAKE-UP INPUT WU

Vth_down_WU

Overload Shutdown Filter Time

60

75

ms

Wake-up Negative Edge Threshold WU configurable as Source/Sink

Voltage

0.4

0.5

0.6

VS_OUT

via SPI

Vth_up_WU

Wake-up Positive Edge Threshold

Voltage

Vhyst_WU

Ipullup_WU

Ipulldown_WU

Twu_WU

Wake-up Threshold Hysteresis

Pullup Current

100

−30

10

300

−20

20

500

−10

30

mV

mA

ms

1.5 V < V(WU) < V(VS_OUT − 3 V)

Pulldown Current

Minimum Time for Wake-up

50

64

85

8. Based on characterization, Guaranteed by design.

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NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MODE TRANSITION TIMING

Tdel_powerup

Tdel_norm_stdby

Tdel_norm_sleep

Tdel_stdby_norm

Tdel_sleep_init

Transition Time from Power-up to

Init

VS reaching VS_PORH to VR1

startup

15

10

ms

Transition Time from Normal/Flash CSN going high to Standby mode

to Standby Mode via SPI entry (Note 9)

Transition Time from Normal/Flash CSN going high to Sleep mode

to Sleep Mode via SPI

entry (Note 9)

Delay of INTN Pulse in Standby af-

ter Wakeup

Transition from Sleep to Init Mode

via Wakeup

NRES AND INTN SIGNAL TIMING

T_NRES

NRES Low Pulse Duration,

e.g. after a Watchdog Failure or

VR1 Undervoltage

1.7

2

2.3

ms

T_INTN

INTN Low Pulse Duration

after Wake-up Event

106

125

144

ms

DRIVER TIMING

Tdel_OUT1−3_on

Activation Delay of OUT1−3 Driver VS_OUT = 13.2 V;

12

20

17

40

55

85

62

ms

(from CSN rising edge)

V(OUT1−3) > 0.5·VS_OUT

Tdel_OUT1−3_off

Tdel_LS1/2_on

Tdel_LS1/2_off

De-activation Delay of OUT1−3

Driver (from CSN rising edge)

VS_OUT = 13.2 V;

V(OUT1−3) < 0.5·VS_OUT

Activation Delay of LS1/2 Driver

(from CSN rising edge)

VS_OUT = 13.2 V;

V(LS1/2) < 0.5·VS_OUT

42

32

De-activation Delay of LS1/2 Driver VS_OUT = 13.2 V;

(from CSN rising edge)

V(LS1/2) > 0.5·VS_OUT

INTERNAL PWM FOR DRIVERS CONTROL

f_PWM_lo

f_PWM_hi

PWM Controller Frequency,

Low Setting

FSEL_OUTx/LSx = 0

FSEL_OUTx/LSx = 1

127

170

150

200

173

230

Hz

PWM Controller Frequency,

High Setting

TIMER1/2 TIMING

Ttim_acc

Timer1/2 Period/On-time Accuracy T1_TPER.[2:0], T1_TON,

(see CONTROL_2 register settings) T2_TPER.[2:0], T2_TON.[1:0]

−15

+15

%

9. Delays and slopes of LS1/2 drivers not included.

www.onsemi.com

9

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

SPI TIMING

tCSN_SCLK

Parameter

Conditions

Min

Typ

Max

Unit

First SPI Clock Edge after CSN Ac- (Note 10)

tive

200

ns

ms

tCSN_SDO

tCSN_High

tSCLK_High

tSCLK_Low

SDO Output Stable after CSN Ac-

tive

C(SDO) = 100 pF (Note 10)

150

Inter-frame Space (CSN Inactive)

All SPI frames stored into internal

registers (Note 10)

6

Duration of SPI Clock High Level

Duration of SPI Clock Low Level

SPI Clock Period

(Note 10)

250

ns

(Note 10)

tSCLK_per

tSDI_set

(Note 10)

1

ms

Setup Time of SDI Input Towards

SPI Clock

100

ns

tSDI_hold

tSCLK_SDO

t_SPI_exec

Hold Time of SDI Input Towards SPI (Note 10)

Clock

100

ns

ms

SDO Output Stable after SPI Clock C(SDO) = 100 pF (Note 10)

Falling Edge

250

25

SPI Frame Execution Time

Time from CSN rising edge to exe-

cution of the frame

10.Guaranteed by design; not tested in production.

SPI frame executed

t_{CSN _High}

t_{CSN _SCLK}

t_{SCLK _per}

t_{SCLK_Low}

t_{S CLK_High}

CSN

SCLK

SDI

t_{SDI _set}

t_{SDI_hold}

SDO

t_SPI _exec

t_{CSN _SDO}

t_{SCLK_SDO}

Figure 3. SPI Timing Parameters

www.onsemi.com

10

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

WATCHDOG TIMING

Twd_acc

Watchdog Timing Accuracy

−15

55

+15

75

%

T_wd_TO

Timeout Watchdog Period;

(watchdog is in the timeout mode

after NRES release or in the Stand-

by mode)

65

ms

T_wd_CW

T_wd_OW

Window Watchdog Closed Window

Window Watchdog Open Window

ms

SPI WD_PER.x = 00

SPI WD_PER.x = 01

SPI WD_PER.x = 10

SPI WD_PER.x = 11

SPI WD_PER.x = 00

SPI WD_PER.x = 01

SPI WD_PER.x = 10

SPI WD_PER.x = 11

SPI WD_PER.x = 00

SPI WD_PER.x = 01

SPI WD_PER.x = 10

SPI WD_PER.x = 11

SPI WD_PER.x = 00

SPI WD_PER.x = 01

SPI WD_PER.x = 10

SPI WD_PER.x = 11

Position inside T_wd_TO interval

6

24

60

120

10

40

100

200

9.75

39

T_wd_trig

Window Watchdog Trigger Period

via SPI (the safe trigger area)

6.9

27.6

69

13.6

54.1

136

272

18.4

73.6

184

736

97.5

195

16

138

13.6

54.4

136

544

T_wd_TO_FLASH

Timeout Watchdog Period in Flash

Mode

64

160

640

33

T_wd_33_TO

T_wd_66_TO

T_wd_33_OW

WD_STATUS.1 bit Threshold of

Timeout Length (in timeout mode)

%

WD_STATUS.0 bit Threshold of

Timeout Length (in timeout mode)

Position inside T_wd_TO interval

Position inside T_wd_OW interval

66

33

WD_STATUS.1 bit Threshold of

Open Window Length (in open win-

dow mode)

T_wd_66_OW

WD_STATUS.0 bit Threshold of

Open Window Length (in open win-

dow mode)

Position inside T_wd_OW interval

66

%

Reset or previous

WD service

nominal T _wd_TO

Time −out

WD period

Safe trigger of time−out WD

WD expired

T_wd_TO tolerance

T_wd_trig

nominal T _wd_CW

nominal T _wd_OW

Window WD

Closed window

(WD trigger would be too early

Safe trigger of window WD

period

)

OK20170129.01

T_wd_CW

tolerance

T_wd_OW

tolerance

recommended

WD trigger

Figure 4. Watchdog Modes Timing

www.onsemi.com

11

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

LIN TRANSMITTER DC CHARACTERISTICS

VLin_dom_LoSup

VLin_dom_HiSup

VLin_rec

LIN Dominant Output Voltage

LIN Recessive Output Voltage

TxDL = low; VS = 7.3 V

TxDL = low; VS = 18 V

1.2

2

V

TxDL = high;

I(LIN) = 0 mA

VS − 1.5

VS

ILIN_lim

Short Circuit Current Limitation

Internal Pull-up Resistance

V(LIN) = VS = 18 V

40

20

200

47

mA

Rslave_LIN

33

kW

LIN RECEIVER DC CHARACTERISTICS

Vbus_dom_LIN

Vbus_rec_LIN

Vrec_dom_LIN

Vrec_rec_LIN

Vrec_cnt_LIN

Vrec_hys_LIN

ILIN_off_dom

Bus Voltage for Dominant State

0.4

VS

mA

Bus Voltage for Recessive State

Receiver Threshold

0.6

0.4

0.5

LIN bus recessive → dominant

LIN bus dominant → recessive

0.5

0.6

Receiver Threshold

Receiver Center Voltage

Receiver Hysteresis

(Vrec_dom_LIN + Vrec_rec_LIN) / 2 0.475

0.525

0.175

−0.2

(Vrec_rec_LIN − Vrec_dom_LIN)

0.05

−1

LIN Output Current,

Bus in Dominant State

Normal mode, driver off;

VS = 12 V; V(LIN) = 0 V

ILIN_off_dom_slp

ILIN_off_rec

LIN Output Current,

Bus in Dominant State

Sleep or Standby mode, driver off;

VS = 12 V; V(LIN) = 0 V

−20

−1

−15

−2

10

mA

LIN Output Current,

Bus in Recessive State

Driver off; 8 V < VS < 18 V;

8 V < V(LIN) < 18 V; V(LIN) ≥ VS;

Guaranteed by design

ILIN_no_GND

ILIN_no_VS

Communication Not Affected

LIN Bus Remains Operational

VS = GND = 12 V;

0 < V(LIN) < 18 V

1

5

mA

VS = GND = 0 V;

0 < V(LIN) < 18 V

mA

LIN TRANSMITTER DYNAMIC CHARACTERISTICS

D1

D2

D3

D4

Duty Cycle 1 =

tBUS_REC(min) / (2 × TBit)

THREC(max) = 0.744 × VS,

THDOM(max) = 0.581 × VS,

Tbit = 50 ms,

0.396

0.5

0.581

0.5

VS = 7 V to 18 V; L1−L3 (Note 11)

Duty Cycle 2 =

tBUS_REC(max) / (2 × TBit)

THREC(min) = 0.422 × VS,

THDOM(mi) = 0.284 × VS,

Tbit = 50 ms,

VS = 7.6 V to 18 V; L1−L3 (Note 11)

Duty Cycle 3 =

tBUS_REC(min) / (2 × TBit)

THREC(max) = 0.788 × VS,

THDOM(max) = 0.616 × VS,

Tbit = 96 ms,

0.417

0.5

VS = 7 V to 18 V; L1−L3 (Note 11)

Duty Cycle 4 =

tBUS_REC(max) / (2 × TBit)

THREC(min) = 0.389 × VS,

THDOM(min) = 0.251 × VS,

Tbit = 96 ms

0.59

VS = 7.6 V to 18 V; L1−L3 (Note 11)

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12

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

LIN TRANSMITTER DYNAMIC CHARACTERISTICS

T_fall_LIN

T_rise_LIN

T_sym_LIN

LIN Falling Edge

LIN Rising Edge

LIN Slope Symmetry

VS = 12 V; L1, L2 (Note 11);

Normal slope mode

22.5

4

ms

VS = 12 V; L1, L2 (Note 11);

Normal slope mode

VS = 12 V; L1, L2 (Note 11);

Normal slope mode

−4

0

T_fall_norm_LIN

T_fall_low_LIN

LIN Falling Edge

LIN Rising Edge

LIN Slope Symmetry

VS = 12 V; L3 (Note 11);

Normal slope mode

27

62

27

62

5

ms

VS = 12 V; L3 (Note 11);

Low slope mode

T_rise_norm_LIN

T_rise_low_LIN

T_sym_norm_LIN

T_TxDL_timeout

VS = 12 V; L3 (Note 11);

Normal slope mode

VS = 12 V; L3 (Note 11);

Low slope mode

Normal mode; VS = 12 V;

L3 (Note 11)

−5

0

TxDL Dominant Time-out

Selected by SPI bits TxDL_TO

SPI setting TxDL_TO[1:0]=“00”

SPI setting TxDL_TO[1:0]=“01”

SPI setting TxDL_TO[1:0]=“1X”

27

6

55

13

70

20

disabled

20

C_LIN

Capacitance of the LIN Pin

Guaranteed by design;

not tested in production

30

pF

LIN RECEIVER DYNAMIC CHARACTERISTICS

Trec_prop_down

Trec_prop_up

Trec_sym

Propagation Delay of Receiver Fall- C(RxDL) = 20 pF

ing Edge

6

ms

Propagation Delay of Receiver Ris-

ing Edge

C(RxDL) = 20 pF

Propagation Delay Symmetry

Trec_prop_down − Trec_prop_up,

C(RxDL) = 20 pF

−2

30

2

T_LIN_wake

Dominant Duration for Wakeup

90

150

11. The following bus loads are considered: L1 = 1 kW/1 nF; L2 = 680 W/6.8 nF; L3 = 500 W/10 nF.

TxDL

t_BIT

50%

t

t_{BUS_dom(max)}

t_{BUS_rec(min)}

LIN

TH_Rec(max)

TH_Dom(max)

Thresholds of

receiving node 1

TH_Rec(min)

TH_Dom(min)

Thresholds of

receiving node 2

t

t_{BUS_dom(min)}

t_{BUS_rec(max)}

Figure 5. LIN Dynamic Characteristics − Duty Cycles

www.onsemi.com

13

NCV7429

LIN

100%

60%

40%

60%

40%

0%

t

T_fall

T_rise

Figure 6. LIN Dynamic Characteristics − Transmitter Slope

LIN

VS

60% VS

40% VS

t

Trec _prop _down

Trec _prop _up

RxDL

50%

t

Figure 7. LIN Dynamic Characteristics − Receiver

LIN

Detection of Remote Wake−Up

VS

recessive

dominant

T_LIN_wake

60% VS

40 % VS

t

Figure 8. LIN Wakeup

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14

NCV7429

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(6 V ≤ V ≤ 18 V, 6 V ≤ V

≤ 18 V, −40°C ≤ T ≤ 150°C; unless otherwise specified)

j

s

s_out

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DIGITAL OUTPUTS RXDL/INTN, SDO

IoutL_pinx

Low-level Output Driving Current

pinx is logical Low,

forced V(pinx) = 0.4 V

2

5

12

−2

5

mA

IoutH_pinx

High-level Output Driving Current

Leakage in the Tristate, Pin SDO

pinx is logical High,

forced V(pinx) = VR1 − 0.4 V

−12

−5

Ileak_HZ_pinx

pinx in the HZ state,

forced 0 V < V(pinx) < VR1

DIGITAL OUTPUT NRES

IoutL_NRES

Low-level Output Driving Current

NRES is active (logical Low),

forced V(NRES) = 0.4 V

2

5

12

mA

V

VoutL_NRES

Low-level Output Voltage, Low

VR1/VS

VR1 > 2 V, VS < VR1,

I(NRES) = 0.1 mA

0.4

VS > 2 V,

0.4

V

I(NRES) = 0.1 mA

Rpullup_NRES

Internal Pull-up Resistor to VR1

55

100

185

kW

DIGITAL INPUTS SWDM, TXDL, SDI, SCLK, CSN

VinL_pinx

VinH_pinx

Low-level Input Voltage

0

2

0.8

VR1

500

10

V

High-level Input Voltage

Vin_hys_pinx

Vin_SWDM

Input Voltage Hysteresis

100

7

mV

V

SWDM Pin Threshold Voltage

SWDM Pin Threshold Hysteresis

8.5

200

100

Vin_hys_SWDM

Rpullup_pinx

10

55

300

185

mV

kW

Internal Pull-up Resistor to VR1;

Pins TxDL, CSN

Rpulldown_pinx

Internal Pull-down Resistor to

Ground; Pins SWDM, SDI, SCLK

55

100

185

kW

THERMAL PROTECTION

Tjw

Tjsd1

Thermal Warning Level

125

135

145

5

135

147

159

12

145

160

175

°C

Thermal Shutdown Level 1

Thermal Shutdown Level 2

Tjsd2

Tjsd1−Tjw

Thermal Warning and Thermal

Shutdown 1 Level Distance

Tjsd2−Tjsd1

Thermal Shutdown 1 and Thermal

Shutdown 2 Levels Distance

5

12

°C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

15

NCV7429

FUNCTIONAL DESCRIPTION

The NCV7429 is a monolithic LIN System-Basis-Chip

microcontroller unit (MCU) and related 5 V loads (e.g. its

own MCU-related digital inputs/outputs). An external

capacitor needs to be connected on VR1 pin in order to

ensure the regulator’s stability and to filter the disturbances

caused by the connected loads. Ceramic X7R 2.2 mF

capacitor is recommended.

VR1 voltage is supplying all digital low-voltage

input/output pins.

The protection and monitoring of the VR1 regulator

consist of the following features:

• VR1 Current Limitation – the current protection

ensures fast enough charging of the external capacitor

at start-up while protecting the regulator in case of

shorts to ground

• Junction Temperature Monitor – the junction

temperature is monitored and when it rises above the

second shutdown level, the VR1 regulator is

de-activated and the device is forced to the Fail-safe

mode in order to protect the regulators and the full

application. For details, see par. “Thermal Protection”.

with enhanced feature set useful in automotive body control

systems. Besides the LIN bus interface, the IC features a 5 V

voltage regulator, several high-side and low-side switches to

control LEDs and relays plus supervision functionality like

a window watchdog. This allows a highly integrated

solution by replacing external discrete components while

maintaining the valuable flexibility. Due to this the board

space and ECU weight can be minimized to the lowest level.

POWER SUPPLY AND REGULATORS

VS/VS_OUT – Main Power Supply

VS pin is the main power supply of the device, while

VS_OUT supplies OUT1−3 drivers and WU input. In the

application, it will be typically connected to the KL30 or

KL15 car node. It is necessary to provide an external

reverse-polarity protection and filtering capacitor on the VS

supply (see Figure 2).

VS/VS_OUT supplies are monitored with respect to the

following events:

• VS power-on reset is detected as a crossing of VS_POR

• VR1 Failure Comparator – during the VR1 start-up and

operation, the VR1 voltage is continuously compared

with Vfail_VR1 level (typ. 2 V). During startup, if VR1

does not rise above Vfail_VR1 level within Tshort_VR1

(typ. 40 ms), it’s considered shorted to ground and the

device is forced to the Fail-safe mode (see Figure 10).

During the VR1 operation, any dip below Vfail_VR1

level longer than Tfail_VR1 (typ. 5 ms) is considered as

a failure – temporary excursions of VR1 under the

failure threshold can be caused, for example, by EMC,

and can lead to memory data inconsistencies inside the

MCU. Both the failure during VR1 startup and the

operation are latched in the “VR1_FAIL” SPI bit for

subsequent software diagnostics.

level. When VS remains below VS_POR,

the device is passive and provides no functionality, the

SPI registers are reset to their default values. When VS

rises above VS_PORH, the device starts following its

state diagram through the power-up state. This event is

latched in the SPI bit “COLD_START” so that the

application software can detect the VS connection.

• VS_OUT Under-Voltage is detected when VS_OUT

falls below VS_OUT_UV threshold (typ. 5.5 V).

A VS_OUT under-voltage can be encountered, for

example, with a discharged car battery or during engine

cranking. The high-side and low-side drivers are

typically forced off. The exact driver reaction depends

on the SPI control settings – see par. “VS_OUT Over-

and Under-Voltage”. Under-voltage events are flagged

through SPI bit “VS_OUT_UV”.

• VR1 Reset Comparator – the VR1 regulator output is

compared with a reset level VR1_RES (programmable

to typ. 74%, 79%, 87% and 91% of the nominal VR1

voltage). If the VR1 level drops below this level for

longer than Tfilt_VR1_RES (typ. 16 ms), a reset towards

the MCU is generated through the NRES pin and all

outputs (OUT1−3, LS1/2) are switched off and all the

control registers are set to their defaults, except

“FSO_DIS” bit setting (see Figure 11).

• VS_OUT Over-Voltage is detected when VS_OUT

rises over VS_OUT_OV threshold (typ. 21 V). Similarly

to the under-voltage, the high-side and low-side drivers

are de-activated based on the SPI settings and the event

is flagged through SPI bit “VS_OUT_OV”.

GND1, GND2 – Ground Connections

• VR1 Consumption Monitor (Icmp) – to ensure a safe

transition into the Standby mode, where VR1 remains

active while the watchdog is off, the VR1 current

consumption is monitored. The watchdog is really

disabled in the Standby mode only when the VR1

consumption falls below Icmp_VR1_fall (typ. 1.1 mA).

An increase of the VR1 consumption above the

Icmp_VR1_rise level activates the watchdog again.

The device ground connection is split to two pins – GND1

and GND2. Both pins have to be connected on the

application PCB.

Regulator VR1

VR1 is a low-drop output regulator providing 5 V voltage

derived from the VS main supply. It is able to deliver up to

150 mA and is primarily intended to supply the application

www.onsemi.com

16

NCV7429

0

1

0

1

0

1

0

SPI: VR1_FAIL

1

0

SPI: COLD_START

VS

VS_UV

VS_POR

<Tfilt_VR1_RES

VR1

VR1_RES

Vfail_VR1

<Tfail_VR1

>Tfail_VR1

NRES

SPI

T_NRES

Figure 9. VR1 Monitoring

Mode Sleep mode

Watchdog off

Normal mode

Fail−safe mode

1

Reset

timeout −> window

0

1

0

SPI VR1_FAIL

:

< Tshort_VR1

VR1 failure

during startup

VR1_RES

Vfail_VR1

VR1

NRES

OUTx

FSO

VR1 startup

successfull

Tshort_VR1

Tdel_VR1_RES

T_NRES

OUTx, LS1/2

setting ignored

Figure 10. VR1 Monitoring − VR1 Failure during Startup

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17

NCV7429

Mode

Watchdog

Normal / Standby mode

timeout / window / off

Normal mode

Reset

0

timeout −> window

SPI VR1_FAIL

0

VR1 overload

VR1_RESx

Vfail_VR1

VR1

Tfilt_VR1_RES

Tdel_VR1_RES

Tfilt_VR1_RES

NRES

OUTx

FSO

T_NRES

Figure 11. VR1 Monitoring − VR1 Undervoltage

Mode

Watchdog

Normal / Standby mode

Normal mode

Reset

1

timeout / window / off

timeout −> window

0

1

0

SPI: VR1_FAIL

VR1 short

VR1_RESx

Vfail_VR1

VR1

Tfilt_VR1_RES

Tdel_VR1_RES

NRES

OUTx

FSO

T_NRES

OUTx, LS1/2

setting ignored

Tfail_VR1

Figure 12. VR1 Monitoring − VR1 Short in Normal/Standby Mode

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18

NCV7429

COMMUNICATION TRANSCEIVER

HIGH- AND LOW-SIDE DRIVERS

LIN Transceiver

High-Side Drivers OUT1−3

The NCV7429 on-chip LIN transceiver is an interface

between a physical LIN bus and the LIN protocol controller.

It is compatible to LIN2.x and J2602 specifications.

The LIN is supplied solely from the VS pin and its state

control is as follows:

• In the Normal mode of the device, LIN transceiver

transmits dominant or recessive symbols on the LIN

bus based on the logical level on TxDL pin. The signal

received from the bus is indicated on RxDL pin. Both

logical pins are referred to the VR1 supply. A resistive

pull-up path of typ. 30 kW is internally connected

between LIN and VS.

High-side drivers OUT1−OUT3 are designed to supply

mainly LED’s or switches (for cyclic monitoring). When

switched on, they connect the corresponding pin to the

VS_OUT supply. Driver OUT1 can be configured to have

two distinct levels of on-resistance; typically 5 W in

“normal-ohmic” configuration (default) and typically 20 W

in “high-ohmic” configuration. Drivers OUT2−3 have

a typical on-resistance of 5 W.

At the VS power-up or wakeup from the Sleep mode, all

OUT1−3 drivers are off. Immediately after the device enters

the Normal mode, they can be set to one of the following

states via the corresponding SPI bits:

• Driver is off in all modes (default)

• In the Standby and Sleep mode of the device, the LIN

transceiver is in its wakeup detection state. Logical

level on TxDL is ignored and pin RxDL is kept high

until it’s used as an interrupt request signal. A LIN bus

wakeup corresponds to a dominant symbol at least

T_LIN_wake long (typ. 90 ms) followed by a rising

edge (i.e. transition to recessive) – see Figure 8. In this

way, false wakeups due to permanent LIN dominant

failures are avoided. Only a pull-up current of typ.

15 mA is connected between VS and LIN instead of the

30 kW pull-up path. The LIN wakeup detection is by

default active in the Standby and Sleep modes and can

be disabled via SPI control registers.

• Driver is on in all modes, except Fail-safe mode

• Driver is activated periodically in all modes, except

Fail-safe mode. The periodicity is driven either by

Timer 1 (period from 0.5 sec to 4 sec, on time 10 ms or

20 ms) or Timer 2 (period from 10 ms to 200 ms, on

time 100 ms, 200 ms, 1 ms or 5 ms). Periodical

activation can be used, for example, for LED flashing

or cyclic contact monitoring.

• Driver is controlled by the on-chip PWM controller in

all modes, except Fail-safe mode. Each OUTx driver

has a dedicated 7-bit PWM duty cycle and the base

frequency selectable through individual SPI settings.

The LIN transceiver features SPI-configurable TxDL

dominant time-out timer. This circuit, if enabled, prevents

the bus lines being driven to a permanent dominant state

(blocking all network communication) if pin TxDL is forced

permanently low by a hardware and/or software application

failure. The timer is triggered by a negative edge on pin

TxDL. If the duration of the low-level on pin TxDL exceeds

the internal timer value T_TxDL_timeout, the transmitter is

disabled, driving the bus into a recessive state and the event

is latched in the SPI status bit “TO_TxDL”. The

transmission is de-blocked when “TO_TxDL” bit is reset by

the corresponding register “read and clear” and TxDL pin

returns to high (recessive) state.

The LIN transceiver provides two LIN slope control

modes, configured by SPI bit “LIN_SLOPE”.

In normal slope mode the transceiver can transmit and

receive data via LIN bus with speed up to 20 kBaud

according LIN2.x specification. This mode is used by

default.

The SPI settings for the drivers are applied immediately

after the SPI frame is successfully completed (CSN rising

edge) as long as FSO is not active. This can be done even

immediately after the device initialization before the first

watchdog service.

All OUTx outputs are protected by the following features:

• Over-current protection and current limitation: if the

driver current exceeds the over-current limit for longer

than Tfilt_OLD_OUTx (typ. 60 ms), the event is latched

into the SPI status bits and the driver is disabled. It will

be again enabled only when the corresponding SPI flag

is read and cleared. The over-current event in the

Standby or Sleep mode causes the interrupt in case SPI

bit “WU_OC” is set.

• Under-load detection: during the on-time of the driver,

a too low current indicates missing load. The

under-load event is latched into the corresponding SPI

status bits; however, the driver is not disabled and

remains controlled according the SPI bits.

In low slope mode the slew rate of the signal on the LIN

bus is reduced (rising and falling edges of the LIN bus signal

are longer). This further reduces the EMC emission. As a

consequence the maximum speed on the LIN bus is reduced

up to 10 kBaud. This mode is suited for applications where

the communication speed is not critical. The low slope mode

can be configured by setting SPI bit “LIN_SLOPE”.

• Thermal protection and VS_OUT under/over-voltage

protection: through monitoring of the junction

temperature and the VS_OUT supply voltage; all loads

are protected as described in par. “Protection”. If SPI

bit “WU_TSD” resp. “WU_OVUV” is set, the thermal

shutdown 1 event resp. VS_OUT over-/under-voltage

in the Standby or Sleep mode causes the interrupt.

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NCV7429

OUT3 output is also intended for failure indication. By

(period from 10 ms to 200 ms). WU is left to settle

during the on-time and the state detection is started

20 ms before the on-time end through a filter of typ.

16 ms. The result of the periodical state detection is

latched into the SPI status register and is not updated

until the next period of the selected timer. A wakeup is

detected in case sample of the WU state changes in any

direction.

default, OUT3 switch is not controlled by the SPI settings

but by the internal FSO signal – see section “Fail-Safe (FSO)

Signal”. Only when the FSO signal is disconnected from

OUT3 by setting SPI bit “FSO_DIS”, OUT3 acts identically

to OUT1 and OUT2.

Low-Side Drivers LS1/2

NCV7429 offers two low-side drivers LS1 and LS2

primarily intended to drive relays, typically:

Additionally, the WU input can be internally pre-biased

through individual control bits by

a

pull-down

• R = 160 W 10%, L = 240/300 mH

(WU_PUD=0) or pull-up (WU_PUD=1) current source.

The pre-bias is disabled in Standby or Sleep mode if WU

wakeup is disabled (WU_DIS=1).

In case cyclic sense is used, the WU timer settings must

be correctly chosen together with the high-side output

settings. The driver physically ensuring the periodical

contact supply must be set for the same timer as the contact

monitor by the MCU software.

• R = 220 W 10%, L = 330/420 mH

For the relay demagnetization, LS1/2 drivers feature

active flyback clamps towards ground (no diode to

VS_OUT) allowing to keep the load off even under

load-dump condition on VS_OUT. Alternatively, LS1/2 can

drive LED’s.

LS1/2 can be configured in one of the following states:

• Off in all modes (default)

• On in the Normal mode; off in all other modes

OPERATING MODES

• Controlled by individual PWM in the Normal mode; off

in all other modes. If a relay is connected to the output,

this setting should not be used.

LS1/2 outputs are protected by the following features:

• Over-current protection and current limitation: if the

driver current exceeds the over-current limit for longer

than Tfilt_OLD_LS1/2 (typ. 60 ms), the event is latched

into the SPI status bits and the driver is disabled. It will

be again enabled only when the corresponding SPI flag

is read and cleared.

NCV7429 can be configured to different operating modes

in function of the application needs and the external

conditions. The device resources can be enabled/disabled and

the overall power consumption can be adapted to the

electronic module state – ranging from full power mode down

to a very low quiescent current “sleep” mode. The principal

operating modes of NCV7429 are shown in Figure 13.

Un-Powered and Init Modes

As long as VS remains below the VS_POR level (typ.

3.45 V), the device is held in power-up reset. All outputs

except NRES are in HiZ state, the linear regulator output is

off.

• Thermal protection and VS_OUT under/over-voltage

protection: through monitoring of the junction

temperature and the VS_OUT supply voltage; all loads

are protected as described in par. “Protection”.

As soon as the VS main supply exceeds the power-on reset

level, the device enters an initialization sequence

represented by a transient “init” mode. All SPI registers are

set to their default values, “COLD_START” SPI bit is set

high for subsequent diagnostics and the VR1 regulator is

started. After a successful start of the VR1 regulator (i.e.

VR1 exceeds the Vfail_VR1 level in less than Tshort_VR1 –

typ. 40 ms), NRES is still kept low until VR1 reaches its

reset level. After another 2 ms (parameter T_NRES), NRES

is released to high and the device enters Normal mode with

timeout watchdog.

In case VR1 does not start within Tshort_VR1, it’s again

disabled, SPI “VR1_FAIL” bit is set and the device enters

Fail-safe mode. The Fail-safe mode can be exited via any

valid wakeup event or by VS re-connection. The

initialization sequence is shown in Figure 12.

WAKEUP INPUT WU

NCV7429 offers an independent contact-monitoring

input WU which can be used either for Normal-mode

contact polling or for contact change detection during the

Standby and Sleep modes. In any mode, the WU input can

be configured into one of the following modes of operation:

• Static sense: the WU input is constantly monitored by

an input comparator and a filter of typ. 64 ms. In the

Normal mode, the result of the comparison (the input

high/low state) can be polled any time through the SPI

status bits. In the Standby and Sleep modes, a change of

the WU polarity (in any direction) is recognized as a

wakeup event. The MCU can then recognize the exact

WU wakeup source by reading “WU_WU” SPI status

bits.

During Init phase, the SWDM input is sampled. In case

SWDM is High, the Software Development mode is entered

and watchdog is disabled in all modes until the following Init

mode. SWDM pin can be sampled upon SPI request as well.

• Cyclic sense: the WU state detection is performed

periodically as fostered by one of the internal timers:

Timer 1 (period from 0.5 sec to 4 sec) or Timer 2

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NCV7429

Normal Mode

Fail-Safe Mode

In this mode the device provides full functionality, all

resources are available. The voltage regulator VR1 is able to

source 150 mA. MCU can enable/disable the device features

via SPI as well as monitor the status of the device.

VR1 level is monitored through reset and failure

comparators – see Figure 12. When the Normal mode is

entered, the watchdog is started in a timeout mode;

a window watchdog mode is applied after the first correct

watchdog service. The watchdog has to be correctly

triggered; otherwise a watchdog failure is detected resulting

in reset signal to the MCU. Afterwards, the watchdog is

re-started in the timeout mode. After eight consecutive

watchdog failures, the VR1 regulator is disabled for 200 ms

and re-started again. If the watchdog service still fails seven

more times, the device is put into Fail-safe mode. The

Fail-safe mode can then be exited either via a wakeup or VS

re-connection.

Fail-safe mode is the mode equals to the Sleep mode, but

all peripherals (VR1, OUT1−3, LS1/2) and the watchdog are

inactive.

The Fail-safe mode is entered after following failure

conditions:

• VR1 did not reach Vfail_VR1 level (typ. 2 V) within

Tshort_VR1 during startup (VS connection or wakeup

from Sleep mode)

• Fifteen consecutive watchdog failures occur

• The device junction temperature exceeded thermal

shutdown level Tjsd2 (typ. 155°C) for eight times

within one minute

Wakeup from Fail-safe mode is indicated by SPI flag

“FAIL-SAFE”.

Flash Mode

Flash mode is identical to the Normal mode with the

exception of the watchdog which operates in timeout mode.

The purpose of the Flash mode is to enable transfer of bigger

bulk of data between the MCU and a programming interface

– typically in the field. The Flash mode is entered by setting

dedicated SPI bit FLASH_RDY in CONTROL_2 register

followed by “MODE[1:0]” = 11b request.

Through SPI bits “MODE[1:0]”, the MCU can either keep

the device in the Normal mode, or request transition into one

of the low-power modes – Standby or Sleep.

Standby Mode

Standby mode is the first low-power mode. The voltage

regulator VR1 remains active while the watchdog is

disabled. The Standby mode is mainly intended to keep the

application powered (e.g. for RAM content preservation)

while the MCU is in a halt-state (software not running).

In order to make a safe transition into the Standby mode,

the watchdog will remain enabled even in the Standby mode

until the consumption from VR1 decreases below

Icmp_VR1_fall level (typ. 1.1 mA). When the VR1

consumption increases back above Icmp_VR1_rise level

(typ. 1.7 mA), the device will perform a wakeup from the

Standby mode to ensure supervision of the MCU software.

The current supervision of VR1 can be disabled via SPI by

setting the bit “ICMP_STBY”.

During the Standby mode, several types of wakeup events

can be signaled to the MCU through INTN pin: timer1 or

timer2 expiration, wakeup on LIN bus, change on WU pin

or SPI activity. SPI activity wakeup is not signaled through

INTN pin. The watchdog is started in timeout mode and

MCU can request a mode transition afterwards. VR1 also

continues to be monitored by the reset circuit, which will

generate a low NRES pulse in case the regulator output

drops below the reset level.

Software Development Mode

Software Development mode is identical to the Normal

mode with the exception of the watchdog which is disabled.

The purpose of the Software Development mode is to enable

software debugging without watchdog interaction or

transfer of bigger bulk of data between the MCU and

a programming interface

module-level production.

–

typically during the

The Software Development mode will be entered if the

voltage applied on SWDM pin exceeds the corresponding

comparison level Vin_SWDM in the Init phase or is SWDM

sampling is requested by “SWDM_SAMP” SPI bit.

Sampled SWDM state is latched in read-only “SWDM” SPI

bit. As SWDM pin is high-voltage tolerant, it might be tied

to the VS line through a protection resistor.

Sleep Mode

Sleep mode is the mode with the lowest consumption.

VR1 regulator and the watchdog are inactive. The device

maintains minimum operation allowing reception of

wake-up events generated by WU input, LIN bus line, or

driven by timer1 or timer2. In case of a wake-up event, the

device switches from the Sleep mode to the Normal mode

(through the Init mode, as the VR1 must be started similarly

to the VS power-up). SPI bit WD_TRIG is set to 0 after

a wakeup.

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NCV7429

Failure condition:

• TSD2 recovery

All controlregisters

set to default

VS < VS_POR

Fail−safe Mode

Init Mode

(transition mode)

All registers set to default

VR1: started −up

OUT1−3:per SPI

LS1/2: off

Watchdog : off

LIN : inactive

VR1: off

OUT1−3 : off

LS1/2 : off

Watchdog : off

LIN: wakeup detection

FSO : on

VS > VS_POR

Wakeup

All controlregisters

Un−Powered

All controlregisters

set to default

FSO: as per FSO generator

NRES: Low

NRES : Low

VR1 > Vfail_VR1 (typ. 2 V)

beforeTshort_VR1 (typ. 40 ms)

and SWDM< Vin_SWDM

VR1 > Vfail_VR1 (typ. 2 V)

beforeTshort_VR1 (typ. 40 ms)

and SWDM> Vin_SWDM

Fail−safe condition:

• VR1 < Vfail_VR1 after Tshort_VR1 (from Init ),

• 15 consecutive watchdog failures ,

• 8 consecutive TSD 2 events

Reset

(transition mode)

Reset

(transition mode)

Reset event:

• VR1 < VR1_RESx,

• watchdog failure

Reset event:

• VR1 < VR1_RESx

VR1: on

OUT 1−3 : per SPI

LS1/2: off

Watchdog: off

LIN : off

VR1: on

OUT 1− 3: per SPI

LS1/2: off

Watchdog: off

LIN : off

All controlregisters

set to default

All controlregisters

set to default

FSO : as per FSO generator

NRES: Low

FSO : as per FSO generator

NRES : Low

Normal Mode

Timeout Watchdog

Software Development

Mode

VR1: on

SWDM pin sample request

and

SWDM> Vin_SWDM

SWDM pin sample request

and

SWDM< Vin_SWDM

Watchdog off

OUT 1−3 : per SPI

LS1/2: off/on/PWM

Watchdog : timeout

LIN : normal communication

FSO : as per FSO generator

NRES : High

All other functions equal to Normal

mode incl. all mode transitions

Wakeup

SPI request to keep

Normal/ Flash

Normal/Flash Mode

Window/Timeout Watchdog

VR1: on

OUT 1−3 : per SPI

LS1/2: off/on/PWM

Watchdog : window /timeout

LIN : normal communication

FSO : as per FSO generator

NRES : High

Normal mode

SPI request

I(VR1) < Icmp_VR1 (if enabled)

and

Sleep mode

SPI request

no Wakeup request pending

Standby mode

SPI request

Standby Mode

Watchdog off

Standby Mode

Timeout Watchdog

Sleep Mode

VR1: off

OUT 1−3: per SPI

LS 1/2: off

VR1: on

OUT 1−3: per SPI

LS 1/ 2: off

VR1: on

OUT 1− 3: per SPI

LS1/2: off

Watchdog : timeout

LIN : wakeup detection / off

FSO : as per FSO generator

NRES : High

Watchdog : off

LIN: wakeup detection /off

FSO : as per FSO generator

NRES : Low

LIN : wakeup detection / off

FSO : as per FSO generator

NRES : High

I(VR1) > Icmp_VR1 (if enabled)

or

Wakeup

Figure 13. Principal Operating Modes

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NCV7429

WAKE-UP EVENTS

Every valid wakeup event starts the timeout watchdog,

which then must be correctly triggered. If another wakeup

event occurs during the initial timeout watchdog, the

watchdog is not re-started and another interrupt request

(pulse on INTN pin) is generated only if the corresponding

wakeup flag is located in different status register. E.g., LIN

wakeup will start the watchdog timeout timer while the

device remains in the Standby mode. If, for example, a WU

pin wakeup is then detected, it will be latched into the SPI

registers, but no new interrupt will be generated and the

watchdog will keep running. If VS_OUT overvoltage is

detected afterwards, new interrupt will be generated. This

example is shown in Figure 14 and Figure 15.

In all wakeup cases in the Standby mode, the device

remains in the Standby mode with watchdog running until

it is changed. SPI settings for drivers are applied after the

correct watchdog service.

In case LIN, WU pin and Timer1/2 wakeup sources are

disabled while the Standby or Sleep mode is entered through

a SPI request, LIN and WU wakeup is automatically enabled

(SPI bits “WU_LIN_DIS” and “WU_DIS” are ignored).

SPI wakeup flags have to be cleared before transition to

the Standby or Sleep mode is requested, otherwise

immediate wakeup occurs.

In the Standby and Sleep modes, NCV7429 can detect

several types of wake-up events summarized in Table 6:

• In the Sleep mode, a wakeup will cause initialization of

VR1 regulator and transition to a Reset mode. After the

release of the NRES signal, the timeout watchdog will

be started and the device enters the Normal mode – i.e.

the SPI settings for outputs will be applied immediately.

The following events will cause wakeup from the Sleep

mode:

♦ Bus wakeup through LIN – can be enabled/disabled

through SPI.

♦ Switch monitoring on WU input – can be configured

and enabled/disabled through SPI.

♦ Timer wakeup – timer1 and timer2 can be

configured to cause a wakeup after a fixed time

period – the selected timer is started at the moment

the Sleep mode is requested and causes wakeup

immediately when the selected time period expires.

The timer wakeup can be configured and

enabled/disabled by SPI.

♦ Thermal shutdown 1 – enabled if “WU_TSD” is set.

♦ OUT1−3 overcurrent – enabled if “WU_OC” is set.

♦ VS_OUT over-/under-voltage – enabled if

“WU_OVUV” is set.

• From the Standby mode, where VR1 remains active,

a wakeup event will cause watchdog startup in timeout

mode:

♦ SPI wakeup (CSN low and rising edge on SCLK).

Interrupt request is not generated.

♦ VR1 consumption wakeup (VR1 consumption

exceeds the Icmp_VR1_rise level; can be disabled by

SPI control). Interrupt request is generated. If VR1

consumption falls below the Icmp_VR1_fall level

within the timeout period, the watchdog is disabled

again.

♦ Bus wakeup through LIN, switch monitoring on

WU, timer wakeups, thermal shutdown 1, OUT1−3

overcurrent and VS_OUT over-/under-voltage have

the same meaning as in the Sleep mode. Any of

them will cause an interrupt request, if enabled.

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NCV7429

Table 6. WAKEUP EVENTS

NRES

Pulse

INTN

Pulse

Device Mode

Wakeup Event

SPI Default

SPI Control

SPI Flag

SPI

N/A

Cannot be Disabled

ICMP_STBY

WU_LIN_DIS

WU_DIS

N/A

No

I(VR1) > Icmp

Bus Wakeup (LIN)

WU Change

Timer1/2 Wakeup

TSD1

Enabled

Disabled

STATUS_0.WU_LIN

STATUS_0.WU_WU

STATUS_0.WU_TIM

STATUS_1.TSD1

Standby

No

WU_TIM_EN[1:0]

WU_TSD

Yes

STATUS_1.VS_OUT_OV,

STATUS_1.VS_OUT_UV

VS_OUT OV/UV

Disabled

WU_OVUV

WU_OC

OUT1−3 Overcurrent

STATUS_2.OUTx_OC

Bus Wakeup (LIN)

WU Change

Enabled

Disabled

WU_LIN_DIS

WU_DIS

STATUS_0.WU_LIN

STATUS_0.WU_WU

STATUS_0.WU_TIM

STATUS_1.TSD1

Timer1/2 Wakeup

TSD1

WU_TIM_EN[1:0]

WU_TSD

Sleep

Yes

No

STATUS_1.VS_OUT_OV,

STATUS_1.VS_OUT_UV

VS_OUT OV/UV

Disabled

WU_OVUV

WU_OC

OUT1−3 Overcurrent

STATUS_2.OUTx_OC

Bus Wakeup (LIN)

WU Change

Enabled

Disabled

STATUS_0.WU_LIN

STATUS_0.WU_WU

STATUS_0.WU_TIM

Cannot be Disabled

(settings ignored)

Fail-safe

No

Timer1/2 Wakeup

WU_TIM_EN[1:0]

Mode

Standby mode

Watchdog

off

0

timeout

off

1

0

SPI: WU_LIN

SPI: WU_WU

0

1

0

SPI: VS_OUT_OV

0

1

0

RxDL/

INTN

T_INTN

MCU stopped

MCU running

VR1 load

Figure 14. Interrupt Generation, VR1 Current Comparator Enabled

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NCV7429

Mode

Watchdog

Standby mode

off

0

timeout

1

0

SPI: WU_LIN

SPI: WU_WU

0

1

SPI: VS_OUT_OV

0

1

0

RxDL/

INTN

T_INTN

Figure 15. Interrupt Generation, VR1 Current Comparator Disabled

WATCHDOG

• Window: the watchdog time is split to two distinct parts

– a closed window, where the watchdog may not be

triggered, is followed by an open window where the

MCU must send a valid watchdog trigger. Window

watchdog is used during the Normal operating mode of

the device after the initial timeout watchdog is correctly

triggered. Position of the watchdog counter inside the

open window is reflected in SPI status bits

The on-chip watchdog requires that the MCU software

sends specific SPI messages (watchdog “triggers” or

“services”) in a specified time frame. A correct watchdog

trigger/service consists of a write access to SPI register

CONTROL_0 with “WD_TRIG” bit inverted compared to

its previous state. The watchdog timer re-starts immediately

after a successful trigger is received.

A read access to the CONTROL_0 register or a write

access with “WD_TRIG” bit unchanged does not trigger the

watchdog. The moment of the watchdog trigger corresponds

to the rising edge of the CSN signal (end of the SPI frame).

The watchdog can work in the following modes (see

Figure 4 and Figure 16):

• Off; the watchdog is always off in the Sleep and

Software development modes. It is also off in the

Standby mode, provided that the VR1 consumption

stays below the Icmp_VR1_rise limit, or when the Icmp

comparator is disabled.

• Timeout: the watchdog works as a timeout timer. The

MCU software must serve the watchdog any time

before the time-out expiration. Timeout watchdog is

started after reset events (power-up, watchdog failure,

VR1 under-voltage, thermal shutdown 2), by any

wakeup event from both Standby and Sleep mode and

in Flash mode. After NRES event, the timeout is typ.

65 ms, while in the Flash mode the timeout may be

selected via SPI. The timeout watchdog is started

regardless if the wakeup is or is not accompanied by a

reset. Watchdog counter position is reflected in SPI

status bits “WD_STATUS[1:0]”.

“WD_STATUS[1:0]”.

• Failure: If the watchdog is not triggered correctly

(trigger not sent during timeout or open window; or

sent during the closed window), reset is generated on

pin NRES and the “WD_TRIG” bit is reset to ”0”.

After the NRES release, the watchdog always starts in

the timeout mode. Watchdog failures are counted and

their number can be read from the SPI status registers

(bits “WD_CNT[3:0]”). After eight watchdog failures

in sequence, the VR1 regulator is switched off for

200 ms. In case of seven more watchdog failures, VR1

is completely turned off and the device goes into

Fail-safe mode until a wake-up occurs (e.g. via the LIN

bus). Second successful watchdog trigger (first in

window mode) resets the failure counter. Watchdog

failure handling is shown in Figure 17 and Figure 18.

The watchdog time for window mode is selectable from

four different values by SPI bits “WD_PER[1:0]”. The

watchdog time setting is applied only if it’s contained in an

SPI frame representing a correct watchdog trigger message.

The setting is ignored otherwise.

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NCV7429

Any reset even,t except WD failure

SPI bit WD_TRIG = 0

Init mode

(Standby requested

AND(I(VR1)<Icmp OR Icmp disabled))

OR Sleep requested

TIME−OUT Watchdog

No Failure

WD started as a timeout

HS drivers: as per SPI/ mode

LS drivers: as per SPI/ mode

LIN : as per SPI/ mode

WD trigger OK

Normal / Flash mode requested

FSO : off in no other failure occured

WD trigger OK

Wakeup

WD trigger failed

WINDOW Watchdog (Normal)

TIME−OUT Watchdog (Flash)

Watchdog OFF

WD started as window(closed+open) or

timeout

WD de−activated

HS drivers: as per SPI/ mode

LS drivers: SPI/ mode

LIN : as per SPI/ mode

FSO: off in no other failure occured

SPI counter WD_CNT cleared

HS drivers: as per SPI/ mode

LS drivers: as per SPI/ mode

LIN: as per SPI/ mode

WD trigger failed

FSO:off in no other failure occurred

HW condition

for Software Development mode

Watchdog failure

(transient state)

2 ms NRES pulse

SPI counter WD_CNT incremented

SPI bit WD_TRIG = 0

HS drivers: off

WD trigger OK

LS drivers: off

VR1 Off

(transient state)

LIN: off

FSO: on

WD trigger failed

VR1 off for 200 ms, WD de−activated

WD trigger

NRES

HS drivers: off

LS drivers: off

LIN : off

failed

VR1 re−initialized

after200 ms

released

after2 ms

AND

WD _CNT 8/15

0

FSO: on

WINDOW Watchdog (Normal)

TIME−OUT Watchdog (Flash)

Failure Recovery

TIME−OUT Watchdog

Failure Recovery

8 consecutive failures

(WD_CNT=8)

WD started as a timeout

HS drivers: off

LS drivers: off

LIN : off

WD started as window (closed+open) or

timeout

7 more consecutive failures

(WD_CNT=15)

HS drivers: off

LS drivers: off

LIN : as per SPI/ mode

FSO : on

WD trigger OK

Fail −safe Mode

OR

Flash mode request

VR1 off, WD de−activated

HS drivers: off

Wakeup

LS drivers: off

LIN : wakeup detection

FSO : on

Figure 16. Watchdog Operation

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NCV7429

Mode

Watchdog

Normal mode

Window watchdog

Timeout watchdog

Timeout wd

2

SPI: WD_CNT

0

1

2

0

Watchdog

services

missing watchdog services

T_wd_TO

T_wd_CW+ T_wd_OW

NRES

1^stwatchdog

failure

2^ndwatchdog

failure

watchdog services

restored

OUTx

/ LSx

OUTx, LS1/2

setting ignored

OUTx, LS1/2

setting ignored

FSO

Figure 17. Watchdog Failure − Isolated Events

Normal

Timeout Window

Mode

Watchdog

VR1 off

Fail−safe

15

Window

Timeout

0

1

2

7

8

9

14

15

0

SPI: WD_CNT

Watchdog

services

missing watchdog services

T_wd_TO

1^stwd

failure

2^ndwd

failure

8^thwd

failure

15^thwd

failure

wd services

restored

NRES

VR1

Toff_VR1

OUTx

/ LSx

OUTx, LSx

ignored

FSO

Figure 18. Watchdog Failure − Multiple Events

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NCV7429

PROTECTION

that the MCU can still take appropriate actions. Junction

temperature above the second shutdown level leads to

complete device de-activation, VR1 included and SPI

counter TSD_CNT[2:0] is incremented. VR1 is re-started

after a waiting time of 1 second in case the junction

temperature drops below the second shutdown level. If the

thermal shutdown then re-occurs seven more times, the

device is forced into the Fail-safe mode. TSD_CNT[2:0] is

decremented by one after each one minute without thermal

shutdown 2 event.

“TSD1” SPI flag has to be cleared to re-activate the high-

and low- side drivers. In the Standby and Sleep mode, the

interrupt request is generated to inform the microcontroller

about the thermal shutdown 1 event.

Thermal Protection

The device junction temperature is monitored in order to

avoid permanent degradation or damage. Three distinct

junction temperature levels are provided – thermal warning

level Tjw (typ. 135°C), thermal shutdown level 1 Tjsd1 (typ.

145°C) and thermal shutdown level 2 Tjsd2 (typ. 155°C).

The thermal protection circuit is always active in the Normal

and Standby mode. It is also active in the Sleep mode if any

of the high-side outputs is active.

When the junction temperature exceeds the warning level,

the event is only latched into the SPI for subsequent

diagnostics without any direct effect on the device

configuration. When the first thermal shutdown level is

exceeded, the most power-consuming functions are disabled

(high- and low- side drivers) while VR1 keeps running so

The details of the thermal protection handling are shown

in Figure 19, Figure 20 and Figure 21.

Sleep mode

with OUTx active

Normal mode

Standby mode

Junction Temperature OK

Wakeup

Junction Temperature OK

HS outputs: per SPI

LIN: wakeup detection

WU : per SPI

All functions unaffected

Tj > Tjw

TWAR bit

read& cleared

AND Tj< Tjw

Thermal Warning

(Normal mode, Standby mode)

(Sleep mode with OUTx active)

Wakeup

TWAR bit set in SPI

HS outputs: per SPI

LIN : wakeup detection

WU : per SPI

TWAR bit set in SPI

TSD1/2bit read& cleared

AND

All functions unaffected

Tj < Tjsd 1

Tj > Tjsd1

Thermal Shutdown 1

(Normal mode, Standby mode)

Thermal Shutdown 1

(Sleep mode with OUTx active)

TSD1 bit set in SPI

HS, LS drivers: permanently off

LIN: as per SPI/ mode

VR1: on

WU as per SPI/ mode

INTN pulse generated in Standby

TSD1 bit set in SPI

HS outputs: off

LIN: wakeup detection

WU : per SPI

VR 1 started

Wakeup

1 sec elapsed

AND

Tj > Tjsd 2

Tj < Tjsd 2

Thermal Shutdown 2

(Normal mode, Standby mode)

Fail −safe mode

TSD 2 bit set in SPI

SPI counter TSD_CNT incremented

HS, LS drivers: permanently off

LIN : off

SPI counter TSD_CNT= 7

HS, LS drivers: off

LIN : wakeup detection

VR1:off

VR 1: off

WU : no wakeup detection

FSO:on

WU : wakeup enabled

FSO : on

TSD 2 re−occured 8 times

(TSD 2 while TSD_CNT=7)

AND

Tj< Tjsd 2

Figure 19. Thermal Protection

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28

NCV7429

Mode

SPI: TW/TSD1/2

SPI: TSD_CNT

Tj

Normal mode

TSD2

i. R.

Normal mode

TW

0

TSD 1

TSD2

TSD 2

1

0

Tjds2

1 minute

Tjsd1

Tjw

high power

dissipation

normal

power dissipation

VR1

1s

NRES

OUTx

/ LSx

OUTx, LS1/2

setting ignored

FSO

Figure 20. Thermal Monitoring − Single Event

Normal mode

TSD2

i. R. N.

TSD2

1

TSD2

i. R. N.

TSD2

7

TSD2

Fail−safe

i. R. Normal

Mode

SPI: TW/TSD1/2

SPI: TSD_CNT

Tj

TW

0

TSD1

TSD 2

TSD2

7

1

2

7

Tjds2

Tjsd1

Tjw

high power

dissipation

high power

dissipation

high power

dissipation

normal power

dissipation

VR1

1s

NRES

OUTx

/ LSx

FSO

Figure 21. Thermal Monitoring − Multiple Events

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29

NCV7429

VS_OUT Over- and Under-Voltage

If the SPI control bit “LS_OVUV” is low, the same action

is taken for the low-side drivers. After the VS_OUT

under/over-voltage condition disappears, it remains flagged

in the SPI status. If the SPI control bit “VS_LOCK_DIS” is

low, the drivers will remain deactivated until the

corresponding flag is not read and cleared. If

“VS_LOCK_DIS” is high, the drivers will return to their

state defined by SPI registers settings. The details of the

VS_OUT monitoring are shown in Figure 22.

SPI control bit “VS_LOCK_DIS” is ignored by OUT3

driver in case it is controlled by FSO signal. OUT3 will

return to the previous state immediately after VS_OUT

under/over-voltage disappears.

In order to protect the loads connected to the high- and

low- side drivers, the VS_OUT (car battery) supply is

compared against two levels – under-voltage level

VS_OUT_UV (typ. 5.5 V) and VS_OUT_OV (typ. 21 V).

The VS_OUT monitoring circuitry is active in Normal mode

as well as in the Standby and Sleep modes.

Whenever VS_OUT falls below theVS_OUT_UV level or

raises above VS_OUT_OV level, all high-side drivers are

disabled. The under/over-voltage event is latched in the

corresponding SPI status bit and if SPI bit “WU_OVUV” is

set, the wakeup request is generated in Standby or Sleep

mode.

VS_OUT< VS_OUT_UV

VS_OUT> VS_OUT_OV

VS_OUT in range

VS_OUT Under−Voltage

VS_OUT Over−Voltage

VS_OUT_UV bit set

HS outputs: off

VS_OUT_OV bit set

HS outputs : off

HS, LS outputs: as per SPI

LSx: off if LS_OVUV bit = 0;

unaffected otherwise

LSx: off if LS_OVUV bit = 0;

unaffected otherwise

VS_OUT> VS_OUT_UV

AND

(VS_OUT_UV bit read and cleared

OR

VS_OUT< VS_OUT_OV

AND

(VS_OUT_OV bit read and cleared

OR

VS_LOCK_DIS bit=1)

Figure 22. Under- and Over-voltage on VS_OUT Supply

INTERRUPT SIGNAL

RESET SIGNAL NRES

NRES is an open-drain output with an internal pull-up

resistor connected to VR1. It signals reset to the MCU as

a consequence of several specific events:

• VR1 under-voltage (including VS power-up)

• Watchdog failure

• Thermal shutdown 2

• Sleep mode

An interrupt request is used in the Standby mode to

indicate some of the wakeup events to the MCU – see section

“Wake-up Events”. Interrupt is signaled through RxDL pin

by pulling it Low for typically 125 ms. Beside the 125 ms

Low pulse, RxDL/INTN remains High throughout the

Standby mode.

During Normal mode, RxDL/INTN assumes its normal

function (LIN received data).

• Wakeup from Sleep mode (the wakeup is accompanied

by reset – see Table 6; SPI control registers are not

cleared)

FAIL-SAFE (FSO) SIGNAL

A fail-safe signal is internally generated reflecting some

critical system failures and events. By default, the signal is

connected to the OUT3 output and over-rules the OUT3 SPI

settings – active FSO signal switches OUT3 on, inactive

FSO signal switches OUT3 off. In case the SPI bit

“FSO_DIS” is set, OUT3 acts as a general-purpose

high-side driver identically to OUT1 and OUT2. FSO

remains then only an internal signal not visible to the

application. SPI bit “FSO_DIS” is not cleared during any

reset event.

• Fail-safe mode

The low-level pulse on NRES pins always extends

T_NRES (typ. 2 ms) beyond the reset event – e.g. a watchdog

failure causes a 2 ms NRES low pulse; a VR1 under-voltage

causes NRES pulse extending

under-voltage disappearance.

2 ms beyond the

After NRES pulse caused by failure (not after wakeup

from Sleep mode), all outputs (OUT1−3, LS1/2) are inactive

and CONTROL SPI registers are cleared, except

“FSO_DIS” bit. After a wakeup from the Sleep mode,

registers content is preserved.

Both LIN transmission and reception is blocked during

NRES pulse. A recessive-to-dominant edge on TxDL pin

after NRES pulse is required to start transmission to the LIN

bus.

FSO internal signal is active after the following events:

• During the Init phase:

♦ VR1 short: FSO is active when VR1 is below its

failure level (Vfail_VR1) for more than Tshort_VR1

(typ. 40 ms) during VR1 regulator startup.

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30

NCV7429

♦ Thermal shutdown: FSO is active when the junction

• In the Normal and Standby modes:

temperature is above the second shutdown threshold

(Tjsd2). It is deactivated only when TSD2 status bit

is cleared.

♦ VR1 under-voltage: FSO is active when VR1 is

below its failure level (Vfail_VR1). It is deactivated

only when VR1_FAIL status bit is cleared.

♦ Watchdog: FSO is immediately activated in case of

failed watchdog trigger. It is deactivated only when

the watchdog is correctly triggered again for two

times.

• In the Fail-safe mode: FSO is always active. FSO is

deactivated only when corresponding SPI flag is

cleared.

SPI CONTROL

Serial Peripheral Interface (SPI) is the main

communication channel between the application MCU and

NCV7429. The structure of a SPI frame is shown in Figure

23. MCU starts the frame by sending an 8-bit header

consisting of two bits of register access mode type followed

by a six-bit address. During the header transmission,

NCV7429 sends out eight bits of status information

regardless the address. After the header, sixteen bits of data

are exchanged. A correct SPI frame has either no bits (no

SCLK edges during CSN low; serves to read out the global

status information) or exactly twenty-four bits. If another

amount of clock edges occurs during CSN low, the frame is

considered incorrect and the input data are always ignored.

Depending on the access type, the transmitted/received

data are treated differently:

data after a successful completion of the frame (rising

edge on CSN). Only the bits eligible for write access

are refreshed, the input data are ignored for the others

(e.g. a write access to status registers).

• For read access, the data on SDI are ignored; SDO

signals data content of the register addressed by the

header. After the frame completion, the register content

remains unchanged regardless the type of the individual

bits.

• For read & clear access, a normal register read is

performed. When the frame is completed (CSN rising

edge), the register bits eligible for read & clear access

are reset to 0.

• Device ROM access switches the address space to

sixteen-bit constant data memorized in the NCV7429

(indicating the device version, SPI frame format and

other information). Input data are ignored.

• During a write access, SDO signals current content of

the register while new data for the same register are

received on SDI. The register is refreshed with the new

SPI frame

Access

Type

Input Data

Byte 1

Input Data

Byte 0

valid

IN

Register Address

CSN

SCLK

SDI

RW1 RW0

A5

A4

A3

A2

A1

A0

DI14

DI2

DI1

DI0

DI15

FLT

res.

FLT

SPI

FLT

VS

FLT

VR1

FLT

TH

FLT

DRV

res.

SDO

DO14

DO2

DO1

DO0

X

DO15

GLOB

Address−dependent

Data

Device Status Bits

OUT

Figure 23. SPI Frame Structure

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31

NCV7429

SPI FRAME FORMAT

D23

D22

D21

D20

D19

D18

D17

D16

D15

...

D0

DI0

NCV7429 IN

RW1

RW0

A5

A4

A3

A2

A1

A0

DI15

NCV7429 OUT FLT_GLOB Reserved FLT_SPI

FLT_VS FLT_VR1 Reserved FLT_TH FLT_DRV DO15

DO0

Inframe:

RW1

RW0

Description

0

1

0

1

0

1

Write to SPI Register

Read Only from SPI Register

Read & Clear SPI Register

Access Device ROM

SPI Access Type

A5

0

1

A4

A3

0

A2

0

A1

0

A0

0

Register

CONTROL_0

SPI Access

0

1

X

Write, Read

0

1

CONTROL_1

CONTROL_2

CONTROL_3

CONTROL_4

Reserved

Write, Read

0

1

0

1

0

1

0

1

0

1

0

1

0

PWM_OUT1/2

PWM_OUT3

PWM_LS

Write, Read

SPI Registers

0

1

0

1

0

1

STATUS_0

STATUS_1

STATUS_2

Reserved

Read, Read & Clear

1

0

1

0

1

0

1

X

Reserved

A5

0

A4

0

A3

0

A2

0

A1

0

A0

0

Data Content

Comment

$4300

ID_HEADER

0

1

$0203

PRODUCT VERSION

PRODUCT CODE 1

PRODUCT CODE 2

0

1

0

$7400

0

1

$2900

Device ROM

0

1

0

Reserved

$0200

...

1

...

1

...

1

...

1

...

0

...

1

0

SPI_FRAME_ID

1

Reserved

Outframe:

SDO Bit

Bit Name

Bit Content

D23

D22

FLT_GLOB

Reserved

Logical combination (OR) of all following flags

0

Previous SPI frame faulty − wrong number of clocks or addressing a nonexistent

address

D21

FLT_SPI

General Device

Status Info

D20

D19

D18

D17

D16

FLT_VS

FLT_VR1

Reserved

FLT_TH

VS_OV OR VS_UV

Equal to VR1_FAIL bit

0

TSD2 OR TSD1 OR TWAR

FLT_DRV

OR combination of all overcurrent and underload bits of OUTx and LSx

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32

NCV7429

SPI REGISTER DETAILS

CONTROL_0 REGISTER

Address: 00h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

−

RW

−

RW

Access Type

Bit Name

MODE. MODE.

1

WD

TRIG

WD

ICMP

Res.

0

Res.

0

VR1

RES.1 RES.0

VR1

Res.

0

Res.

0

LIN

TXDL

TO.0

FSO

DIS

0

PER.1 PER.0 STBY

SLOPE TO.1

0

x

Reset Value

MODE.1

MODE.0

Operating Mode Request

0

1

0

1

0

Normal mode (window watchdog)

Go to Sleep mode

Mode Control

Go to Standby mode

Flash mode (time-out watchdog); preceding SPI command has to set

FLASH_RDY bit in CONTROL_2, otherwise mode is not changed

1

WD_TRIG

Watchdog Trigger Bit

Watchdog trigger set to 0; default state after wakeup from Sleep

Watchdog trigger set to 1

Watchdog Trigger

Bit

0

1

WD_PER.1

WD_PER.0

Configuration of the Watchdog Trigger Time

0

1

0

1

0

1

Trigger time = 9.75 ms (Normal mode) / Timeout = 16 ms (Flash mode)

Trigger time = 39 ms (Normal mode) / Timeout = 64 ms (Flash mode)

Trigger time = 97.5 ms (Normal mode) / Timeout = 160 ms (Flash mode)

Trigger time = 195 ms (Normal mode) / Timeout = 640 ms (Flash mode)

Watchdog Trigger

Time

ICMP_STBY

Disables the VR1 Current Comparator

Comparator is Enabled in Standby mode

Comparator is Disabled

Standby VR1

Comparator

0

1

VR1_RES.1

VR1_RES.0

Adjustment of the VR1 Reset Level

Set the reset threshold to typ. 4.5 V (91%)

Set the reset threshold to typ. 4.3 V (87%)

Set the reset threshold to typ. 3.9 V (79%)

Set the reset threshold to typ. 3.7 V (74%)

0

1

0

1

0

1

VR1 Reset Level

LIN Slope Control

LIN_SLOPE

Change of the LIN Slope

High slew rate (as per LIN specification)

Low slew rate

0

1

TxDL_TO.1

TxDL_TO.0

Dominant TxD Time-out Configuration of the LIN Interface

Set the timer to typ. 55 ms

0

1

0

1

0

1

TxDL Time-out

Timer

Set the timer to typ. 13 ms

Time-out timer disabled

FSO_DIS

OUT3/FSO Function

0

OUT3 pin is driven by internal FSO signal

FSO Function

Disable

OUT3 pins is a general-purpose high-side driver, setting not cleared during

Reset

1

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NCV7429

CONTROL_1 REGISTER

Address: 01h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

−

RW

−

RW

−

RW

−

RW

Access Type

Bit Name

Res.

0

WU

LIN

DIS

WU

TIM

EN.1

WU

TIM

EN.0

Res.

0

Res.

0

WU

DIS

Res.

0

Res.

0

WU

PUD

Res.

0

Res.

0

Res.

0

Res.

0

WU

T.1

WU

T.0

0

Reset Value

WU_LIN_DIS

Disables LIN Wakeup in Standby or Sleep Mode

LIN Wakeup

Disable

0

1

LIN Wakeup Enabled

LIN Wakeup Disabled

WU_DIS

Disables WU Input Wakeup in Standby or Sleep Mode

WU Input

Wakeup Disable

0

1

WU Input Wakeup Enabled

WU Input Wakeup Disabled

WU_PUD

WU Input Sink/Source Current Configuration

WU Input

Sink/Source

0

1

WU configured as current sink in all modes, if WU wakeup is enabled

WU configured as current source in all modes, if WU wakeup is enabled

WU_TIM_EN.[1:0]

Enables Cyclic (Timer Controlled) Wakeup from Standby or Sleep Mode

Timers 1/2 are not used as wakeup sources

Wakeup generated based on Timer 1

0

1

0

1

0

1

Timer Wakeup

Control

Wakeup generated based on Timer 2

Wakeup generated based on Timer 1

WU_T.[1:0]

Defines the Filter Configuration for Wake Input WU

0

1

Static sense with 64 μs filter time (static sense)

Timer 2 cyclic sense with sampling start 20 ms before off-state and 16 ms filter

time

WU Input Filter

Time

Timer 2 cyclic sense with sampling start 20 ms before off-state and 16 ms filter

time

1

0

1

Timer 1 cyclic sense with sampling start 20 ms before off-state and 16 ms filter

time

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NCV7429

CONTROL_2 REGISTER

Address: 02h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

−

RW

Access Type

Bit Name

FLASH SWDM

Res.

T2

T1

TPER.2 TPER.1 TPER.0 TON.1 TON.0 TPER.2 TPER.1 TPER.0 TON

RDY

SAMP

0

Reset Value

FLASH_RDY

Unlocks Flash Mode Entry

Flash mode request in CONTROL_0 register ignored

Flash mode may be entered by setting MODE.[1:0] to 11b in following SPI

0

1

Flash Ready

write request. This bit is automatically cleared by any following SPI write com-

mand.

SWDM_SAMP

SWDM Pin Sample Request

0

1

SWDM latched value preserved

SWDM Pin Sample

SWDM pin sample is requested. New SWDM value will be latched.

This bit is automatically cleared when the sampling is finished.

T2_TPER.[2:0]

Defines the Period of the Cyclic Sense Timer2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Period: 200 ms

Period: 50 ms

Period: 20 ms

Period: 10 ms

Timer2 Period

Period: 100 ms

Period: 150 ms

Reserved − if used, will be equal to the default value of 200 ms

T2_TON.[1:0]

Defines the On Time for the Cyclic Sense Timer2

0

1

0

ON time 100 ms

ON time 200 ms

ON time 1 ms

ON time 5 ms

1

0

1

Timer2 On-time

T1_TPER.[2:0]

Defines the Period of the Cyclic Sense Timer1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Period: 0.5 s

Period: 1.0 s

Period: 1.5 s

Period: 2.0 s

Period: 2.5 s

Period: 3.0 s

Period: 3.5 s

Period: 4.0 s

Timer1 Period

T1_TON

Defines the On Time for the Cyclic Sense Timer1

0

1

ON time 10 ms

ON time 20 ms

Timer1 On-time

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NCV7429

CONTROL_3 REGISTER

Address: 03h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

−

RW

−

Access Type

Bit Name

WU

TSD

WU

OC

WU

OVUV

Res.

0

Res.

0

Res.

0

Res.

0

Res.

0

VS

LS

LS2

ON.1

LS2

ON.0

LS1

ON.1

LS1

ON.0

Res.

0

Res.

0

LOCK OVUV

DIS

0

Reset Value

WU_TSD

Enables Thermal Shutdown 1 Wakeup

Thermal

Shutdown 1

Wakeup

0

1

TSD1 wakeup disabled

TSD1 wakeup enabled in Standby/Sleep mode

WU_OC

Enables OUT1−3 Overcurrent Wakeup

OUT1−3

Overcurrent

Wakeup

0

1

OUT1−3 overcurrent wakeup disabled

OUT1−3 overcurrent wakeup enabled in Standby/Sleep mode

WU_OVUV

Enables VS_OUT Over-/Under-voltage Wakeup

VS_OUT OV/UV wakeup disabled

VS_OUT OV/UV

Wakeup

0

1

VS_OUT OV/UV wakeup enabled in Standby/Sleep mode

VS_LOCK_DIS

Disables the Automatic VS_OUT Lockout

VS_OUT

UV/OV Lockout

0

1

Outputs will be reactivated only when the VS_OUT UV/OV flag is cleared

Outputs will be reactivated when VS_OUT UV/OV condition disappears

LS_OVUV

Enables LSx in Case of VS_OUT OV/UV

LS1/2 Active

in VS_OUT UV/OV

0

1

Disabled − LSx will be disabled in case of VS_OUT UV/OV

Enabled − LSx will remain in their previous state in case of VS_OUT UV/OV

LSx_ON.1

LSx_ON.0

Defines the Configuration of the Low-side LS1/2

Driver is off in all modes

0

1

0

1

0

Driver is on in Normal/Flash mode (off in other modes)

LS1/2 Driver

Control

Driver is controlled by its PWM setting in Normal/Flash mode (off in other

modes)

1

Reserved − if used, LSx will be off in all modes (equal to default)

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36

NCV7429

CONTROL_4 REGISTER

Address: 04h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

−

RW

−

Access Type

Bit Name

OUT1

HIGHR

Res.

0

Res.

0

Res.

0

OUT3 OUT3 OUT3 OUT2 OUT2 OUT2 OUT1 OUT1 OUT1

ON.2

Res.

0

Res.

0

Res.

0

ON.1

ON.0

ON.2

ON.1

ON.0

ON.2

ON.1

ON.0

0

Reset Value

OUT1_HIGHR

Enables Weaker Switch on OUT1 Output

0

1

“Normal-ohmic” configuration; typ. 5 W Ron; parameters equal to OUT2−3

OUT1 Switch

Strength

“High-ohmic” configuration; typ. 20 W Ron; lower underload threshold and

current limitation

OUTx_ON.[2:0]

Defines the Configuration of the High-side OUT1..3

Driver is off in all modes

0

1

0

1

0

Driver is on in Normal/ Flash, Standby and Sleep mode

Driver is cyclic on with the timing of Timer1 in Normal/Flash, Standby and

Sleep mode

0

1

0

1

0

Driver is cyclic on with the timing of Timer2 in Normal/Flash, Standby and

Sleep mode

OUT1−3 Driver

Control

Driver is controlled by the corresponding PWM unit in Normal/Flash, Standby

and Sleep mode

1

0

1

0

1

Reserved − if used, the driver is off in all modes (equal to default)

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NCV7429

PWM_OUT1/2 REGISTER

Address: 06h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

Access Type

Bit Name

FSEL

PW

FSEL

PW

OUT1 OUT1.6 OUT1.5 OUT1.4 OUT1.3 OUT1.2 OUT1.1 OUT1.0 OUT2 OUT2.6 OUT2.5 OUT2.4 OUT2.3 OUT2.2 OUT2.1 OUT2.0

0

Reset Value

PWM_OUT3 REGISTER

Address: 07h

Access: Write, Read

Bit

D15

D14

RW

PW

D13

RW

PW

D12

RW

PW

D11

RW

PW

D10

RW

PW

D9

RW

PW

D8

RW

PW

D7

−

D6

−

D5

−

D4

−

D3

−

D2

−

D1

−

D0

−

RW

Access type

Bit Name

FSEL

OUT3

Res.

OUT3.6 OUT3.5 OUT3.4 OUT3.3 OUT3.2 OUT3.1 OUT3.0

0

Reset Value

PWM_LS REGISTER

Address: 08h

Access: Write, Read

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RW

Access Type

Bit Name

FSEL

LS1

PW

LS1.6

PW

LS1.5

PW

LS1.4

PW

LS1.3

PW

LS1.2

PW

LS1.1

PW

LS1.0

FSEL

LS2

PW

LS2.6

PW

LS2.5

PW

LS2.4

PW

LS2.3

PW

LS2.2

PW

LS2.1

PW

LS2.0

0

Reset Value

FSEL_OUTx

FSEL_LSx

PWM Frequency Selector

PWM Frequency

0

1

Base frequency of PWM on the corresponding output f(PWM) = 150 Hz

Base frequency of PWM on the corresponding output f(PWM) = 200 Hz

PW_OUTx[6:0]

PW_LSx[6:0]

Duty Cycle Selector

Output Duty Cycle

$0 … $7F

Corresponding output is active with duty cycle PW_xxx[6:0] / 127

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NCV7429

STATUS_0 REGISTER

Address: 09h

Access: Read, Read & Clear

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R

R/RC

R

−

R/RC

R

Access Type

Bit Name

OP

COLD

WU

TIM

WU

LIN

SWDM

Res.

WU

WD

TSD

MOD.1 MOD.0 START

CNT.3 CNT.2 CNT.1 CNT.0 CNT.2 CNT.1 CNT.0

OPMOD.1

OPMOD.0

Operating Mode

0

Sleep or Fail-safe – latched; updated after first successful access to the regis-

ter

Operating Mode

0

1

0

1

Standby

Normal

Flash

COLD_START

Power on Reset Status

0

1

Cold start (= VS connection) not occurred

Cold Start

Cold start (= VS connection) occurred;

cleared after first successful access of the register

WU_TIM

WU_LIN

Remote Wake-up Source

No timer nor LIN wake-up occurred

LIN wake-up occurred

0

X

1

0

1

Wake-up Source

Recognition

X

Timer wake-up occurred

SWDM

Software Development Mode Status (SWDM Pin)

SWDM low during sampling – Normal watchdog operation

0

1

SWDM Status

SWDM high during sampling – Software Development mode entered

WU_WU

Local Wake-up Source (WU Pin)

No WU pin wake-up occurred

Wake-up Source

Recognition

0

1

WU pin wake-up occurred

WD_CNT.[3:0]

Number of Watchdog Failures

0

No watchdog failure encountered

Watchdog Failure

Counter

$1 … $E

Non-zero number of watchdog failures encountered;

cleared by second successful watchdog service

$F

Fail-safe mode entered due to 15 watchdog failures;

cleared by successful watchdog service

TSD_CNT.[2:0]

Number of VR1 Restarts after Thermal Shutdown 2

No VR1 restarts encountered

0

$1 … $6

$7

TSD2 VR1 Restart

Counter

Non-zero VR1 restarts encountered; decremented after 1 minute

Seven consecutive thermal shutdown 2 events, another TSD2 leads to

Fail-safe mode entry; decremented after 1 minute after wakeup if no another

TSD2 occurs

www.onsemi.com

39

NCV7429

STATUS_1 REGISTER

Address: 0Ah

Access: Read, Read & Clear

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R/RC

−

R

−

R/RC

−

R/RC

−

Access Type

Bit Name

FAIL

SAFE

Res.

WU

Res.

VR1

FAIL

Res.

VS

OUT

OV

VS

OUT

UV

TSD2

TSD1 TWAR

TO

TxDL

Res.

FAIL_SAFE

Wakeup from Fail-safe Mode

0

1

Fail-safe was not entered

Fail-safe Mode

Wakeup from Fail-safe mode

WU

0

Status of WU Input in Normal Mode

Status of WU

Input

WU is Low

WU is High

1

VR1_FAIL

Voltage Regulator VR1 Failure

0

1

No VR1 failure occurred

VR1 Failure

VR1 fails for at least 5 ms (VR1 < 2 V for > 5 ms) OR

(VR1 < 2 V at 40 ms after turn-on)

VS_OUT_OV

Overvoltage on VS_OUT Pin

VS_OUT has not been above the overvoltage limit

VS_OUT exceeded the overvoltage limit (latched)

VS_OUT

Overvoltage

0

1

VS_OUT_UV

Undervoltage on VS_OUT Pin

VS_OUT has not been below the undervoltage limit

VS_OUT fell below the undervoltage limit (latched)

VS_OUT

Undervoltage

0

1

TSD2

TSD1

TWAR

Thermal Warning/Shutdown

No thermal limit exceeded

0

1

0

1

0

1

Thermal warning encountered

Thermal shutdown 1 encountered

Thermal shutdown 2 encountered

Reserved

Thermal

Protection

Other Combinations

TO_TxDL

TxDL Dominant

No LIN transmitter timeout encountered

LIN transmitter timeout encountered

Permanent

Dominant

Protection

0

1

www.onsemi.com

40

NCV7429

STATUS_2 REGISTER

Address: 0Bh

Access: Read, Read & Clear

Bit

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

−

R

R/RC

−

R/RC

−

R/RC

Access Type

Bit Name

Res.

WD

LS2

OC

LS1

OC

Res.

OUT3 OUT2 OUT1

OC OC OC

Res.

OUT3 OUT2 OUT1

UL UL UL

STAT.1 STAT.0

WD_STAT.[1:0]

Watchdog Counter Status

Watchdog counter below 33% of acceptable interval (Note 1)

0

Watchdog

Counter Status

0

1

0

1

Watchdog counter above 33% and below 66% of acceptable interval (Note 1)

Reserved − not used

Watchdog counter above 66% of acceptable interval (Note 1)

1. Acceptable interval means timeout or open window interval

LSx_OC

OUTx_OC

Overcurrent Status of the Corresponding Output

No overcurrent encountered

Driver

Overcurrent

0

1

Overcurrent encountered

OUTx_UL

Underload Status of the Corresponding Output

No underload encountered

Driver

Underload

0

1

Underload encountered

www.onsemi.com

41

NCV7429

PACKAGE DIMENSIONS

TSSOP−20 EP

CASE 948AB

ISSUE O

B

NOTES:

D

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

DETAIL B

e/2

B

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.07 IN EXCESS OF THE LEAD WIDTH AT

MMC. DAMBAR CANNOT BE LOACTED ON THE

LOWER RADIUS OR THE FOOT OF THE LEAD.

4. DIMENSIONS b, b1, c, c1 TO BE MEASURED BE-

TWEEN 0.10 AND 0.25 FROM LEAD TIP.

5. DATUMS A AND B ARE ARE DETERMINED AT DATUM

H. DATUM H IS LOACTED AT THE MOLD PARTING

LINE AND COINCIDENT WITH LEAD WHERE THE

LEAD EXITS THE PLASTIC BODY.

0.20 C A-B

D

20

11

2X 10 TIPS

DETAIL B

E1

E

b

b1

6. DIMENSION D DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT

EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT

INCLUDE INTERLEAD FLASH OR PROTRUSION. IN-

TERLEAD FLASH OR PROTRUSION SHALL NOT EX-

CEED 0.15 PER SIDE. D AND E1 ARE DETERMINED

AT DATUM H.

D

c c1

PIN 1

REFERENCE

1

10

e

SECTION B−B

20X b

A

M

0.10

C A-B D

MILLIMETERS

TOP VIEW

DIM MIN

MAX

1.10

0.15

0.95

0.30

0.25

0.20

0.16

6.60

M

A

A1

A2

b

---

0.05

0.85

0.19

0.09

6.40

A2

A

0.05 C

0.08 C

B

DETAIL A

B

b1

c

END VIEW

c1

D

A1

SEATING

PLANE

20X

H

C

SIDE VIEW

P

E

6.40 BSC

E1

e

4.30

4.50

0.70

L2

0.65 BSC

GAUGE

PLANE

L

0.50

L2

M

0.25 BSC

0

8

_

SEATING

PLANE

P

---

4.20

L

P1

3.00

C

DETAIL A

SOLDERING FOOTPRINT

P1

4.30

BOTTOM VIEW

6.76

3.10

20X

0.98

20X

0.35

0.65

PITCH

DIMENSIONS: MILLIMETERS

www.onsemi.com

42

NCV7429

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NCV7429/D

◊

www.onsemi.com

43


型号：	NCV7429DE5R2G
厂家：	ONSEMI
描述：	System Basis Chip
文件：	总43页 (文件大小：612K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCV7429DE5R2G [ONSEMI]

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