NCV7683DQR2G [ONSEMI]
LED 驱动器，汽车，八路，100 mA 序列;
| 型号： | NCV7683DQR2G |
| 厂家： | 
ONSEMI |
| 描述： | LED 驱动器，汽车，八路，100 mA 序列 驱动 驱动器 |
| 文件： | 总24页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MARKING DIAGRAM
Enhanced 100 mA Linear
Current Regulator and
Controller for Automotive
Sequenced LED Lighting
NCV7683G
AWLYYWW
SSOP24 NB EP
CASE 940AP
NOTE: This marking style is specific to Case 940AP
NCV7683
NCV7683 = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The NCV7683 consists of eight linear programmable constant
current sources. The part is designed for use in the regulation and
control of LED based Rear Combination Lamps and blinking
functions for automotive applications. System design with the
NCV7683 allows for two programmed levels for stop (100% Duty
Cycle) and tail illumination (programmable Duty Cycle), or an
optional external PWM control can be implemented.
WL
YY
WW
G
MARKING DIAGRAM
LED brightness levels are easily programmed (stop is programmed
to the absolute current value, tail is programmed to the duty cycle)
with two external resistors. The use of an optional external ballast FET
allows for power distribution on designs requiring high currents. Set
back power limit reduces the drive current during overvoltage
conditions. This is most useful for low power applications when no
external FET is used.
Sequencing functionality is activated, controlled, and programmed
by individual pins. In addition to programming of the sequence
interval, the device can sequence 8 individual output channels, 4 pairs
of output channels, 2 quad output channels, or all 8 at once (for multi
IC use at high currents).
NCV7683
FAWLYWW
G
SSOP24 NB EP
CASE 940AQ
NOTE: This marking style is specific to Case 940AQ
NCV7683 = Specific Device Code
F
A
= Fab Location
= Assembly Location
= Wafer Lot
WL
Y
= Year
WW
G
= Work Week
= Pb−Free Package
Enhanced features of this device are a global enable function and
display sequencing.
The device is available in a SSOP−24 package with exposed pad.
ORDERING INFORMATION
†
Device
Package
Shipping
Features
NCV7683DQR2G* SSOP24−EP
(Pb−Free)
2500 /
Tape & Reel
• Constant Current Outputs for LED String Drive
• LED Drive Current up to 100 mA per Channel
• Open LED String Diagnostic with Open−Drain Output in All Modes
• Slew Rate Control Eliminates EMI Concerns
• Low Dropout Operation for Pre−Regulator Applications
• External Modulation Capable
• On−chip 800 Hz Tail PWM Dimming
• Single Resistor for Stop Current Set Point
• Single Resistor for Tail Dimming Set Point
• Overvoltage Set Back Power Limitation
• Improved EMC Performance
• Programmable Latch−Off function on Open String
♦ Restart Option of Unaffected Strings
• Over Temperature Fault Reporting
• Global Enable
• Display Sequencing
* Per PCN FPCN23658ZE, customers may receive
either case 940AP or 940AQ. Differentiation of the
case is based on the marking seen above.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Applications
• Rear Combination Lamps (RCL)
• Daytime Running Lights (DRL)
• Fog Lights
• Center High Mounted Stop Lamps (CHMSL) Arrays
• Turn Signal and Other Externally Modulated Applications
• Signature Lamp
• SSOP−24 Fused Lead Package with Exposed Pad
• AEC−Q100 Qualified and PPAP Capable
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April, 2022 − Rev. 4
NCV7683/D
NCV7683
Timer Circuit
Timer
Programming Current
VP
Output
Drive Control
ENABLE
Vref
200k
SEQTIME
SEQ1
SEQ2
8
1
7 65 4 3 2
SEQON
200k
DIAG
SEQOUT
Open Load
Detection
LO
Channel Control
Interface
CC
SEQOUT
VP
EMC Filter
UVLO
Vreg
Overvoltage
1 of 8
Ballast
Drive
Soft Start,
Bias and
Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
−
Reference
Output
Current
Drive
FB
Channel
Control
+
FET Drive
200K
200K
Over temperature &
Over voltage sense
Setback
Current
−20%
1V
Control Logic
50% IOUT
Open Load
Detect
Output
Latch−Off
STOP
DIAG
GND_Signal
GND_DRV
Vreg
x 150
Oscillator
and PWM
I
RSTOP
Irstop
−
+
2.2V
0.4V
CC
V−I Converter
Rtail
Pin
Current
Limit
−
+
Open
Circuit
Restart
1.8V
RTAIL
RSTOP
Figure 1. Block Diagram
DIAG
STOP
FB
Ballast Drive
VP
SEQ1
SEQ2
LO
RSTOP
RTAIL
ENABLE
SEQON
SEQOUT
OUT1
SEQTIME
OUT8
OUT7
OUT2
OUT6
OUT3
OUT5
GND_Signal
OUT4
GND_DRV
Figure 2. Pinout Diagram
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2
NCV7683
V
MRA4003T3G
MRA4003T3G
STRING
TAIL
SVD2955
STOP
C2
R3
1K
0.22uF
C3
100nF
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
C1
R1
VP
10K
0.68uF
Ballast
Drive
FB
STOP
DIAG
RSTOP
RTAIL
R4, 3.01K
R5, 1.62K
OUT7
OUT8
C4
10nF
R6
GND_Signal
GND_DRV
ENABLE
SEQOUT
SEQ1
9.53K
R7
1K
SEQ2
SEQON
SEQTIME
LO
R2
NCV7683
Figure 3. Application Diagram with External FET Ballast Transistor
R6 and R7 values shown yield 10.5 V regulation on V
C1 is for line noise and stability considerations.
C3 is for EMC considerations.
.
STRING
Unused OUTx channels should be shorted to ground as OUT7 shows in this example.
MRA4003T3G
V
STRING
TAIL
MRA4003T3G
STOP
C3
100nF
OUT1
C1
R1
VP
0.68uF
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
10K
Ballast
Drive
FB
STOP
DIAG
RSTOP
RTAIL
R4, 3.01K
C4
10nF
R5, 1.62K
GND_Signal
GND_DRV
ENABLE
SEQOUT
SEQ1
SEQ2
SEQON
SEQTIME
LO
R2
NCV7683
Figure 4. Application Diagram without the FET Ballast Transistor
When using the NCV7683 without the FET ballast transistor, tie the FB pin and Ballast Drive pin to GND.
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3
NCV7683
Table 1. APPLICATION I/O TRUTH TABLE
STOP
INPUT
TAIL
MODE
OUTx LATCH OFF
(w/ LO = GND)
OUTX
CURRENT
FAULT
STATE*
DIAG
STATE**
EN
1
SEQON
X
0
0
0
0
0
0
1
1
1
X
0
1
1
1
0
0
X
X
X
X
0
no
no
OFF
OFF
−
1
0
−
1
0
X
X
X
1
no
I
I
NORMAL
0
STOP
STOP
0
no
OPEN CIRCUIT***
OPEN CIRCUIT***
NORMAL
1
0
yes
no
OFF
PWM
PWM
1
0
0
0
1
no
OPEN CIRCUIT***
NORMAL
PWM
0
X
X
X
no
I
I
0
1
1
STOP
STOP
0
no
OPEN CIRCUIT***
OPEN CIRCUIT***
0
yes
OFF
Reference Figures below.
X = don’t care
0 = LOW
1 = HIGH
* Open Circuit, RSTOP Current Limit, Set Back Current Limit down 20%, and thermal shutdown
**Pull−up resistor to DIAG and SEQOUT required.
*** OPEN CIRCUIT = Any string or SEQOUT open.
DIAG
DIAG
Open String Occurs
Open String Removed
Open String Occurs
Open String Removed
on
OUTx
on
OUTx
Current
Current
off
off
on
OUTx
Current
on
OUTx
Outputs with no open string.
Current
Outputs with no open string.
off
off
Figure 5. DIAG timing diagram WITH
Open String Latch Active
All outputs latch off.
Figure 6. DIAG timing diagram WITHOUT
Open String Latch Active
No outputs are turned off.
DIAG will report the state.
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4
NCV7683
Sequence Programming Timing Diagrams
The four timing diagrams show the options available for sequencing of the 8 outputs dependent on the state of SEQ1 and SEQ2.
1. 8 individual sequence intervals.
2. 4 pairs of sequence intervals.
3. 2 quads of sequence intervals.
4. 1 single sequence interval.
Sequencing_on
Sequencing_on
ENABLE
ENABLE
OUT1
OUT1
(current)
(current)
OUT2
OUT2
(current)
(current)
Sequence
Interval
OUT3
OUT3
(current)
(current)
Sequence
Interval
OUT4
OUT4
(current)
(current)
OUT5
OUT5
(current)
(current)
OUT6
OUT6
(current)
(current)
OUT7
OUT7
(current)
(current)
OUT8
OUT8
(current)
(current)
SEQOUT
SEQOUT
Sequence Time
Sequence Time
Figure 7. Sequencing Timing Diagram
(SEQ1 = 0, SEQ2 = 0)
Figure 8. Sequencing Timing Diagram
(SEQ1 = 1, SEQ2 = 0)
Sequencing_on
Sequencing_on
ENABLE
ENABLE
OUT1
OUT1
(current)
(current)
OUT2
OUT2
(current)
(current)
OUT3
OUT3
(current)
(current)
OUT4
OUT4
(current)
(current)
OUT5
OUT5
(current)
(current)
Sequence
Interval
OUT6
OUT6
(current)
(current)
OUT7
OUT7
(current)
(current)
OUT8
OUT8
(current)
(current)
SEQOUT
SEQOUT
Sequence Time
Sequence Time
Figure 9. Sequencing Timing Diagram
(SEQ1 = 0, SEQ2 = 1)
Figure 10. Sequencing Timing Diagram
(SEQ1 = 1, SEQ2 = 1)
The sequencing function is triggered by a logic level high to low signal on the ENABLE pin.
0=ground
1=floating
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5
NCV7683
Table 2. PIN FUNCTION DESCRIPTION
SSOP−24 Exposed
Pad Package
Pin #
Label
Description
1
DIAG
Open−drain diagnostic output. Requires a pull−up resistor.
Reporting Open Circuit, RSTOP Current Limit,
Set Back Current Limit down 20%, and thermal shutdown.
Normal Operation = LOW.
Open Load reset input.
Ground if not used (only if latchoff is not used).
2
3
SEQ1
SEQ2
Grounding this pin changes the output sequencing.
Reference the sequencing section of the datasheet.
Grounding this pin changes the output sequencing.
Reference the sequencing section of the datasheet.
4
5
LO
Latch Off. Ground this pin for latch off function.
RSTOP
Stop current bias program resistor.
Referenced to ground (pin 12).
6
RTAIL
Tail current duty cycle PWM program resistor.
Referenced to ground (pin 12).
Ground pin if using external modulation.
7
8
SEQTIME
OUT8
Sequence Time program resistor.
Referenced to ground (pin 12).
Channel 8 constant current output to LED.
Unused pin should be grounded (pin 13).
9
OUT7
Channel 7 constant current output to LED.
Unused pin should be grounded (pin 13).
10
11
OUT6
Channel 6 constant current output to LED.
Unused pin should be grounded (pin 13).
OUT5
Channel 5 constant current output to LED.
Unused pin should be grounded (pin 13).
12
13
14
GND_Signal
GND_DRV
OUT4
Low Current Logic Ground.
High Current Driver Ground. Pin is fused to the epad.
Channel 4 constant current output to LED.
Unused pin should be grounded (pin 13).
15
16
17
18
OUT3
OUT2
Channel 3 constant current output to LED.
Unused pin should be grounded (pin 13).
Channel 2 constant current output to LED.
Unused pin should be grounded (pin 13).
OUT1
Channel 1 constant current output to LED.
Unused pin should be grounded (pin 13).
SEQOUT
Open−drain output. Requires a pull−up resistor. Follows ENABLE pin after delay of OUT8
with SEQON high.
19
20
21
22
SEQON
ENABLE
VP
High turns on 1−8 output sequencing.
Global enable input. Low turns device on.
Supply voltage input.
Ballast Drive
Gate drive for external power distribution PFET.
Ground if not used.
23
FB
Feedback Sense node for V
regulation.
STRING
Use feedback resistor divider or connect to GND.
24
STOP
epad
Stop Logic Input. External Modulation Input when VP is high.
Ground. Do not connect to pcb traces other than GND.
epad
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6
NCV7683
Table 3. MAXIMUM RATINGS (Voltages are with respect to device substrate.)
Rating
Value
Unit
Supply Input (VP, Ballast Drive, STOP, DIAG, ENABLE, SEQON, SEQOUT)
V
DC
−0.3 to 40
Peak Transient
40
Output Pin Voltage (OUTX)
−0.3 to 40
200
V
mA
mA
V
Output Pin Current (OUTX)
DIAG Pin Current
10
Input Voltage (RTAIL, RSTOP, FB, SEQTIME, SEQ1, SEQ2, LO)
−0.3 to 3.6
−40 to 150
260 peak
Junction Temperature, T
°C
°C
J
Peak Reflow Soldering Temperature: Lead−free
60 to 150 seconds at 217°C (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. ATTRIBUTES
Characteristic
Value
ESD Capability
Human Body Model
Machine Model
≥
≥
4.0 kV
200 V
Moisture Sensitivity (Note 1)
Storage Temperature
MSL3
−55 to 150°C
Package Thermal Resistance (Note 2)
SSOP24
Junction–to–Board, R
18°C/W
78°C/W
54°C/W
q
JB
Junction–to–Ambient, R
q
JA
Junction–to–Lead, R
q
JL
1. For additional information, see or download onsemi’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and
Application Note AND8003/D.
2
2. Values represent typical still air steady−state thermal performance on 1 oz. copper FR4 PCB with 645 mm copper area.
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7
NCV7683
Table 5. ELECTRICAL CHARACTERISTICS
(4.5 V < VP < 16 V, STOP = VP, RSTOP = 3.01 kW, RTAIL = 1.62 kW, RSEQTIME = 4.99 kW, −40°C ≤ T ≤ 150°C, unless otherwise specified.)
J
Characteristic
Conditions
Min
Typ
Max
Unit
GENERAL PARAMETERS
Supply Current (IOUTx = 50 mA)
STOP mode
mA
VP = 16 V
VP = 16 V
VP = 16 V, STOP = 0 V, OUTx = 0 mA,
Disconnected output
−
−
−
6
5
−
12
12
2.0
Tail mode
Fault mode
Driver Ground Pin Current (pin13)
Output Under Voltage Lockout
IOUT1 to IOUT8 = 50 mA
VP Rising
−
3.8
−
400
4.1
500
4.4
−
mA
V
Output Under Voltage Lockout
Hysteresis
200
mV
Open Load Disable Threshold
Open Load Disable Hysteresis
THERMAL LIMIT
7.2
7.7
8.2
V
−
200
−
mV
Thermal Shutdown
(Note 3)
(Note 3)
150
175
15
−
−
°C
°C
Thermal Hysteresis
−
CURRENT SOURCE OUTPUTS
Output Current
OUTX = 0.5 V
OUTX = 1 V, R
45
90
50
100
55
110
mA
= 1.5 K
STOP
Maximum Regulated Output Current
Current Matching
0.5V to 16V
100
−
−
mA
%
−4
0
4
2IOUTx(min)
ƪ
ƪ
* 1ƫ
* 1ƫ
100
100
IOUTx(min) ) IOUTx(max)
2IOUTx(max)
IOUTx(min) ) IOUTx(max)
Line Regulation
9 V ≤ VP ≤ 16 V
–
1.2
6.0
mA
Open Circuit Detection Threshold
25 mA
50 mA
25
35
50
50
75
65
% of Output
Current
Current Slew Rate
Iout = 44 mA, 10% to 90% points
@ 99% Iout
−
16.0
−
6
17.2
78
80
−
15
18.4
−
mA/ms
V
Overvoltage Set Back Threshold
Overvoltage Set Back Current
Diag Reporting of Set Back Current
Output Off Leakage
VP = 20 V (Note 4)
%Iout
%Iout
mA
−
−
EN = high
−
1
FET DRIVER
Ballast Drive
DC Bias
mA
V
FB = 1.5 V, Ballast Drive = 3 V
FB = 0.5 V, Ballast Drive = 3 V
−
1.0
13
2.4
20
Sink Current
4
Ballast Drive Reference Voltage
STOP / ENABLE / SEQON LOGIC
Input High Threshold
0.92
1.00
1.08
0.75
0.70
100
120
1.25
1.00
250
200
1.75
1.44
400
300
V
V
Input Low Threshold
V
IN
Hysteresis
mV
kW
Input Impedance
Vin = 14 V
3. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
4. The output current degrades at a rate of 8%/V.
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NCV7683
Table 5. ELECTRICAL CHARACTERISTICS
(4.5 V < VP < 16 V, STOP = VP, RSTOP = 3.01 kW, RTAIL = 1.62 kW, RSEQTIME = 4.99 kW, −40°C ≤ T ≤ 150°C, unless otherwise specified.)
J
Characteristic
SEQ1/SEQ2/LO LOGIC
Input High Threshold
Conditions
Min
Typ
Max
Unit
0.75
0.70
100
5
1.25
1.00
250
10
1.75
1.44
400
20
V
V
Input Low Threshold
V
IN
Hysteresis
mV
mA
Input Pull−up Current
CURRENT PROGRAMMING
RSTOP Bias Voltage
RSTOP K multiplier
SEQx = 0 V
Stop current programming voltage
0.94
1.00
150
1.06
V
−
−
−
I
/I
OUTX RSTOP
RSTOP Over Current Detection
RTAIL Bias Current
Duty Cycle
RSTOP = 0 V
0.70
290
1.00
330
1.45
370
mA
mA
%
Tail duty cycle programming current
RTAIL = 0.49 V
RTAIL = 0.76 V
RTAIL = 1.66 V
3.5
17
59.5
5
20
70
6.5
23
80.5
SEQTIME Voltage
0.94
1.00
1.06
V
DIAG / SEQOUT OUTPUT
Output Low Voltage
Output Active, I
= 1 mA
–
−
0.1
−
0.40
10
V
mA
V
DIAG,SEGOUT
DIAG Output Leakage
V
DIAG
= 5 V
Open Load Reset Voltage on DIAG
1.6
0.70
1.8
0.8
2.0
SEQOUT Open Load Detection
Threshold Voltage
0.90
V
SEQOUT Open Load Detection Sink
Current
10
20
35
mA
AC CHARACTERISTICS
Stop Turn−on Delay Time
Stop Turn−off Delay Time
PWM Frequency
V(STOP) > 1.75 V to I(OUTx) = 90%
V(STOP) < 0.75 V to I(OUTx) = 10%
STOP = 0 V
−
−
14
14
800
2
45
45
msec
msec
Hz
400
1
1200
4
Open Circuit to DIAG Reporting
4.8 mA pull−up to VP, V(DIAG) >1.5 V
SEQTIME = 1K to 10K
ms
Sequence Time / R
45.5
49
52.5
msec
kohm
SEQTIME
Sequence Re−Enable
Time / R
SEQTIME = 1K to 10K
45.5
0.55
49
52.5
1.2
msec
kohm
SEQTIME
VP Turn−on Time
0.80
msec
3. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100%
parametrically tested in production.
4. The output current degrades at a rate of 8%/V.
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NCV7683
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
20
53
52
51
50
49
48
10
0
RSTOP = 3.01 kW
T = 25°C
47
0
1
2
3
4
5
6
7
8
9
10
−40 −20
0
20 40 60 80 100 120 140 160
RSTOP (kW)
TEMPERATURE (°C)
Figure 11. Iout vs. RSTOP
Figure 12. Iout vs. Temperature
100
90
100
90
80
80
70
70
60
50
40
30
20
60
50
40
30
20
10
0
10
0
RSTOP = 3.01 kW
0
1
2
3
4
5
6
7
0
0.5
1.0
1.5
2.0
2.5
RTAIL (kW)
V(RTAIL)
Figure 13. Duty Cycle vs. RTAIL
Figure 14. Duty Cycle vs. V(RTAIL)
80
70
60
50
40
30
20
RTAIL = 5 kW
RTAIL = 2.3 kW
RTAIL = 1.5 kW
10
0
−40 −20
0
20
40 60 80 100 120 140 160
TEMPERATURE (°C)
Figure 15. Duty Cycle vs. Temperature
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NCV7683
TYPICAL CHARACTERISTICS
60
50
40
30
20
51.0
50.8
50.6
50.4
50.2
50.0
49.8
49.6
49.4
49.2
10
0
R
= 3.01 k
STOP
49.0
9
0
0
11
13
15
17
19
21
23
25
27
6
7
8
9
10 11 12
(V)
13 14 15 16
VP (V)
V
OUT
Figure 16. IOUT vs. VP
Figure 17. IOUT Line Regulation
60
50
40
30
20
60
50
40
30
20
10
0
10
0
2
4
6
8
10
12
14
16
0
0.1
0.2
0.3
0.4
0.5
V
(V)
V
OUT
(V)
OUT
Figure 18. IOUT vs. VOUT
Figure 19. IOUT vs. VOUT
14
12
10
8
500
450
400
350
300
250
200
150
100
6
4
per eq. 1
R7 = 1 kW
2
0
50
0
2K
4K
6K
8K
10K
12K 14K
0
1
2
3
4
5
6
7
8
9
10
R6 (W)
RSEQTIME (kW)
Figure 20. VSTRING vs. R6
Figure 21. (Sequence Time / Re−Enable Time)
vs. RSEQTIME
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NCV7683
TYPICAL CHARACTERISTICS
160
140
120
100
80
1 oz
2 oz
60
40
20
0
0
100
200
300
400
500
600
700
2
COPPER HEAT SPREADER AREA (mm )
Figure 22. qJA Copper Spreader Area
100
10
50%
20%
10%
5%
2%
1%
1
Single Pulse
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 23. Thermal Duty Cycle Curves on 645 mm2 Spreader Test Board
1000
100
10
2
50 mm
2
100 mm
2
500 mm
1
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 24. Single Pulse Heating Curve
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NCV7683
DETAILED OPERATING DESCRIPTION
General
Each output has its own sensing circuitry. An open string
The NCV7683 device is an eight channel LED driver
detection on any output latches off all 8 outputs when
programmed (LO = low). There are three means to reinitiate
the IC drivers.
whose output currents up to 100 mA/channel are
programmed by an external resistor. The target application
for the device is in automotive Rear Combination Lighting
(RCL) systems and blinking functions.
1. Forcing the DIAG pin below the Open Circuit
Reset Voltage (1.8 V typical).
The STOP logic input switches the two modes of the IC.
While in the STOP mode (high), the duty cycle of the outputs
is at 100%. When STOP is low, the duty cycle of the outputs
is programmed via an external resistor on the RTAIL pin.
A mixture of sequencing options is available using the
Sequencing ON, SEQ1, and SEQ2 pins. Sequencing options
include individual channels 1−8, 4 paired combinations, 2
quad combinations, and an all on delay. A logic output
(DIAG) communicates open circuit of the LED driver outputs
and SEQOUT back to the microprocessor. Both DIAG and
SEQOUT require a pull−up resistor for proper operation.
An optional external control for a ballast transistor helps
distribute the system power.
2. Toggling the ENABLE input
3. A complete power down of the device below the
Under Voltage Lockout threshold including
hysteresis (3.9 V typical).
Open Load Detection
Open load detection has an under voltage lockout feature
to remove the possibility of turning off the device while it is
powering up. The Open Load Disable Threshold is 7.7 V
(typ). Open load detection becomes active above this
threshold. Current is monitored internal to the NCV7683
device and an open load is flagged when the current is 1/2
of the targeted output current.
For multiple IC implementation of Open Load Detection
and preservation of the Latch Off feature, multiple ballast
transistors in series must be used as shown in Figure 25.
Interruption of any of the series devices will provide an all
off occurrence. The string voltage is set up by the feedback
in just the first device. Any subsequent devices should
connect their FB pin to ground. This will remove
competition of voltage regulation points of Vstring.
The part features an enable input logic pin.
LO (Latch Off) and DIAG
Automotive requirements sometime dictate all outputs
turn off if one of the outputs is an open circuit. This
eliminates driving with partial illuminated lights. The
module will either display all LED strings or no LED strings
at all. The option to turn all LED strings off with an open
circuit detect on any of the 8 outputs is programmed by
grounding the LO pin. This pin should be left open if this
feature is not required.
www.onsemi.com
13
NCV7683
D1
MRA4003T3G
TAIL
Q1
SVD2955
Q2
SVD2955
VSTRING
D2
MRA4003T3G
STOP
R1
1K
R2
D3
D4
D6
D7
D8
D9
D12
D13
D14
C2
0.22uF
C4
0.22uF
1K
1 -8
D10
C1
0.68uF
C3
0.68uF
C6
100nF
C5
100nF
D5
D11
OUT1-OUT8
OUT1-OUT8
OUT1
OUT1
Ballast Drive
VP
VP
Ballast Drive
OUT8
OUT8
R3
9.53K
FB
FB
R4
1K
GND
GND
NCV7683 U2
NCV7683 U1
Figure 25.
DIAG
pins specific to each customer application. The Ballast Drive
pin provides the drive in the feedback loop from the FB pin.
In steady state, the voltage is regulated at the feedback
voltage (FB). A simple voltage divider helps set the voltage
at Vstring. Unlike other systems, the ballast drive current
does not turn off in a leakage state when turned off (FB high),
but instead provides 1 mA of current providing a faster
response of the system loop. This sets the gate voltage of the
SVD2955 to 1 V at 25°C.
The logic DIAG pins main function is to alert the
controlling microprocessor an open string has occurred on
one of the outputs (DIAG high = open string). Reference
Table 1 for details on logic performance.
Open circuit conditions are reported when the outputs are
actively driven. When operating in STOP mode the DIAG
signal is a DC signal. When operating in TAIL the DIAG
signal is a PWM signal reporting open circuit when the
output drive is active.
Parallel Outputs
Ballast Drive
The maximum rating per output is 100 mA. In order to
increase system level LED string current, parallel
combinations of any number of outputs is allowed.
Combining all 8 outputs will allow for a maximum system
level string current design of 800 mA.
The use of an external FET device (SVD2955) helps
distribute the system power. A DC voltage regulation system
is used which regulates the voltage at the top (anode) of the
LED strings (Vstring). This has the effect of limiting the
power in the NCV7683 by setting the voltage on the IOUTx
www.onsemi.com
14
NCV7683
Unused Outputs
subsequent output (OUT8) has been pulled in (in time) as
shown by the 1st arrow. The 2nd arrow shows the SEQOUT
signal has also been pulled in (in time). For instances which
are coupled with others (in time) (e.g. SEQ1=1 and SEQ2=0
with OUT7 GND), there is no change in the ensuing
waveforms. Figure 27 shows there is no impact for channel
8 when OUT7 is not used.
Unused outputs should be shorted to ground. The
NCV7683 detects the condition during power−up using the
open load disable threshold and disables the open circuit
detection circuitry. The timing diagrams below highlight the
impacts in time with the sequencing function when an output
is not used. In this example (Figures 26 and 27), OUT7 is not
used and is grounded with SEQ1=0 and SEQ2=0. The
Sequencing_on
Sequencing_on
ENABLE
ENABLE
OUT1
OUT1
(current)
(current)
OUT2
OUT2
(current)
(current)
Sequence
Interval
OUT3
OUT3
(current)
(current)
Sequence
Interval
OUT4
OUT4
(current)
(current)
OUT5
OUT5
(current)
(current)
OUT6
OUT6
(current)
(current)
OUT7
OUT7
(current)
(current)
OUT8
OUT8
*
(current)
(current)
SEQOUT
*
SEQOUT
Sequence Time
Sequence Time
*Sequence interval unaffected.
Figure 26. Unused Output time shift.
(SEQ1=0, SEQ2=0)
Figure 27. Unused Output No Time Shift.
(SEQ1=1, SEQ2=0)
Sequencing
(STOP=0) (Figure 29) will revert to TAIL mode. A device
which was previously in STOP mode (STOP=1) Figure 30
will revert to STOP mode.
Before a sequence event, SEQOUT is high impedance.
After a sequence event, SEQOUT is high impedance.
Output sequencing is controlled by the SEQON,
SEQTIME, SEQ1, and SEQ2 pins. The SEQON pin must be
high to enable any of the sequencing functions. With the
SEQON pin in a low state, all 8 outputs turn on at the same
time and SEQOUT remains high all the time (via the
external pull−up resistor). The SEQ1 and SEQ2
programming pins are utilized by grounding them or leaving
them floating. They follow Table 6 (reference timing
diagrams in Figure 7, Figure 8, Figure 9, and Figure 10). The
sequence interval is defined by the delay of the ENABLE pin
going low to OUT2 turning on (OUT1 turns on coincident
with ENABLE). The same sequence time interval is present
for each additional sequential turn−on output of the IC.
Forcing an ENABLE high or SEQON low will cause a
device which is operating in the sequence mode to leave the
sequence mode. ENABLE going from low to high
(Figure 28) will turn off all outputs. With SEQON going
high to low (Figure 29 and Figure 30), operation will
continue as a device which is not using the sequence mode
feature. A device which was previously in TAIL mode
Sequence and Re−Enable Time Programming
Sequence time is programmed using a resistor from the
SEQTIME pin to ground. Figure 21 displays the expected
time using the program resistor. Acceptable values for the
resistor are between 1 K and 10 K. These provide 49 msec
and 490 msec times respectively.
The Sequence Re−Enable Time uses the same internal
timer as the Sequence Time. The Sequence Re−Enable Time
is provided to prevent an immediate feedback triggering in
a daisy chain setup. Reference Figures 33 and Figure 36 for
details.
The program resistor used can be calculated by using the
electrical parameters
1. Sequence Time / R
SEQTIME
2. Sequence Re−Enable Time / R
SEQTIME
www.onsemi.com
15
NCV7683
Sequence_Time
RSEQTIME
Example:
Electrical Parameter (typ)
Sequence Time / R
Sequence Time +
@ RSEQTIME
= 49 msec/kW
SEQTIME
R
= 1 kW
Sequence ReEnable_Time +
SEQTIME
Sequence Time = 49 * 1 = 49 msec
Sequence ReEnable_Time
RSEQTIME
@ RSEQTIME
Table 6. SEQUENCING COMBINATIONS
SEQON
SEQ1
SEQ2
Sequencing Functionality
All On
1
1
0
0
1
0
1
0
Dual Output Combination
Quad Combination
ENABLE
OUTx (V)
SEQOUT
Full 8 Channel Sequencing
0 = ground
1 = floating*
SEQON = 1
*Internal pull−up to the internal power supply.
Figure 28. Sequence Interrupt from EN
STOP
STOP
SEQON
SEQON
ENABLE
ENABLE
OUTx (V)
OUTx (V)
SEQOUT
SEQOUT
Figure 29. Sequence Interrupt from SEQON
(STOP=0)
Figure 30. Sequence Interrupt from SEQON
(STOP=1)
Daisy Chain
NCV7683 devices can be daisy−chained as shown in
Figure 32. Connections allow for a continuous stream of
devices including all delays attributed to the previous
sequence timing events from the previous integrated
circuits. This setup ripples the signal through all devices
until all devices are on. The example shows 3 devices, but
as many devices as desired may be used.
For retriggerable functionality such that once a signal
reaches the end of the daisy chain string, all devices turn off,
and the sequence starts again refer to Figure 33 or Figure 35.
The NCV7683 device utilizes a Sequence Re−Enable time
whereby a device turned off via the ENABLE pin will not
turn back on until the Sequence Re−Enable time has passed.
This allows all devices to turn off for a discernible time
before reinitiating the sequence. Additional time at the end
of the sequence can be achieved through the use of an
optional capacitor. If the optional capacitor does not provide
sufficient time at the end of the sequence, an NCV303
Voltage Detector can be added as shown in Figure 34.
Figure 36 shows the timing diagram associated with the
setup shown in Figure 33. As each NCV7683 device
receives a turn on signal through its ENABLE pin, the output
turns on an LED. There is an internal delayed response for
the SEQOUT pin to go low which delays the turn−on of the
next sequential LED. An alternative setup using NFET
transistors instead of PFET transistors is shown in
Figure 35.
An open circuit detection circuit is implemented (refer to
Figure 31) on the SEQOUT pin to enable the detection of the
condition (open circuit), report the condition back to the
www.onsemi.com
16
NCV7683
controller via the DIAG pin, and turn off all driver ICs in the
daisy chain eliminating any spurious lighting events.
SEQOUT is not active during STOP/TAIL modes
(SEQOUT=0).
+
−
Vol
VS
R1
Open Load
detection
10K
Sequence Output
Input Control
ENABLE
Sequence
Output
Iol
Output
Turn−on
Control
GND
NCV7683
NCV7683
IC2
IC1
Electronic module 1
Electronic module 2
Figure 31. Daisy Chain Interface between Multiple ICs
Table 7. APPLICATION SPECIFIC TRUTH TABLE
Input
Fault State
Condition
Current Sources
Status
ENB
OFF
SEQON
STOP
LO
DIAG
SEQOUT
1
X
X
X
X
1
Hi Z
ALL OFF
TURN
0
1
1
1
1
1
1
X
X
X
X
X
X
X
NORMAL
BIAS ERROR
OPEN CIRCUIT
TSD
0
1
1
1
1
1
ACTIVE
ACTIVE
ACTIVE
Hi Z
SEQUENCING
SEQUENCING
SEQUENCING
ALL OFF
0
X
0
OPEN
0
X
0
SHORT TO GROUND
X
OPEN CIRCUIT
SEQOUT OPEN
Hi Z
ALL OFF
0
Hi Z
SEQUENCING
STOP
0
0
0
0
0
0
1
1
1
1
1
X
NORMAL
BIAS ERROR
OPEN CIRCUIT
TSD
0
1
1
1
1
0
0
0
0
0
ALL ON
ALL ON
ALL ON
ALL OFF
ALL OFF
0
X
0
OPEN
0
X
0
SHORT TO GROUND
OPEN CIRCUIT
TAIL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
NORMAL
BIAS ERROR
OPEN CIRCUIT
TSD
0
0
0
0
0
0
ALL PWM
ALL PWM
ALL PWM
ALL OFF
ALL OFF
X
1
PWM
1
OPEN
X
SHORT TO GROUND
OPEN CIRCUIT
1
BIAS ERROR = 20% current foldback (via overvoltage on VP and/or over temperature) or RSTOP current limit.
www.onsemi.com
17
NCV7683
VBAT
OUT
OUT
OUT
10K
10K
10K
ENABLE SEQOUT
ENABLE SEQOUT
ENABLE SEQOUT
NCV7683
NCV7683
NCV7683
IC1
IC2
IC3
Figure 32. Daisy Chain Sequencing
5V
VBAT
R8
10k
OUT
OUT
OUT
R9
R2
R3
3.9k
R1
10k
10k
10k
R7, 10k
ENABLE SEQOUT
SEQON
ENABLE SEQOUT
SEQON
ENABLE SEQOUT
SEQON
(Turn Control)
(optional)
NCV7683
NCV7683
NCV7683
R4
R5
R6
10k
10k
10k
IC1
IC2
IC3
5V
Figure 33. Retriggerable Daisy Chain Sequencing using the Sequence Re−Enable Time
www.onsemi.com
18
NCV7683
5V
VBAT
R8
10k
R9
OUT
OUT
OUT
10k
R2
R3
R7
10k
10k
Reset
Input
NCV303
10k
R7, 10k
CD
ENABLE SEQOUT
SEQON
ENABLE SEQOUT
SEQON
ENABLE SEQOUT
SEQON
(Turn Control)
NCV7683
NCV7683
NCV7683
R4
10k
R5
R6
10k
10k
IC1
IC2
IC3
5V
Figure 34. Extending the End of Sequence Time
STOP
TAIL
VBAT
TURN
OUT
OUT
OUT
R9
10k
R2
R3
R7
10k
10k
10k
ENABLE
SEQON
ENABLE
SEQON
ENABLE
SEQON
SEQOUT
SEQOUT
SEQOUT
NCV7683
NCV7683
NCV7683
R4
10k
R6
10k
R5
10k
IC1
IC2
IC3
Figure 35. Alternate Retriggerable Daisy Chain Sequencing using Sequence Re−Enable Time
www.onsemi.com
19
NCV7683
TURN
ENABLE1
Re−Enable Time
I
out1−4
I
out5−8
Sequence
Interval
Sequence
Interval
SEQOUT
1
ENABLE2
I
out1−4
I
out5−8
SEQOUT
2
ENABLE3
I
out1−4
I
out5−8
SEQOUT
3
Figure 36. Sequencing Timing Diagram with Re−Enable Time Delay
www.onsemi.com
20
NCV7683
Programmability
Duty Cycle will vary according to the changes in RTAIL
Voltage and RTAIL Bias Current (generated from the current
through RSTOP).
Voltage errors encompass generator errors (0.4 V to
2.2 V) and comparator errors and are included in testing as
the Duty Cycle. Typical duty cycle measurements are 5%
with RTAIL = 0.49 V and 70% with RTAIL = 1.66 V.
RTAIL Bias Current errors are measured as RTAIL Bias
Current and vary as 290 mA (min), 330 mA (typ), and 370 mA
(max) with RSTOP = 3.01 kW.
The error duality originating from both the internal current
source generated on the RSTOP pin and the comparator
voltage thresholds of the RTAIL pin combined with the
choice of duty cycle levels make it difficult to specify duty
cycle minimum and maximum limits, but worst case
conditions can be calculated when considering the variation
in the voltage threshold and current source. Duty Cycle
variation must include the direct duty cycle as specified in
the electrical parameter table plus an additional error due to
the Irstop current which generates this voltage in the system.
Strings of LEDs are a common configuration for RCL
applications. The NCV7683 provides eight matched outputs
allowing individual string drive with current set by a single
resistor. Output currents are mirrored and matched within
4% at hot temperature.
A high STOP condition sets the output current using
equation 1 below.
A low STOP condition, modulates the output currents at
a duty cycle (DC) programmed using equation 2 below.
Note, current limiting on RSTOP limits the current which
can be referenced from the RSTOP Pin. Exceeding the
RSTOP Current Limit will set the output current to less than
100 mA, and the DIAG Pin will go high. This helps limit
output current (brightness and power) for this type of fault.
The average ISTOP Duty Cycle current provides the
dimmed tail illumination function and assures a fixed
brightness level for tail. The PWM generator’s fixed
frequency (800 Hz typ.) oscillator allows flicker−free
illumination. PWM control is the preferred method for
dimming LEDs.
RSTOP Over Current Protection
The diagnostic function allows the detection of an open in
any one of the output circuits. The active−low diagnostic
output (DIAG) is coincident with the STOP input and the ON
state in the tail mode. DIAG remains high (pulled up) if an
open load is detected in any LED string when STOP is high.
Over Current protection has been included for the RSTOP
pin. Without protection, the device performance could cause
excessive high current and potential damage to the external
LEDs. Detection of the RSTOP over current event (RSTOP
to ground) is 1 mA (typ) and is current limited to 2.2 mA
(typ). Output drive currents will limit to typically 65 mA.
Note – A feature of the NCV7683 device includes
operation of the device during a short circuit on the RSTOP
pin. Iout is decreased during the STOP condition and the
TAIL duty cycle is reduced to less than 40% by reducing the
voltage on the RTAIL pin to 2/3 of normal operation.
Output Current Programming
Reference Figure 11 (typ performance graph) to choose
programming resistor (RSTOP) value for stop current.
Reference Figure 13 Typical Performance Graph (Duty
Cycle vs. RTAIL) to choose a typical value programming
resistor for output duty cycle (with a typical RSTOP value
of 3.01 kW). Note the duty cycle is dependent on both
RSTOP and RTAIL values. RSTOP should always be
chosen first as the stop current is only dependent on this
value.
Set Back Current
Automotive battery systems have wide variations in line
supply voltage. Low dropout is a key attribute for providing
consistent LED light output at low line voltage. Unlike
adjustable regulator based constant current source schemes
where the set point resistor resides in the load path, the
NCV7683’s set point resistor lies outside the LED load path,
and aids in the low dropout capability.
Alternatively, the equations below can be used to calculate
a typical value and used for worst case analysis.
Set the Stop Current using RSTOP
RSTOP_Bias_Voltage
I
OUTX + 150 @
(eq. 1)
RSTOP
Setback Current Limit is employed during high voltage.
During a Setback Current Limit event, the drive current is
reduced resulting in lower power dissipation on the IC. This
occurs during high battery voltage (VP > 16 V). In this way
the NCV7683 can operate in extreme conditions and still
provide a controlled level of light output The Setback
Current (−20%) condition is reported on the DIAG Pin.
Activation of the set back current feature provides a
roll−off rate of −8%/V.
RSTOP Bias Voltage = 1 V (typ)
Set the Duty Cycle (DC) using RTAIL
RTAIL + 1.8 @ RSTOP(DC ) 0.22)
(eq. 2)
DC = duty cycle expressed in fractional form. (e.g. 0.50
is equivalent to 50% duty cycle) (ground RTAIL when using
external modulation)
Output Current is directly tested per the electrical
parameter table to be 10% (with RSTOP = 3.01 KW) or
45 mA (min), 50 mA (typ), 55 mA (max) at room and hot
temperature.
www.onsemi.com
21
NCV7683
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AP
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
A2
h
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.75
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B
D
D
8.64 BSC
NOTE 8
D2
E
2.37
2.67
D2
6.00 BSC
3.90 BSC
1.79 1.99
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
RECOMMENDED
SOLDERING FOOTPRINT
L1
L2
M
NOTE 8
0
8
_
_
2.72
BOTTOM VIEW
24X
1.15
2.19
6.40
1
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
www.onsemi.com
22
NCV7683
PACKAGE DIMENSIONS
SSOP24 NB EP
CASE 940AQ
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
0.20 C A-B
NOTE 4
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
BE 0.10 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE
FOOT. DIMENSION b APPLIES TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.10 TO 0.25
FROM THE LEAD TIP.
NOTE 6
D
L1
A
24
13
2X
H
L2
0.20 C
GAUGE
PLANE
4. DIMENSION D DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 PER SIDE. DIMENSION D IS
DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25 PER
SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
E1
E
L
A1
NOTE 5
PIN 1
SEATING
PLANE
DETAIL A
C
NOTE 7
REFERENCE
1
12
0.20 C
e
2X 12 TIPS
24X b
B
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
NOTE 6
M
0.12
C A-B D
7. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
8. CONTOURS OF THE THERMAL PAD ARE UN-
CONTROLLED WITHIN THE REGION DEFINED
BY DIMENSIONS D2 AND E2.
TOP VIEW
DETAIL A
A
h
A2
h
0.10 C
0.10 C
M
MILLIMETERS
DIM MIN
MAX
1.75
0.10
1.65
0.30
0.20
c
A
A1
A2
b
---
0.00
1.10
0.19
0.09
A1
SEATING
PLANE
END VIEW
24X
C
SIDE VIEW
c
M
0.15
C A-B D
D
8.64 BSC
NOTE 8
D2
E
2.50
2.70
D2
6.00 BSC
3.90 BSC
1.80 2.00
0.65 BSC
0.25 0.50
0.40 0.85
1.00 REF
0.25 BSC
E1
E2
e
M
0.15
C A-B
D
h
L
E2
L1
L2
M
NOTE 8
0
8
_
_
RECOMMENDED
SOLDERING FOOTPRINT*
3.00
BOTTOM VIEW
24X
1.15
2.20
6.40
1
24X
0.40
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
23
NCV7683
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