NLV74HC11ADR2G [ONSEMI]
三路 3 输入 AND 门极;
| 型号： | NLV74HC11ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 三路 3 输入 AND 门极 |
| 文件： | 总6页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC11A
Triple 3-Input AND Gate
High−Performance Silicon−Gate CMOS
The MC74HC11A is identical in pinout to the LS11. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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Features
MARKING
DIAGRAMS
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 V to 6 V
• Low Input Current: 1 mA
14
SOIC−14
D SUFFIX
CASE 751A
HC11AG
AWLYWW
14
14
• High Noise Immunity Characteristic of CMOS Devices
1
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
1
14
1
TSSOP−14
DT SUFFIX
CASE 948G
HC
11A
1
ALYW
ꢀ
1
A1
2
13
12
6
ꢀ
B1
C1
Y1
Y2
Y3
A
= Assembly Location
= Wafer Lot
3
4
5
A2
B2
C2
WL, L
YY, Y
Y = ABC
= Year
WW, W = Work Week
G or = Pb−Free Package
ꢀ
9
(Note: Microdot may be in either location)
A3
B3
C3
8
10
11
PIN ASSIGNMENT
PIN 14 = V
CC
PIN 7 = GND
A1
B1
1
2
14
13 C1
12
V
CC
Figure 1. Logic Diagram
A2
B2
3
4
Y1
11 C3
10 B3
C2
Y2
5
6
9
8
A3
Y3
GND
7
FUNCTION TABLE
Inputs
Output
Y
A
B
C
L
X
X
H
X
L
X
H
X
X
L
L
L
L
H
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
June, 2013 − Rev. 3
MC74HC11A/D
MC74HC11A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to +7.0
CC
V
−0.5 to V +0.5
V
in
CC
V
out
−0.5 to V +0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
SOIC Package
TSSOP Package
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
−55
+125
°C
ns
t , t
Input Rise and Fall Time
(Figure 2)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
r
f
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2
MC74HC11A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
− 55 to
V
V
CC
25°C
v 85°C
v 125°C
Symbol
Parameter
Test Conditions
= 0.1 V or V − 0.1 V
|I | v 20 mA
Unit
V
IH
Minimum High−Level Input
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
Voltage
out
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V − 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
CC
|I | v 20 mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
OL
Maximum Low−Level Output
V
in
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
Voltage
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
0.1
1
1.0
10
1.0
40
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
CC
in
CC
I
= 0 mA
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
− 55 to
25°C
V
V
CC
v 85°C
v 125°C
Symbol
Parameter
Unit
t
,
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 2 and 3)
2.0
3.0
4.5
6.0
95
45
19
16
120
60
145
75
ns
PLH
t
PHL
24
20
29
25
t
t
,
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
pF
pF
TLH
THL
19
C
Maximum Input Capacitance
−
10
10
10
in
Typical @ 25°C, V = 5.0 V
CC
27
C
Power Dissipation Capacitance (Per Gate)*
PD
*Used to determine the no−load dynamic power consumption: P = C
V
2f + I
V
.
D
PD CC
CC CC
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3
MC74HC11A
TEST POINT
OUTPUT
t
t
f
r
V
INPUT
CC
90%
50%
10%
DEVICE
UNDER
TEST
A, B, OR C
GND
C *
L
t
t
PHL
PLH
90%
50%
10%
OUTPUT Y
*Includes all probe and jig capacitance
t
t
THL
TLH
Figure 3. Test Circuit
Figure 2. Switching Waveforms
A
B
C
Y
Figure 4. Expanded Logic Diagram
(1/3 of the Device)
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC11ADG
SOIC−14
(Pb−Free)
55 Units / Rail
2500 / Tape & Reel
96 Units / Tube
MC74HC11ADR2G
MC74HC11ADTG
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
MC74HC11ADTR2G
NLV74HC11ADR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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4
MC74HC11A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0 ꢁ
8 ꢁ
0 ꢁ
8 ꢁ
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74HC11A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C
A
DETAIL A
h
X 45ꢁ
A
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0 ꢁ
M
A1
e
M
7ꢁ
0 ꢁ
7ꢁ
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HC11A/D
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