NLV74HC132ADTR2G [ONSEMI]
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs;
| 型号： | NLV74HC132ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input NAND Gate with Schmitt-Trigger Inputs 栅 |
| 文件： | 总9页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High−Performance Silicon−Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
http://onsemi.com
MARKING
DIAGRAMS
14
Features
PDIP−14
N SUFFIX
CASE 646
MC74HC132AN
AWLYYWWG
14
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
1
1
14
SOIC−14
D SUFFIX
CASE 751A
HC132AG
AWLYWW
• High Noise Immunity Characteristic of CMOS Devices
14
• In Compliance with the Requirements as Defined by JEDEC
1
Standard No. 7A
1
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
14
HC
132A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
14
1
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
1
Compliant
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
A1
B1
1
2
14
13 B4
12
V
CC
W, WW = Work Week
Y1
A2
3
4
A4
G or G
= Pb−Free Package
11 Y4
10 B3
(Note: Microdot may be in either location)
B2
Y2
5
6
FUNCTION TABLE
9
8
A3
Y3
GND
7
Inputs
Output
Y
A
B
L
L
H
H
L
H
L
H
H
H
L
Figure 1. Pin Assignment
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 15
MC74HC132A/D
MC74HC132A
1
A1
3
6
8
Y1
2
4
B1
A2
Y2
5
9
B2
A3
Y = AB
Y3
Y4
10
12
B3
A4
11
13
B4
PIN 14 = V
CC
PIN 7 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
†
Device
Package
Shipping
MC74HC132ANG
PDIP−14
(Pb−Free)
25 / Tape & Ammo Box
MC74HC132ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74HC132ADR2G
MC74HC132ADTG
MC74HC132ADTR2G
NLV74HC132ADG*
NLV74HC132ADR2G*
NLV74HC132ADTG*
NLV74HC132ADTR2G*
SOIC−14
(Pb−Free)
2500 / Tape & Reel
96 Units / Rail
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
55 Units / Rail
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
2500 / Tape & Reel
96 Units / Rail
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
http://onsemi.com
2
MC74HC132A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Positive DC Supply Voltage
Digital Input Voltage
ꢀ0.5 to ꢁ7.0
ꢀ0.5 to ꢁ7.0
ꢀ0.5 to ꢁ7.0
CC
V
V
IN
V
OUT
DC Output Voltage
Output in 3−State
High or Low State
V
ꢀ0.5 to V
ꢁ 0.5
CC
I
Input Diode Current
ꢀ20
mA
mA
mA
mA
mA
_C
IK
I
Output Diode Current
DC Output Current, per Pin
ꢂ
2
0
OK
I
ꢂ
2
5
OUT
I
DC Supply Current, V and GND Pins
ꢂ
7
5
CC
CC
I
DC Ground Current per Ground Pin
Storage Temperature Range
ꢂ
7
5
GND
T
ꢀ65 to ꢁ150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
_C
L
T
ꢁ
1
5
0
_C
_C/W
J
q
14−PDIP
14−SOIC
14−TSSOP
78
125
170
JA
P
D
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
V
ESD
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
ꢃ2000
ꢃ100
ꢃ500
V
I
Latch−Up Performance
Above V and Below GND at 85_C (Note 4)
ꢂ
3
0
0
mA
Latch−Up
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
Max
Unit
V
V
CC
6.0
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
V
CC
V
T
A
ꢀ55
−
ꢁ
1
2
5
_C
ns
t , t
No Limit
(Note 5)
r
f
5. When V ꢄ 0.5 V , I >> quiescent current.
IN
CC CC
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
http://onsemi.com
3
MC74HC132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
= 0.1 V
OUT
V
*55_C to 25_C
ꢅ85_C ꢅ125_C Unit
V
T+
max Maximum Positive−Going
Input Threshold Voltage
(Figure 5)
V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
V
|I
| ꢅ 20 mA
OUT
V
T+
min Minimum Positive−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= 0.1 V
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
OUT
|I
| ꢅ 20 mA
V
T–
max Maximum Negative−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= V – 0.1 V
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
OUT
CC
|I
| ꢅ 20 mA
V
T–
min Minimum Negative−Going
Input Threshold Voltage
(Figure 5)
V
OUT
= V – 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
OUT
CC
|I
| ꢅ 20 mA
V max Maximum Hysteresis
V
OUT
= 0.1 V or V – 0.1 V
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
H
OUT
CC
Voltage
|I
| ꢅ 20 mA
(Note 7)
(Figure 5)
V min
Minimum Hysteresis
Voltage
(Figure 5)
V
OUT
= 0.1 V or V – 0.1 V
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
H
OUT
CC
|I
| ꢅ 20 mA
(Note 7)
V
OH
Minimum High−Level
Output Voltage
V
OUT
ꢅ
V
min or V max
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IN
T−
T+
|I
| ꢅ 20 mA
V
IN
ꢅ
−V min or V max
T− T+
|I
| ꢅ 4.0 mA
OUT
| ꢅ 5.2 mA
OUT
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
|I
V
OL
Maximum Low−Level
Output Voltage
V
OUT
≥ V max
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
T+
|I
| ꢅ 20 mA
V
V
V
≥ V max
|I
|I
| ꢅ 4.0 mA
OUT
| ꢅ 5.2 mA
OUT
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IN
IN
T+
I
Maximum Input Leakage
Current
= V or GND
6.0
ꢂ
0
.
1
ꢂ
1
.
0
ꢂ
1
.
0
mA
mA
IN
CC
I
Maximum Quiescent
Supply Current
(per Package)
= V or GND
6.0
1.0
10
40
CC
IN
CC
I
= 0 mA
OUT
7. V min ꢃ (V min) ꢀ (V max); V max = (V max) ꢁ (V min).
H
T+
T−
H
T+
T−
http://onsemi.com
4
MC74HC132A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
V
CC
Guaranteed Limit
Symbol
Parameter
V
*55_C to 25_C
ꢅ85_C ꢅ125_C Unit
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
2.0
4.5
6.0
125
25
155
31
190
38
ns
ns
pF
PLH
t
PHL
21
26
32
t
,
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
—
10
10
10
in
Typical @ 25°C, V = 5.0 V
CC
C
Power Dissipation Capacitance (per Gate) (Note 8)
24
pF
PD
2
8. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
TEST POINT
OUTPUT
t
t
f
r
V
CC
90%
50%
10%
INPUT
A OR B
DEVICE
UNDER
TEST
GND
t
t
PLH
C *
L
PHL
90%
50%
10%
Y
t
t
THL
TLH
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
http://onsemi.com
5
MC74HC132A
4
3
2
V typ
H
1
2
3
4
5
6
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
V typ = (V typ) - (V typ)
H
Tꢀ+
Tꢀ-
Figure 5. Typical Input Threshold, VT+, VT− Versus Power Supply Voltage
V
CC
V
CC
V
H
V
H
V
Tꢀ+
V
Tꢀ-
V
Tꢀ+
V
Tꢀ-
V
IN
V
IN
GND
GND
V
OH
V
OH
V
OUT
V
OUT
V
OL
V
OL
V
CC
V
OUT
V
IN
(a)ꢁA SCHMITT TRIGGER SQUARES UP INPUTS
(a)ꢁWITH SLOW RISE AND FALL TIMES
(b)ꢁA SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
Figure 6. Typical Schmitt−Trigger Applications
http://onsemi.com
6
MC74HC132A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C
A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MC74HC132A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
J1
K
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
−T−
H
G
0
8
0
8
DETAIL E
_
_
_
_
D
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MC74HC132A
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74HC132A/D
相关型号：
©2020 ICPDF网 联系我们和版权申明