NLV74HC139ADR2G [ONSEMI]
Dual 1-of-4 Decoder/ Demultiplexer;
| 型号： | NLV74HC139ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual 1-of-4 Decoder/ Demultiplexer |
| 文件： | 总10页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC139A
Dual 1-of-4 Decoder/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 1−of−4 decoders, each of
which decodes a two−bit Address to one−of−four active−low outputs.
Active−low Selects are provided to facilitate the demultiplexing and
cascading functions. The demultiplexing function is accomplished by
using the Address inputs to select the desired device output, and
utilizing the Select as a data input.
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC139AN
AWLYYWWG
16
16
1
1
Features
16
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
SOIC−16
D SUFFIX
CASE 751B
HC139AG
AWLYWW
1
1
16
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
TSSOP−16
DT SUFFIX
CASE 948F
HC
139A
ALYWG
G
16
No. 7 A
1
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
1
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
July, 2012 − Rev. 11
MC74HC139A/D
MC74HC139A
2
4
5
6
7
Y0
Y1
Y2
Y3
ADDRESS
INPUTS
A0
A1
a
a
3
a
ACTIVE−LOW
OUTPUTS
a
SELECT
1
2
16
15
V
a
CC
a
a
A0
a
SELECT
b
3
4
14
13
A1
Y0
Y1
Y2
A0
a
a
a
a
b
A1
b
b
b
b
b
PIN 16 = V
PIN 8 = GND
CC
1
SELECT
a
5
6
7
8
12 Y0
11
10
9
Y1
Y2
Y3
14
13
12
11
10
9
ADDRESS
INPUTS
Y0
b
Y1
b
Y2
b
Y3
b
A0
A1
b
Y3
a
ACTIVE−LOW
OUTPUTS
b
GND
Figure 1. Pin Assignment
FUNCTION TABLE
15
SELECT
b
Figure 2. Logic Diagram
Inputs
Outputs
Y0 Y1 Y2 Y3
Select A1 A0
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
X = don’t care
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC139ANG
PDIP−16
2000 Units / Box
48 Units / Rail
(Pb−Free)
MC74HC139ADG
SOIC−16
(Pb−Free)
MC74HC139ADR2G
MC74HC139ADTR2G
NLV74HC139ADR2G*
NLV74HC139ADTR2G*
SOIC−16
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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2
MC74HC139A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
(Referenced to GND)
ꢀ
0
.
5
t
o
ꢁ
7
.
0
V
IN
DC Input Voltage
(Referenced to GND)
ꢀ1.5 to V ꢁ1.5
V
CC
V
OUT
DC Output Voltage
(Referenced to GND) (Note 1)
ꢀ
0
.
5
t
o
V
ꢁ
0
.
5
V
CC
I
DC Input Current, per Pin
DC Output Current, per Pin
ꢂ20
ꢂ25
ꢂ50
ꢂ50
mA
mA
mA
mA
_C
IN
I
OUT
I
DC Supply Current, V Pin
CC
CC
I
DC Ground Current per Ground Pin
Storage Temperature Range
GND
T
STG
ꢀ65 to ꢁ150
260
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
_C
L
T
ꢁ
1
5
0
_C
_C/W
J
q
PDIP
SOIC
TSSOP
78
112
148
JA
P
D
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
ꢃ2000
ꢃ200
ꢃ1000
V
I
Latchup Performance
Above V and Below GND at 85_C (Note 5)
ꢂ
3
0
0
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
6.0
V , V
IN OUT
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
V
CC
V
T
A
ꢀ
5
5
ꢁ
1
2
5
_C
ns
t , t
Input Rise and Fall Time
(Figure 3)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
MC74HC139A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
= 0.1 V or V ꢀ0.1 V
V
*55_C to 25_C ꢄ85_C ꢄ125_C Unit
V
IH
Minimum High−Level Input
V
OUT
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
OUT
CC
Voltage
|I
| ꢄ 20 mA
V
IL
Maximum Low−Level Input
V
OUT
= 0.1 V or V ꢀ0.1 V
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
OUT
CC
Voltage
|I
| ꢄ 20 mA
V
OH
Minimum High−Level Output
V
OUT
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IN
IH
Voltage
|I
| ꢄ 20 mA
V
IN
= V or V
|I
|I
| ꢄ 4.0 mA
OUT
| ꢄ 5.2 mA
OUT
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
IL
V
OL
Maximum Low−Level Output
Voltage
V
OUT
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
IL
|I
| ꢄ 20 mA
V
V
V
= V or V
|I
|I
| ꢄ 4.0 mA
OUT
| ꢄ 5.2 mA
OUT
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
IN
IN
IH
IL
I
Maximum Input Leakage
Current
= V or GND
6.0
ꢂ
0
.
1
ꢂ
1
.
0
ꢂ
1
.
0
mA
mA
IN
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
6.0
4
40
160
CC
IN
CC
I
= 0 mA
OUT
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
V
CC
Guaranteed Limit
Symbol
Parameter
V
*55_C to 25_C ꢄ85_C ꢄ125_C Unit
t
t
t
,
Maximum Propagation Delay, Select to Output Y
(Figures 1 and 3)
2.0
4.5
6.0
115
23
145
29
175
35
ns
ns
ns
pF
PLH
t
PHL
20
25
30
,
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 3)
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
PLH
t
PHL
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
TLH
t
THL
C
Maximum Input Capacitance
−
10
10
10
in
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
C
Power Dissipation Capacitance (Per Decoder) (Note 8)
55
pF
PD
2
8. Used to determine the no−load dynamic power consumption: P = C
V
f ꢁ I
V
.
D
PD CC
CC CC
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4
MC74HC139A
t
t
r
f
VALID
50%
VALID
V
CC
90%
V
CC
50%
INPUT A
SELECT
10%
GND
GND
t
t
PLH
PHL
t
t
PHL
PLH
90%
50%
10%
OUTPUT Y
50%
OUTPUT Y
t
t
TLH
THL
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 5. Test Circuit
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5
MC74HC139A
PIN DESCRIPTIONS
ADDRESS INPUTS
inputs. A high level on this input forces all outputs to a high
level.
A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13)
OUTPUTS
Address inputs. These inputs, when the respective 1−of−4
decoder is enabled, determine which of its four active−low
outputs is selected.
Y0a − Y3a, Y0b − Y3b (Pins 4 − 7, 12, 11, 10, 9)
Active−low outputs. These outputs assume a low level
when addressed and the appropriate Select input is active.
These outputs remain high when not addressed or the
appropriate Select input is inactive.
CONTROL INPUTS
Selecta, Selectb (Pins 1, 15)
Active−low select inputs. For a low level on this input, the
outputs for that particular decoder follow the Address
SELECT
Y0
Y1
A0
Y2
Y3
A1
Figure 6. Expanded Logic Diagram
(1/2 of Device)
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6
MC74HC139A
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
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7
MC74HC139A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74HC139A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T
U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MC74HC139A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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