NTB35N15 [ONSEMI]
Power MOSFET 37 Amps, 150 Volts N-Channel Enhancement-Mode D2PAK; 功率MOSFET 37安培， 150伏特N沟道增强模式D2PAK
| 型号： | NTB35N15 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 37 Amps, 150 Volts N-Channel Enhancement-Mode D2PAK |
| 文件： | 总12页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTB35N15
Product Preview
Power MOSFET
37 Amps, 150 Volts
N–Channel Enhancement–Mode D2PAK
Features
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• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
37 AMPERES
150 VOLTS
50 mW @ VGS = 10 V
• I
and R
Specified at Elevated Temperature
DSS
DS(on)
2
• Mounting Information Provided for the D PAK Package
Typical Applications
N–Channel
• PWM Motor Controls
D
• Power Supplies
• Converters
G
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol Value Unit
S
Drain–to–Source Voltage
V
150
150
Vdc
Vdc
Vdc
DSS
DGR
Drain–to–Source Voltage (R = 1.0 MW)
V
GS
MARKING DIAGRAM
& PIN ASSIGNMENT
Gate–to–Source Voltage
– Continuous
V
"20
"40
GS
– Non–Repetitive (t v10 ms)
V
GSM
p
4
Drain Current
– Continuous @ T = 25°C
Adc
Drain
I
D
I
D
37
23
A
4
– Continuous @ T = 100°C
A
– Pulsed (Note 2)
I
111
DM
1
2
NTB35N15
LLYWW
Total Power Dissipation @ T = 25°C
Derate above 25°C
Total Power Dissipation @ T = 25°C (Note 1)
P
178
1.43
2.0
Watts
W/°C
Watts
3
A
D
2
D PAK
CASE 418B
STYLE 2
A
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche
T , T
J
–55 to
+150
°C
stg
2
1
3
Drain
Gate
Source
E
700
mJ
AS
Energy – Starting T = 25°C
J
NTB35N15= Device Code
(V = 100 Vdc, V = 10 Vdc,
DD
GS
LL
= Location Code
= Year
I
= 21.6 A, L = 3.0 mH, R = 25 W)
G
L(pk)
Y
Thermal Resistance
– Junction–to–Case
°C/W
°C
WW
= Work Week
R
R
R
0.7
62.5
50
q
JC
JA
JA
– Junction–to–Ambient
– Junction–to–Ambient (Note 1)
q
q
ORDERING INFORMATION
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
L
Device
Package
Shipping
2
NTB35N15
D PAK
50 Units/Rail
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu. Area 0.412 in ).
2. Pulse Test: Pulse Width = 10 m s, Duty Cycle = 2%.
2
2
NTB35N15T4
D PAK
800/Tape & Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
May, 2002 – Rev. 2
NTB35N15/D
NTB35N15
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 250 m Adc)
Temperature Coefficient (Positive)
150
–
–
240
–
–
GS
D
mV/°C
m Adc
Zero Gate Voltage Drain Current
I
DSS
(V = 0 Vdc, V = 150 Vdc, T = 25°C)
–
–
–
–
5.0
50
GS
DS
J
(V = 0 Vdc, V = 150 Vdc, T = 125°C)
GS
DS
J
Gate–Body Leakage Current (V = ±20 Vdc, V = 0)
I
–
–
±100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
DS(on)
DS(on)
V
DS
= V I = 250 m Adc)
GS, D
2.0
–
2.9
–8.56
4.0
–
Temperature Coefficient (Negative)
mV/°C
Static Drain–to–Source On–State Resistance
R
V
W
(V = 10 Vdc, I = 18.5 Adc)
–
–
0.042
–
0.050
0.120
GS
D
(V = 10 Vdc, I = 18.5 Adc, T = 125°C)
GS
D
J
Drain–to–Source On–Voltage
(V = 10 Vdc, I = 18.5 Adc)
Vdc
–
–
1.55
26
1.78
–
GS
D
Forward Transconductance (V = 10 Vdc, I = 18.5 Adc)
g
FS
mhos
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(V = 25 Vdc, V = 0 Vdc,
C
–
–
–
2275
450
90
3200
650
pF
ns
DS
GS
iss
f = 1.0 MHz)
C
oss
Reverse Transfer Capacitance
C
175
rss
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn–On Delay Time
Rise Time
(V = 120 Vdc, I = 37 Adc,
t
d(on)
–
–
–
–
–
–
–
20
125
90
35
225
175
210
100
–
DD
D
V
GS
= 10 Vdc,
t
r
R
= 9.1 W)
G
Turn–Off Delay Time
Fall Time
t
d(off)
t
120
70
f
Total Gate Charge
Gate–to–Source Charge
Gate–to–Drain Charge
(V = 120 Vdc, I = 37 Adc,
Q
nC
DS
D
tot
gs
gd
V
GS
= 10 Vdc)
Q
Q
14
32
–
BODY–DRAIN DIODE RATINGS (Note 3)
Diode Forward On–Voltage
(I = 37 Adc, V = 0 Vdc)
V
–
–
1.00
0.88
1.5
–
Vdc
ns
S
GS
SD
(I = 37 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(I = 37 Adc, V = 0 Vdc,
t
rr
–
–
–
–
170
112
58
–
–
–
–
S
GS
dI /dt = 100 A/m s)
S
t
a
t
b
Reverse Recovery Stored Charge
Q
1.14
m
C
RR
3. Pulse Test: Pulse Width = 300 m s max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
NTB35N15
70
70
60
T = 25°C
J
V
= 10 V
V
DS
≥ 10 V
GS
60
V
GS
= 5.5 V
V
GS
= 9 V
50
40
30
20
50
40
30
20
V
= 8 V
GS
V
= 7 V
GS
V
= 5 V
GS
T = 100°C
J
V
GS
= 6 V
V
GS
= 4.5 V
T = 25°C
J
10
0
10
0
V
= 4 V
9
T = –55°C
J
GS
0
1
2
3
4
5
6
7
8
10
2
3
4
5
6
7
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
GS
, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.055
0.05
T = 25°C
J
V
GS
= 10 V
0.08
T = 100°C
J
V
GS
= 10 V
0.06
0.04
0.045
0.04
V
GS
= 15 V
T = 25°C
J
0.02
0
0.035
0.03
T = –55°C
J
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
2.25
2.0
10,000
1000
V
GS
= 0 V
T = 150°C
J
I
V
= 18.5 A
D
= 10 V
GS
1.75
1.5
1.25
1.0
100
10
T = 100°C
J
0.75
0.5
0.25
0
–50 –25
0
25
50
75
100 125
150
30 40 50 60 70 80 90 100 110 120 130 140150
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
J
V
DS
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
NTB35N15
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V – V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V – V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
6000
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
5000
4000
3000
C
iss
C
rss
C
iss
2000
1000
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTB35N15
1000
12
10
8
120
100
80
60
40
20
0
V
= 75 V
DD
I = 37 A
Q
T
D
V
GS
= 10 V
V
DS
t
f
V
t
GS
d(off)
Q
Q
t
r
1
2
6
100
4
t
d(on)
2
I
= 37 A
T = 25°C
D
J
10
0
0
10
20
30
40
50
60
70
1
10
100
Q , TOTAL GATE CHARGE (nC)
G
R , GATE RESISTANCE (OHMS)
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
V
= 0 V
GS
T = 25°C
35
30
25
20
15
J
10
5
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 m s. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
exceed (T
– T )/(R ).
currents below rated continuous I can safely be assumed to
J(MAX)
C
q
J
C
D
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
equal the values indicated.
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NTB35N15
SAFE OPERATING AREA
1000
700
600
V
= 20 V
I = 21.6 A
D
GS
SINGLE PULSE
T = 25°C
C
100
10
10 m s
500
400
300
200
100
0
100 m s
1 ms
10 ms
dc
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
10
100
1000
25
50
75
100
125
150
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
t
1
READ TIME AT t
1
0.01
t
2
T
J(pk)
– T = P
R
q
(t)
JC
C
(pk)
DUTY CYCLE, D = t /t
1
2
SINGLE PULSE
0.0001
0.01
0.00001
0.001
0.01
t, TIME (m s)
0.1
1.0
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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NTB35N15
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.24
0.42
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
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NTB35N15
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
SOLDER PASTE
OPENINGS
2
and D PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
STENCIL
Figure 15. Typical Stencil for DPAK and
D2PAK Packages
2
typical stencil for the DPAK and D PAK packages. The
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
2
D PAK is not recommended for wave soldering.
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NTB35N15
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER
JOINT
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
200°C
150°C
100°C
5°C
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 16. Typical Solder Heating Profile
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NTB35N15
PACKAGE DIMENSIONS
D2PAK
CASE 418B–04
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
3. 418B-01 THRU 418B-03 OBSOLETE, NEW
STANDARD 418B-04.
E
V
–B–
W
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
8.64
9.65
4.06
0.51
1.14
7.87
MAX
9.65
10.29
4.83
0.89
1.40
8.89
A
B
C
D
E
F
0.340
0.380
0.160
0.020
0.045
0.310
0.380
0.405
0.190
0.035
0.055
0.350
A
S
1
2
3
G
H
J
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.052
0.280
0.110
0.025
0.110
0.072
0.320
2.03
0.46
2.29
1.32
7.11
2.79
0.64
2.79
1.83
8.13
–T–
SEATING
PLANE
K
K
L
W
J
G
M
N
P
R
S
V
0.197 REF
0.079 REF
0.039 REF
5.00 REF
2.00 REF
0.99 REF
H
D 3 PL
0.575
0.045
0.625
0.055
14.60
1.14
15.88
1.40
M
M
T B
0.13 (0.005)
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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NTB35N15
Notes
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11
NTB35N15
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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NTB35N15/D
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NTB35N15G
37A, 150V, 0.05ohm, N-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 418B-04, D2PAK-3
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NTB4302G
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NTB4302T4G
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