NTTFD4D0N04HLTWG
更新时间：2024-09-19 05:38:05
品牌：ONSEMI
描述：MOSFET, Power, 40V POWERTRENCH® Power Clip Half Bridge Configuration
概述
数据手册NTTFD4D0N04HLTWG 概述
MOSFET, Power, 40V POWERTRENCH® Power Clip Half Bridge Configuration
NTTFD4D0N04HLTWG 数据手册
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PDF下载MOSFET - Symmetrical
Dual N-Channel
40 V, 4.5 mW, 60 A
NTTFD4D0N04HL
General Description
This device includes two specialized N−Channel MOSFETs in
a dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck converters.
The control MOSFET (Q2) and synchronous (Q1) have been designed
to provide optimal power efficiency.
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V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
4.5 mW @ 10 V
7 mW @ 4.5 V
40 V
60 A
Features
Q1: N−Channel
• Max r
• Max r
= 4.5 mW at V = 10 V, I = 10 A
GS D
DS(on)
ELECTRICAL CONNECTION
= 7 mW at V = 4.5, I = 8.0 A
DS(on)
GS
D
GND
LSG
V+
SW GND
GND
SW
SW
Q2: N−Channel
SW
SW
LSG
V+
• Max r
= 4.5 mW at V = 10 V, I = 10 A
GS D
DS(on)
SW
• Max r
= 7 mW at V = 4.5, I = 8.0 A
GS D
V+
DS(on)
V+
HSG V+
HSG
• Low Inductance Packaging Shortens Rise/Fall Times, Resulting in
Lower Switching Losses
Dual N-Channel MOSFET
PIN1
• RoHS Compliant
Typical Applications
• Computing
• Communications
• General Purpose Point of Load
PIN1
Bottom
Top
PIN DESCRIPTION
WQFN12, 3x3
CASE 510CJ
Pin
1, 11, 12
Name
GND (LSS)
LSG
Description
Low Side Source
MARKING DIAGRAM
2
Low Side Gate
3, 4, 5, 6
7
V + (HSD)
HSG
High Side Drain
D4D0
AYWWZZ
High Side Gate
8, 9, 10
SW
Switching Node, Low Side Drain
D4D0 = Specific Device Code
A
Y
= Assembly Plant Code
= Numeric Year Code
WW = Work Week Code
ZZ = Assembly Lot Code
ORDERING INFORMATION
Device
NTTFD4D0N04HLTWG
Package
Shipping†
WQFN12
3000 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2020 − Rev. 2
NTTFD4D0N04HL/D
NTTFD4D0N04HL
MOSFET MAXIMUM RATINGS (T = 25°C, Unless otherwise specified)
A
Symbol
Parameter
Q1
Q2
Units
V
V
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain Current −Continuous
40
40
V
V
A
DS
GS
20
20
I
T
T
= 25°C
(Note 4)
(Note 4)
60
60
D
C
C
−Continuous
−Continuous
−Pulsed
= 100°C
37
37
T = 25°C
A
15 (Note 1a)
15 (Note 1b)
T = 25°C
A
349
67
349
67
E
Single Pulse Avalanche Energy
(Note 3)
mJ
W
AS
P
Power Dissipation for Single Operation
Power Dissipation for Single Operation
T
= 25°C
C
26
26
D
T = 25°C
A
1.7 (Note 1a) 1.7 (Note 1b)
T , T
Operating and Storage Junction Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Symbol
Parameter
Thermal Resistance, Junction−to−Case
Q1
4.8
Q2
4.8
Units
°C/W
R
q
JC
R
Thermal Resistance, Junction−to−Ambient (Note 1a), max copper
Thermal Resistance, Junction−to−Ambient (Note 1c), min copper
70 (Note 1a)
70 (Note 1b)
q
JA
R
135 (Note 1a) 135 (Note 1b)
q
JA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
V
OFF CHARACTERISTICS
BV
Drain−to−Source Breakdown Voltage
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
40
40
I
I
I
I
= 250 mA, V = 0 V
DSS
D
D
D
D
GS
= 250 mA, V = 0 V
GS
Breakdown Voltage Temperature
Coefficient
16.63
16.63
mV/°C
mA
= 250 mA, referenced to 25°C
= 250 mA, referenced to 25°C
DBVDSS
DTJ
I
Zero Gate Voltage Drain Current
V
V
V
V
= 40 V, V = 0 V
10
DSS
DS
DS
GS
GS
GS
= 40 V, V = 0 V
10
GS
I
Gate−to−Source Leakage Current,
= +20/−16 V, V = 0 V
100
100
nA
GSS
DS
Forward
= +20/−16 V, V = 0 V
DS
ON CHARACTERISTICS
Gate−to−Source Threshold Voltage
V
GS(th)
Q1
Q2
Q1
Q2
Q1
1.2
1.2
1.5
1.5
2.0
2.0
V
V
V
I
= V , I = 50 mA
GS
DS
D
= V , I = 50 mA
GS
DS
D
Gate−to−Source Threshold Voltage
Temperature Coefficient
−5.75
−5.75
3.7
mV/°C
mW
= 50 mA, referenced to 25°C
= 50 mA, referenced to 25°C
DVGS(th)
DTJ
D
I
D
r
Drain−to−Source On Resistance
Drain−to−Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
GS
V
GS
V
GS
V
DS
V
DS
= 10 V, I = 10 A
4.5
7
DS(on)
D
= 4.5 V, I = 8 A
5.8
D
= 10 V, I = 10 A, T = 125°C
6.4
D
J
r
= 10 V, I = 10 A
Q2
3.7
4.5
7
mW
DS(on)
D
= 4.5 V, I = 8 A
5.8
D
= 10 V, I = 10 A, T = 125°C
6.4
D
J
g
FS
= 15 V, I = 10 A
Q1
Q2
61
S
D
= 15 V, I = 10 A
61
D
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2
NTTFD4D0N04HL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
pF
DYNAMIC CHARACTERISTICS
C
Input Capacitance
Q1:
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1100
1100
271
271
22
ISS
V
DS
= 20 V, V = 0 V, f = 1 Mhz
GS
C
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
pF
OSS
Q2:
V
DS
= 20 V, V = 0 V, f = 1 MHz
GS
pF
RSS
22
R
T = 25°C
2.0
W
G
A
2.0
SWITCHING CHARACTERISTICS
td
Turn−On Delay Time
Q1:
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
9.5
9.5
5.6
5.6
1.7
1.7
5.8
5.8
18
ns
ns
(ON)
V
DD
V
GS
= 32 V, I = 30.5 A,
D
= 4.5 V, R
= 2.5 W
GEN
t
r
Rise Time
Q2:
V
DD
V
GS
= 32 V, I = 30.5 A,
D
= 4.5 V, R
= 2.5 W
GEN
t
Turn−Off Delay Time
Fall Time
ns
D(OFF)
t
f
ns
Q
Q
Total Gate Charge
Total Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
V
V
= 0 V to 10 V
= 0 V to 4.5 V
nC
nC
nC
nC
g
g
GS
18
8.6
8.6
3.1
3.1
3.2
3.2
GS
Q1:
Q
V
D
= 32 V,
gs
gd
DD
I
= 30.5 A
Q2:
V
D
= 32 V,
Q
DD
I
= 30.5 A
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage V = 0 V, I = 10 A
(Note 2)
(Note 2)
Q1
Q2
Q1
Q2
Q1
Q2
0.78
0.78
26
26
9
1.2
1.2
V
SD
GS
S
V
GS
= 0 V, I = 10 A
S
t
Reverse Recovery Time
Q1:
ns
nC
rr
I = 30.5 A, di/dt = 100 A/ms
F
Q2:
Q
Reverse Recovery Charge
rr
I = 30.5 A, di/dt = 100 A/ms
F
9
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. R
is determined
CA
q
q
JA
by the user’s board design.
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3
NTTFD4D0N04HL
a) 70°C/W when mounted on
b) 70°C/W when mounted on
2
2
a 1 in pad of 2 oz copper.
a 1 in pad of 2 oz copper.
c) 135°C/W when mounted on
d) 135°C/W when mounted on
a minimum pad of 2 oz copper.
a minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. Q1: E of 67 mJ is based on starting T = 25_C; N−ch: L = 1 mH, I = 11.6 A, V = 40 V, V = 10 V. 100% test at L = 1 mH, I = 11.6 A.
AS
J
AS
DD
GS
AS
Q2: E of 67 mJ is based on starting T = 25_C; N−ch: L = 1 mH, I = 11.6 A, V = 40 V, V = 10 V. 100% test at L = 1 mH, I = 11.6 A.
AS
J
AS
DD
GS
AS
4. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal
& electro−mechanical application board design.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United
States and/or other countries.
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4
NTTFD4D0N04HL
TYPICAL CHARACTERISTICS
60
54
48
42
36
30
24
18
12
60
V
GS
= 10 V
to 3.2 V
V
DS
= 5 V
3.0 V
2.8 V
50
40
30
20
2.6 V
T = 25°C
J
2.4 V
2.2 V
10
0
6
0
T = 150°C
J
T = −55°C
J
0
1
2
3
4
5
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
10
300
250
200
150
100
T = 25°C
J
9
8
7
6
5
4
3
2
I
= 10 A
D
T = 25°C
J
V
= 4.5 V
= 10 V
GS
V
GS
50
0
1
0
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.0
1.8
1.6
1.4
1.2
1.0
100K
10K
1K
V
= 0 V
GS
V
= 10 V
= 10 A
GS
I
D
T = 150°C
J
T = 125°C
J
T = 85°C
J
100
10
0.8
0.6
−50 −25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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5
NTTFD4D0N04HL
TYPICAL CHARACTERISTICS
10K
1K
10
9
Q
G(TOT)
C
8
7
6
5
4
3
2
ISS
C
OSS
100
Q
Q
GD
GS
C
RSS
10
1
V
I
= 32 V
= 30.5 A
f = 1 MHz
= 0 V
T = 25°C
J
DS
V
D
GS
1
0
T = 25°C
J
0
5
10
15
20
25
30
35
40
0
2
4
6
8
10
12
14
16
18
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
1000
100
10
1000
100
10
V = 0 V
GS
V
V
= 4.5 V
= 32 V
= 30.5 A
GS
DS
I
D
t
d(on)
t
f
t
r
1
1
t
d(off)
T = 150°C T = 25°C
T = −55°C
J
J
J
0.1
0.1
1
10
R , GATE RESISTANCE (W)
100
0
0.2
0.4
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
0.6
0.8
1.0
1.2
1.4
V
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
T = 25°C, V ≤ 10 V
A
GS
Single Pulse
10 ms
R
= 135°C/W
q
JA
100
100 ms
T
= 25°C
J(initial)
10
1
1 ms
10 ms
100 ms
1
T
= 125°C
R
Limit
J(initial)
DS(on)
Thermal Limit
Package Limit
1 sec
10
0.1
0.000001
0.0001
0.001
0.01
0.1
1
0.1
1
100
t , TIME IN AVALANCHE (sec)
AV
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Unclamped Inductive Switching
Capability
Figure 12. Forward Bias Safe Operating Area
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6
NTTFD4D0N04HL
TYPICAL CHARACTERISTICS
1000
100
10
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
1
0.1
0.01
Single Pulse
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Transient Thermal Impedance
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN12 3.3X3.3, 0.65P
CASE 510CJ
ISSUE A
DATE 08 AUG 2022
GENERIC
MARKING DIAGRAM*
XXXX
AYWW
G
XXXX = Specific Device Code
A
Y
= Assembly Location
= Year
WW = Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13806G
WQFN12 3.3X3.3, 0.65P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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