NVMFWD024N06CT1G [ONSEMI]
Power MOSFET, N-Channel, DUAL SO8FL, 60 V, 22.6 mΩ, 24 A;型号: | NVMFWD024N06CT1G |
厂家: | ONSEMI |
描述: | Power MOSFET, N-Channel, DUAL SO8FL, 60 V, 22.6 mΩ, 24 A |
文件: | 总7页 (文件大小:252K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET – Power, Dual
N-Channel, SO-8FL
60 V, 22.6 mW, 24 A
NVMFD024N06C
Features
• Small Footprint (5x6 mm) for Compact Design
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• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• NVMFWD024N06C − Wettable Flank Option for Enhanced Optical
60 V
22.6 mW @ 10 V
24 A
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Power Tools, Battery Operated Vacuums
• UAV/Drones, Material Handling
• BMS/Storage, Home Automation
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
60
Units
V
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
MARKING
DIAGRAM
V
DSS
V
20
V
GS
1
24
Continuous Drain
Current RθJC (Note
1,3)
Steady
State
T
T
= 25°C
= 100°C
I
D
A
DFN8 5x6
(SO−8FL)
CASE 506BT
C
XXXXXX
AYWZZ
17
C
Power Dissipation
RθJC (Note 1)
Steady
State
T
T
= 25°C
P
28
14
8
W
A
C
D
= 100°C
C
XXXXXX = 24DN6C
XXXXXX = (NVMFD024N06C) or
XXXXXX = 24DN6W
Continuous Drain
Current RθJA
(Note 1, 2,3)
Steady
State
T = 25°C
I
D
A
T = 100°C
5
A
XXXXXX = (NVMFWD024N06C)
A
Y
= Assembly Location
= Year
Power Dissipation
RθJA (Note 1, 2)
Steady
State
T = 25°C
P
D
3.1
1.5
85
W
A
T = 100°C
A
W
ZZ
= Work Week
= Lot Traceability
Pulsed Drain Cur-
rent
T = 25°C, t = 10 ms
I
DM
A
A
p
Operating Junction and Storage Temperature
T , T
−55
to
175
°C
J
stg
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
Source Current (Body Diode)
I
23
14
A
S
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I = 5.3 A
)
L
pk
Lead Temperature Soldering Reflow for Sol-
dering Purposes (1/8” from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
December, 2019 − Rev. 0
NVMFD024N06C/D
NVMFD024N06C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
5.3
Unit
Junction−to−Case – Steady State (Note 2)
Junction−to−Ambient – Steady State (Note 2)
R
q
JC
°C/W
R
46.9
q
JA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
I
D
= 250 mA, ref to 25°C
27
mV/°C
(BR)DSS
/ T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
T = 25°C
10
mA
DSS
GS
DS
J
V
= 60 V
T = 125°C
J
250
100
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V = 20 V
nA
GSS
DS
GS
V
V
= V , I = 20 mA
2.0
4.0
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/
I
D
= 20 mA, ref to 25°C
−7.8
mV/°C
GS(TH)
T
J
Drain−to−Source On Resistance
Forward Transconductance
Gate Resistance
R
V
= 10 V, I = 3 A
18.8
10
22.6
mW
S
DS(on)
GS
D
g
FS
V
= 5 V, I = 3 A
DS D
R
T = 25°C
A
0.8
W
G
CHARGES & CAPACITANCES
Input Capacitance
C
333
225
5.05
5.7
ISS
Output Capacitance
C
V
GS
= 0 V, f = 1 MHz, V = 30 V
pF
nC
OSS
RSS
DS
Reverse Capacitance
Total Gate Charge
C
Q
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Q
1.3
G(TH)
V
= 10 V, V = 48 V, I = 3 A
DS D
GS
Q
2.0
GS
Q
0.68
GD
t
6.6
1.3
10
3
d(ON)
t
r
V
GS
I
= 10 V, V = 48 V,
DS
ns
V
= 3 A, R = 6 W
D
G
Turn−Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
T = 25°C
0.8
0.66
23
1.2
J
V
I
= 0 V,
= 3 A
GS
S
Forward Voltage
V
SD
T = 125°C
J
Reverse Recovery Time
Charge Time
t
RR
ta
11
ns
V
= 0 V, d /d = 100 A/ms,
IS t
GS
V
= 30 V, I = 3 A
DS
S
Discharge Time
tb
12
Reverse Recovery Charge
Q
11
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NVMFD024N06C
TYPICAL CHARACTERISTICS
25
50
45
40
35
30
25
20
15
10
5
VGS 7V to 10V
VGS = 6.0 V
20
15
VGS = 5.0 V
10
T = 25°C
J
VGS = 4.5V
5
T = 125°C
J
T = −55°C
J
VGS = 3.6V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.0
1.0
2.0
3.0
4.0
5.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
30
28
26
24
22
20
18
16
30
T = 25°C
I
= 3 A
J
D
T = 25°C
J
25
20
15
10
5
V
= 10 V
GS
3
6
9
12
15
18
21
24
27
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
2.5
2
T
J
= 175°C
I
V
= 3 A
D
T
= 150°C
J
= 10 V
GS
T
= 125°C
J
1.5
1
T
= 85°C
= 25°C
J
T
J
0.5
0
1.E−01
−50 −25
0
25
50
75 100 125 150 175
5
15
25
35
45
55
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVMFD024N06C
TYPICAL CHARACTERISTICS
1,000
100
10
C
C
9
8
7
6
5
4
3
2
1
0
I
= 3 A
ISS
D
T = 25°C
V
J
= 48V
DS
OSS
Q
Q
GD
GS
10
1
C
RSS
T = 25°C
GS
f = 1 MHz
J
V
= 0 V
0
1
2
3
4
5
6
0
10
20
30
40
50
60
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
100
V
GS
= 0 V
V
V
= 10 V
= 48 V
GS
DS
I
D
= 3 A
1
t
d(off)
t
10
d(on)
T = 125°C
J
T = 25°C
J
t
f
T = −55°C
J
t
r
1
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
10
R , GATE RESISTANCE (W)
100
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
10 ms
V
GS
≤ 10 V
SINGLE PULSE
= 25°C
T
C
100 ms
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
1 ms
10 ms
100 ms & 1 s
0.1
1
10
, DRAIN−TO−SOURCE VOLTAGE (V)
100
V
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
NVMFD024N06C
TYPICAL CHARACTERISTICS
100
10
1
T
= 25°C
J(initial)
T
= 100°C
J(initial)
1.E−06
1.E−05
1.E−04
TIME IN AVALANCHE (s)
1.E−03
1.E−02
Figure 12. Maximum Drain Current vs. Time in Avalanche
10
50% Duty Cycle
20%
10%
1
5%
2%
1%
SinglePulse
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
t, PULSE TIME (s)
Figure 13. Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NVMFD024N06CT1G
24DN6C
DFN8
1500 / Tape & Reel
1500 / Tape & Reel
(Pb−Free)
NVMFWD024N06CT1G
24DN6W
DFN8
(Pb−Free, Wettable Flanks)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE F
1
DATE 23 NOV 2021
2X
SCALE 2:1
NOTES:
0.20
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
D
A
B
E
2X
D1
0.20
C
8
7
6
5
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
PIN ONE
E1
MILLIMETERS
IDENTIFIER
DIM
A
A1
b
b1
c
MIN
0.90
−−−
0.33
0.33
0.20
NOM
−−−
−−−
0.42
0.42
−−−
5.15 BSC
4.90
4.10
1.70
6.15 BSC
5.90
4.15
1.27 BSC
0.55
−−−
−−−
−−−
0.61
MAX
1.10
0.05
0.51
0.51
0.33
NOTE 7
4X
h
1
2
3
4
c
TOP VIEW
D
A1
D1
D2
D3
E
E1
E2
e
G
h
K
K1
4.70
3.90
1.50
5.10
4.30
1.90
0.10
0.10
C
C
A
DETAIL B
5.70
3.90
6.10
4.40
ALTERNATE
SEATING
PLANE
NOTE 6
DETAIL A
CONSTRUCTION
C
NOTE 4
SIDE VIEW
DETAIL A
0.45
−−−
0.51
0.56
0.48
3.25
1.80
0.65
12
−−−
−−−
_
D2
D3
L
M
N
0.71
3.75
2.20
4X L
K
3.50
2.00
e
1
4
SOLDERING FOOTPRINT*
DETAIL B
4.56
4X
2X
2.08
2X
0.56
b1
8X
0.75
N
E2
M
8
5
4X
G
b
8X
4X
1.40
0.10
0.05
C
C
A B
K1
6.59
4.84
NOTE 3
2.30
BOTTOM VIEW
3.70
GENERIC
MARKING DIAGRAM*
0.70
1
XXXXXX
AYWZZ
4X
1.27
PITCH
1.00
5.55
XXXXXX = Specific Device Code
DIMENSION: MILLIMETERS
A
Y
W
ZZ
= Assembly Location
= Year
= Work Week
= Lot Traceability
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON50417E
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
PAGE 1 OF 1
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