STK5MFU3C1A-E [ONSEMI]
2 合 1 PFC 和逆变器，智能功率模块 (IPM)，600 V，30 A;
| 型号： | STK5MFU3C1A-E |
| 厂家： | 
ONSEMI |
| 描述： | 2 合 1 PFC 和逆变器，智能功率模块 (IPM)，600 V，30 A 功率因数校正 |
| 文件： | 总18页 (文件大小：722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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STK5MFU3C1A-E
2-in-1 PFC and Inverter Intelligent
Power Module (IPM), 600 V, 30 A
The STK5MFU3C1A-E is a fully-integrated PFC and inverter power
stage consisting of a high-voltage driver, six motor drive IGBT’s, one
PFC IGBT, one PFC rectifier and a thermistor, suitable for driving
permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC)
motors and AC asynchronous motors.
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PACKAGE PICTURE
The IGBT’s are configured in a 3-phase bridge with common emitter
connections for the lower legs.
An internal comparator and reference connected to the over-current
protection circuit allows the designer to set individual over-current
protection levels for the PFC and the inverter stages. Additionally, the
power stage has a full range of protection functions including cross-
conduction protection, external shutdown and under-voltage lockout
functions.
Features
Simple thermal design with PFC and inverter stage in one package.
PFC operating frequency up to 40 kHz
Cross-conduction protection
Adjustable over-current protection level
Integrated bootstrap diodes and resistors
SIP28 78x31.1
MARKING DIAGRAM
Certification
UL1557 (File Number : E339285)
STK5MFU3C1A
Typical Applications
Heat Pumps
ABCDD
Home Appliances
Industrial Fans
Industrial Pumps
3
6
9
12
16 18 20 22 24 26 28
1
4
7
10
13 15 17 19 21 23 25 27
STK5MFU3C1A = Specific Device Code
A = Year
B = Month
C = Production Site
DD = Factory Lot Code
Device marking is on package top side
HINU
LINU
HS1
LS1
HS2
LS2
HS3
LS3
Three channel
half-bridge
driver
HS1
LS1
HS2
LS2
HS3
LS3
HINV
LINV
+
single-ended
PFC driver
ORDERING INFORMATION
HINW
LINW
PFCIN
with
protection
circuits
Shipping
Device
Package
(Qty / Packing)
SIP28 78x31.1
(Pb-Free)
STK5MFU3C1A-E
280 / Box
GND
Figure 1. Functional Diagram
© Semiconductor Components Industries, LLC, 2016
December 2016 - Rev. 1
1
Publication Order Number :
STK5MFU3C1A-E/D
STK5MFU3C1A-E
STK5MFU3C1A
PFCL (1)
RC filtering for
HINx, LINx and
PFCIN not
VP1 (12)
VP2 (13)
From Op-amp
circuit
+
C1
CS
shown.
Recommended
in noisy
environments.
PTRIP (25)
RSPFC
HVGND (15)
N (16)
ITRIP (26)
RSINV
From HV
Power
Source
HINU (17)
HINV (18)
HINW (19)
LINU (20)
LINV (21)
LINW (22)
PFCIN (23)
To Op-amp
circuit
ToOp-amp
circuit
VBU (9)
U (10)
VBV (6)
V (7)
+
+
RP
Controller
FAULT/ TH (24)
Motor
VDD Supply
From 15V
VBW (3)
W (4)
VDD (27)
GND (28)
+
+
Power
Source
LV Ground
Star connection to HVGND
Figure 2. Application Schematic
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2
STK5MFU3C1A-E
VDD (27)
PFCL (1)
VBU (9)
VBV (6)
RBC
DB
DB
DB
RBS
RBS
RBS
VBW (3)
VP2 (13)
VP1 (12)
W (4)
V (7)
PFC
Driver
PFCIN(23)
U (10)
HVGND (15)
N (16)
Level
Level
Level
Shifter
Shifter
Shifter
HINU (17)
HINV (18)
HINW (19)
LINU (20)
LINV (21)
LINW (22)
Logic
Logic
Logic
VDD
undervoltage
shutdown
VDD
FAULT/ TH (24)
ITRIP (26)
PTRIP (25)
VITRIP
Reset after
delay
GND (28)
VPFCTRIP
Figure 3. Simplified Block Diagram
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3
STK5MFU3C1A-E
PIN FUNCTION DESCRIPTION
Pin
Name
PFCL
Description
1
3
4
6
7
9
PFC Inductor Connection to IGBT and Rectifier node
High Side Floating Supply voltage for W phase
V phase output. Internally connected to W phase high side driver ground
High Side Floating Supply voltage for V phase
V phase output. Internally connected to V phase high side driver ground
High Side Floating Supply voltage for U phase
U phase output. Internally connected to U phase high side driver ground
Positive PFC Output Voltage
VBW
W
VBV
V
VBU
U
10
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VP1
VP2
Positive Inverter Output Voltage
HVGND
N
Negative PFC Output Voltage
Low Side Emitter Connection
HINU
HINV
HINW
LINU
LINV
LINW
PFCIN
FAULT / TH
PTRIP
ITRIP
VDD
GND
Logic Input High Side Gate Driver - Phase U
Logic Input High Side Gate Driver - Phase V
Logic Input High Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase U
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver – Phase W
Logic Input PFC Gate Driver
FAULT output and thermistor output
Current protection pin for PFC
Current protection pin for inverter
+15 V Main Supply
Negative Main Supply
Note : Pins 2, 5, 8, 11 and 14 are not present
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4
STK5MFU3C1A-E
ABSOLUTE MAXIMUM RATINGS at Tc = 25°C (Notes 1, 2)
Rating
Symbol
Conditions
Value
Unit
PFC Section
V
Collector-emitter voltage
PFCL to HVGND
600
150
53
26
96
600
90
30
18
65
11
3
V
A
CE
Repetitive peak collector current
ICP
Duty cycle 10%, pulse width 1ms
PFC
IGBT
A
Collector current
IC
A
Tc = 100C
Maximum power dissipation
Diode reverse voltage
PC
W
V
VRM
IFP1
VP1 to PFCL
Repetitive peak forward current
Duty cycle 10%, pulse width 1ms
A
PFC
Diode
A
Diode forward current
IF1
A
Tc = 100C
Maximum power dissipation
PD1
IFP2
IF2
W
A
Repetitive peak forward current
Duty cycle 10%, pulse width 1ms
Anti-
parallel Diode forward current
A
Diode
Maximum power dissipation
PD2
VAC
Vo
5
W
V
Maximum AC input voltage
Maximum output voltage
Input AC current (steady state)
Inverter Section
Single-phase Full-rectified
264
450
33
V
In the Application Circuit
(VAC = 200 V)
Iin
Arms
VP2 to N surge < 500 V
(Note 3)
V
Supply voltage
450
V
CC
V
max
Collector-emitter voltage
VP2 to U, V, W or U, V, W to N
VP2, U, V, W, N terminal current
600
±30
V
A
CE
Output current
Io
VP2, U, V, W, N terminal current
at Tc = 100C
±15
A
VP, U, V, W, N terminal current, pulse
width 1 ms
Output peak current
Iop
Pd
±60
65
A
Maximum power dissipation
IGBT per 1 channel
W
Gate driver section
VBU to U, VBV to V, VBW to W, VDD
to GND (Note 4)
HINU, HINV, HINW, LINU, LINV,
LINW, PFCIN
V
Gate driver supply voltage
Input signal voltage
V
V
0.3 to +20.0
BS
0.3 to V
VIN
DD
0.3 to V
FAULT terminal voltage
ITRIP terminal voltage
PFCTRIP terminal voltage
Intelligent Power Module
Junction temperature
VFAULT
VITRIP
FAULT terminal
ITRIP terminal
PTRIP terminal
V
V
V
DD
0.3 to +10.0
1.5 to 2.0
VPTRIP
Tj
IGBT, FRD, Gate driver IC
150
C
C
Storage temperature
Tstg
Tc
40 to +125
20 to +100
1.17
Operating case temperature
Tightening torque
IPM case temperature
Case mounting screws
C
MT
Nm
50 Hz sine wave AC 1 minute
(Note 5)
Isolation voltage
Vis
2000
Vrms
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for
Safe Operating parameters.
3. This surge voltage developed by the switching operation due to the wiring inductance between VP2 and N terminal.
4.
V
= VBU to U, VBV to V, VBW to W
BS
5. Test conditions : AC 2500 V, 1 second
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5
STK5MFU3C1A-E
RECOMMENDED OPERATING RANGES (Note 6)
Rating
Symbol
Conditions
VP1 to HVGND, VP2 to N
VBU to U, VBV to V, VBW to W
Min
0
Typ
Max
400
17.5
16.5
5.0
0.3
40
Unit
V
V
Supply voltage
280
CC
VBS
12.5
13.5
2.5
0
15
15
-
V
Gate driver supply voltage
V
V
to GND
DD
V
DD
ON-state input voltage
OFF-state input voltage
PWM frequency(PFC)
PWM frequency(Inverter)
Dead time
VIN(ON)
VIN(OFF)
fPWMp
fPWMi
DT
V
HINU, HINV, HINW, LINU, LINV, LINW,
PFCIN
-
V
1
-
kHz
kHz
μs
μs
Nm
1
-
20
Turn-off to Turn-on (external)
ON and OFF
1.5
1
-
-
Allowable input pulse width
Tightening torque
PWIN
-
-
‘M4’ type screw
0.79
-
1.17
6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to
stresses beyond the Recommended Operating Ranges limits may affect device reliability.
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6
STK5MFU3C1A-E
ELECTRICAL CHARACTERISTICS (Note 7)
at Tc = 25C, V (V , V ) = 15 V unless otherwise noted.
BIAS BS DD
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
PFC Section
V
= 600 V
I
Collector-emitter cut-off current
Reverse leakage current (PFC Diode)
-
-
-
-
-
-
-
-
-
-
0.2
0.1
2.2
-
mA
mA
V
CE
CE
VR = 600 V
IR
-
IC = 40 A, Tj = 25°C
IC = 20 A, Tj = 100°C
IF = 40 A, Tj = 25°C
IF = 20 A, Tj = 100°C
1.6
1.3
2.4
1.5
1.5
-
V
(sat)
Collector-emitter saturation voltage
Diode forward voltage (PFC Diode)
CE
V
3.4
-
V
VF1
Diode forward voltage (Anti-parallel Diode) IF = 5 A, Tj = 25°C
VF2
2.4
1.3
1.9
V
IGBT
Junction to case thermal resistance
PFC Diode
θj-c(T)
θj-c(D)
°C/W
°C/W
-
Switching characteristics
tON
tOFF
trr
0.2
0.2
-
0.4
0.5
30
0.6
0.7
-
μs
μs
ns
Switching time
IC = 40 A, VP = 300 V, Tj = 25C
Diode reverse recovery time
Inverter section
V
= 600 V
I
Collector-emitter leakage current
Bootstrap diode reverse current
-
-
0.1
0.1
2.5
-
mA
mA
V
CE
CE
VR(DB) = 600 V
IC = 30 A, Tj = 25C
IC = 15 A, Tj = 100C
IF = 30 A, Tj = 25C
IF = 15 A, Tj = 100C
IGBT
IR(BD)
-
-
-
1.8
V
(SAT)
Collector to emitter saturation voltage
Diode forward voltage
CE
-
1.5
V
-
-
2.0
2.7
-
V
VF
1.6
V
θj-c(T)
θj-c(D)
tON
-
-
1.9
2.9
1.0
1.5
C/W
C/W
μs
Junction to case thermal resistance
Switching time
FRD
-
-
0.3
0.5
0.6
IC = 30 A, V
IC = 60 A, V
= 300 V, Tj = 25C
CC
CE
tOFF
1.1
μs
= 450 V
Reverse bias safe operating area
Short circuit safe operating area
Allowable offset voltage slew rate
RBSOA
SCSOA
dv/dt
Full Square
V
= 400 V, Tj = 100C
4
-
-
-
μs
CE
U, V, W to N
50
V/ns
50
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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7
STK5MFU3C1A-E
ELECTRICAL CHARACTERISTICS (Note 8)
at Tc = 25C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Driver Section
V
V
= 15 V (Note 4), per driver
= 15V, total
ID
ID
-
0.08
0.85
-
0.4
2.4
-
mA
mA
V
BS
DD
Gate driver consumption current
-
High level Input voltage
Low level Input voltage
Logic 1 input current
VIN H
VIN L
IIN+
2.5
HINU, HINV, HINW, LINU, LINV,
LINW, PFCIN to GND
-
-
-
-
-
0.8
143
2
V
VIN = +3.3 V
VIN = 0 V
100
-
μA
μA
V
Logic 0 input current
IIN-
Bootstrap diode forward voltage
IF = 0.1 A
VF(DB)
0.8
-
Resistor value for common boot
charge line
Resister values for separate boot
charge lines
RBC
RBS
-
-
22
33
-
-
Ω
Ω
Bootstrap circuit resistance
FAULT terminal sink current
FAULT clearance delay time
ITRIP threshold voltage
FAULT : ON / VFAULT = 0.1 V
IoSD
-
2
-
mA
ms
V
FLTCLR
VITRIP
VPTRIP
1.0
1.85
0.49
0.31
2.7
ITRIP to GND
PTRIP to GND
0.44
0.37
0.54
0.25
PTRIP threshold voltage
V
V
and V
supply undervoltage
BS
VCCUV+
VBSUV+
DD
positive going input threshold
and V supply undervoltage
10.5
10.3
0.14
11.1
10.9
0.2
11.7
11.5
-
V
V
V
V
VCCUV-
VBSUV-
DD
negative going input threshold
and V supply undervoltage Iockout
BS
V
VCCUVH
VBSUVH
DD
hysteresis
BS
8. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
STK5MFU3C1A-E
TYPICAL CHARACTERISTICS PFC SECTION
60
50
40
30
20
10
0
60
50
40
Tj = 25˚C
Tj = 100˚C
Tj = 100˚C
30
20
10
0
Tj = 25˚C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VCE, COLLECTOR-EMITTER VOLTAGE (V)
VF, FORWARD VOLTAGE (V)
Figure 4. VCE versus IC for different temperatures
(V = 15 V)
Figure 5. VF versus IF for different temperatures
DD
1.2
2.0
1.5
1.0
0.5
0.0
VCE = 300V
VCE = 300V
VDD = 15V
VDD = 15V
0.9
Tj = 100˚C
Tj = 100˚C
0.6
Tj = 25˚C
Tj = 25˚C
0.3
0.0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 7. EOFF versus IC for different temperatures
Figure 6. EON versus IC for different temperatures
1.0
0.8
0.6
0.4
0.2
0.0
0.000001
0.0001
0.01
1
100
ON-PULSE WIDTH (s)
Figure 8. Thermal Impedance Plot
500
400
300
200
100
0
50
40
30
20
10
0
500
400
300
200
100
0
50
40
30
20
10
0
VCE
IC
VCE
IC
-100
-10
-100
0.0
-10
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Time (μs)
Time (μs)
Figure 10. Turn-off waveform Tj = 100°C, V
= 300 V
Figure 9. Turn-on waveform Tj = 100°C, V = 300 V
CC
CC
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9
STK5MFU3C1A-E
TYPICAL CHARACTERISTICS INV SECTION
60
50
40
30
20
10
0
60
50
40
Tj = 25˚C
Tj = 25˚C
30
Tj = 100˚C
Tj = 100˚C
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VCE, COLLECTOR-EMITTER VOLTAGE (V)
VCE, COLLECTOR-EMITTER VOLTAGE (V)
Figure 11. VCE versus IC for different temperatures
(V = 15 V)
Figure 12. VF versus IF for different temperatures
DD
2.0
2.0
1.5
1.0
0.5
0.0
VCE = 300V
VCE = 300V
VDD = 15V
VDD = 15V
1.5
Tj = 100˚C
Tj = 100˚C
1.0
Tj = 25˚C
Tj = 25˚C
0.5
0.0
0
10
20
30
40
50
0
10
20
30
40
50
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 14. EOFF versus IC for different temperatures
Figure 13. EON versus IC for different temperatures
1.0
0.8
0.6
0.4
0.2
0.0
0.000001
0.0001
0.01
1
100
ON-PULSE WIDTH (s)
Figure 15. Thermal Impedance Plot
500
400
300
200
100
0
25
20
15
10
5
500
400
300
200
100
0
25
20
15
10
5
VCE
IC
VCE
IC
0
0
-100
-5
-100
0.0
-5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Time (μs)
Time (μs)
Figure 18. Turn-off waveform Tj = 100°C, V
= 300 V
Figure 17. Turn-on waveform Tj = 100°C, V
= 300 V
CC
CC
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10
STK5MFU3C1A-E
APPLICATIONS INFORMATION
Input / Output Timing Chart
Figure 18. Input / Output Timing Chart
Notes
9. This section of the timing diagram shows the effect of cross-conduction prevention.
10. This section of the timing diagram shows that when the voltage on V decreases sufficiently all gate output signals will go low,
DD
rises sufficiently, normal operation will resume.
switching off all six IGBTs. When the voltage on V
DD
11. This section shows that when the bootstrap voltage on VBU (VBV, VBW) drops, the corresponding high side output U (V, W) is
switched off. When the voltage on VBU (VBV, VBW) rises sufficiently, normal operation will resume.
12. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes
later after the over-current condition is removed. Similarly, when the voltage on PTRIP exceeds the threshold, all IGBT’s are
turned off. Normal operation resumes later after the over-current condition is removed
Input / Output Logic Table
INPUT
OUTPUT
High side IGBT
ON
HIN
H
LIN
L
ITRIP
PTRIP
Low side IGBT
U,V,W
FAULT
OFF
OFF
OFF
OFF
ON
L
L
L
L
H
X
L
L
L
L
X
H
OFF
ON
VP
L
H
L
OFF
N
L
OFF
OFF
OFF
OFF
OFF
High Impedance
High Impedance
High Impedance
High Impedance
H
H
X
OFF
X
OFF
X
X
OFF
ON
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11
STK5MFU3C1A-E
Thermistor characteristics
Parameter
Symbol
Condition
Min
99
Typ
100
Max
101
Unit
kΩ
kΩ
K
R
25
Tth = 25℃
Resistance
R
100
5.18
4208
40
5.38
4250
5.60
4293
+125
Tth = 100℃
B
B-Constant (25 to 50℃)
Temperature Range
℃
Figure 19. Thermistor Resistance versus Thermistor Temperature
Figure 20. Thermistor Voltage versus Thermistor Temperature
Conditions: RTH = 39 kΩ, pull-up voltage 5.0 V (see Figure 2)
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12
STK5MFU3C1A-E
Signal inputs
Calculation of bootstrap capacitor value
Each signal input has a pull-down resistor. An
additional pull-down resistor of between 2.2 kΩ and
3.3 kΩ is recommended on each input to improve noise
immunity.
The bootstrap capacitor value CB is calculated using
the following approach. The following parameters
influence the choice of bootstrap capacitor :
VBS: Bootstrap power supply.
15 V is recommended.
QG: Total gate charge of IGBT at VBS = 15 V.
266 nC
UVLO: Falling threshold for UVLO.
Specified as 12 V.
IDMAX: High side drive power dissipation.
Specified as 0.4 mA
FAULT/ TH pin
The FAULT pin is connected to an open-drain FAULT
output requiring a pull-up resistor. If the pull-up
voltage is 5 V, use a pull-up resistor with a value of 6.8
kꢀ or higher. If the pull-up voltage is 15 V, use a pull-
up resistor with a value of 20 kꢀ or higher. The
FAULT output is triggered if there is a V
undervoltage or an overcurrent condition on either the
PFC or inverter stages.
DD
TONMAX: Maximum ON pulse width of high
side IGBT.
The FAULT/ TH pin is also connected to a grounded
thermistor. Thermal characteristics are shown in this
datasheet for a pull up value of 39 kꢀ.
Capacitance calculation formula:
CB = (QG + IDMAX * TONMAX) / (VBS UVLO)
Undervoltage protection
CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB
is in the range of 1 to 47 μF, however, the value needs
to be verified prior to production. When not using the
bootstrap circuit, each high side driver power supply
requires an external independent power supply. If the
capacitors selected are 47 μF or more, a series resistor
of 20 Ω should be added in series with the three
capacitors to limit the current. The resistors should be
inserted between VBU and U, VBV and V and VBW
and W.
If V
goes below the V supply undervoltage
DD
DD
lockout falling threshold, the FAULT output is
switched on. The FAULT output stays on until V
DD
supply undervoltage lockout
rises above the V
DD
rising threshold. The hysteresis is approximately 200
mV.
Overcurrent protection
An over-current condition is detected if the voltage on
the ITRIP/PTRIP pin is larger than the reference
voltage. There is a blanking time of typically 350 ns to
improve noise immunity. After
propagation delay of typically 0.6 s, the FAULT
output is switched on.
a
shutdown
80
60
40
20
0
The over-current protection threshold should be set to
be equal or lower to 2 times the module rated current
(IO).
An additional fuse is recommended to protect against
system level or abnormal over-current fault conditions.
0.1
1
10
100
1000
Capacitors on High Voltage and V
DD
supplies
Tonmax [ms]
Both the high voltage and V
supplies require an
DD
Figure 21. Bootstrap capacitance versus Tonmax
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high
frequency capacitor is between 100 nF and 10 μF.
Minimum input pulse width
When input pulse width is less than 1μs, an output may
not react to the pulse. (Both ON signal and OFF signal)
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13
STK5MFU3C1A-E
Mounting Instructions
Item
Recommended Condition
Pitch
70.0 ±0.1 mm (Please refer to Package Outline Diagram)
diameter : M4
Screw
Bind machine screw, Truss machine screw, Pan machine screw
Plane washer
Washer
The size is D : 9 mm, d : 4.3 mm and t : 0.8 mm JIS B 1256
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : 50 to 100 μm
Screw holes must be countersunk.
Heat sink
No contamination on the heat sink surface that contacts IPM.
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.79 to 1.17 Nm on first screw
Torque
Grease
Final tightening : 0.79 to 1.17 Nm on second screw
Silicone grease.
Thickness : 100 to 200 μm
Uniformly apply silicone grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and
compressibility parameters have a strong influence on performance.
Screw
First
Second
t
Washer
Module
Grease
Module
D
d
+
Heatsink
showing
warpage
‐
Mounting components
Washer details
Silicone grease
Recommended
Not recommended
Thermal grease must be spread
evenly (left is correct)
Figure 22. Module Mounting details: components; washer drawing; need for even spreading of thermal grease
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14
STK5MFU3C1A-E
TEST CIRCUITS
■ I , IR(DB)
CE
PFC
W-
U+
V+
W+
U-
V-
9
ICE, IR
VBS=15V
VBS=15V
VBS=15V
VDD=15V
IGBT
A
A
10
A
B
13
10
13
7
13
4
10
16
7
4
1
6
7
16
16
15
VCE, VR
U+,V+,W+ : High side phase
U-,V-,W- : Low side phase
3
4
27
B
PFC
Diode
U(DB) V(DB)
W(DB)
28, 15, 16
A
B
9
6
3
12
28
28
28
1
Figure 23. Test Circuit for I
CE
■ V (sat) (Test by pulse)
CE
PFC
IGBT
9
U+
V+
W+
U-
V-
W-
VBS=15V
VBS=15V
VBS=15V
A
10
A
B
C
13
10
17
13
7
13
4
10
16
20
7
4
1
6
7
16
21
16
22
15
23
V
IC
18
19
3
VCE(sat)
4
27
VDD=15V
5V
C
B
28, 15, 16
Figure 24. Test circuit for VCE(SAT)
■ V (Test by pulse)
F
U+
V+
13
7
W+
13
4
U-
10
16
V-
7
W-
4
A
B
13
10
A
V
B
16
16
IF
PFC
Diode
Anti-parallel
Diode
U(DB)
V(DB)
W(DB)
A
B
9
6
3
12
1
1
28
28
28
15
Figure 25. Test circuit for VF
■ ID
V
ID
VBS U+
VBS V+
VBS W+
DD
A
A
B
A
B
9
6
7
3
4
27
28
10
VD*
Figure 26. Test circuit for ID
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15
STK5MFU3C1A-E
■ VITRIP, VPTRIP
VITRIP(U-)
10
VPTRIP
A
B
C
D
1
A
B
16
20
26
15
23
25
27
VDD=15V
V
Io
Input Signal
VITRIP/VPFCTRIP
C
D
28, 15, 16
Input Signal
(0 to 5V)
Figure 27. Test circuit for ITRIP.PTRIP
ITRIP
/PFCTRIP
lo
■ Switching time (The circuit is a representative example of the lower side U phase.)
PFC
IGBT
U+
V+
W+
U-
V-
W-
9
VBS=15V
A
C
10
A
B
C
D
E
13
16
10
16
17
13
16
7
13
16
4
13
16
13
10
20
13
16
13
7
13
16
13
4
12
6
7
VBS=15V
VBS=15V
VDD=15V
15
CS VCC
12
3
4
16
18
16
19
1
D
B
21
22
23
27
E
Input Signal
Io
28, 15, 16
Input Signal
(0 to 5V)
Figure 28. Test circuit for switching time
90%
lo
10%
tON
tOFF
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16
STK5MFU3C1A-E
Package Dimensions
unit : mm
SIP28 78x31.1
CASE 127DG
ISSUE A
1
28
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17
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