PJSRV05-4 [PANJIT]
Low Capacitance TVS and Diode Array; 低电容TVS二极管阵列
| 型号： | PJSRV05-4 |
| 厂家： | 
PAN JIT INTERNATIONAL INC. |
| 描述： | Low Capacitance TVS and Diode Array |
| 文件： | 总3页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PJSRV05-4, PJSRV05W-4
Low Capacitance TVS and Diode Array
This diode array is configured to protect up to four data transmission lines
acting as a line terminator, minimizing overshoot and undershoot conditions
due to bus impedance as well as protect against over-voltage events as
electrostatic discharges. Additionaly the TVS Device offers overvoltage
transient protection between the operating voltage bus and ground plane.
4
6
3
SPECIFICATION FEATURES
1
Peak Power Dissipation of 350W 8/20µs
SOT26
Maximum Capacitance of 5pF at 0Vdc 1MHz Line-to-Ground
Maximum Leakage Current of 5µA @ VRWM
4
Available in SOT23-6L and SOT363 packages
IEC61000-4-2, IEC61000-4-4 and IEC61000-4-5 Full Compliance
100% Tin Matte finish (LEAD-FREE PRODUCT)
6
3
1
SOT363
APPLICATIONS
USB 2.0 and Firewire Port Protection
LAN/WLAN Access Point terminals
Video Signal line protection
I/O3
4
3
2
1
I/O2
REF2
I/O1
REF1
I/O4
5
6
2
I C Bus Protection
Touch Panel Controller lines protection
Device
Marking Code
PJSRV05-4
PJSRV05W-4
054
W5
MAXIMUM RATINGS
Tj = 25°C Unless otherwise noted
Rating
Symbol
Value
350
Units
W
P
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
PPM
I
20
A
PP
T
J
-55 to +150
-55 to +150
260
°C
Operating Junction Temperature Range
Storage Temperature Range
T
stg
°C
T
Soldering Temperature, t max = 10s
°C
L
9/1/2006
www.panjit.com
Page 1
PJSRV05-4, PJSRV05W-4
Tj = 25°C unless otherwise noted
ELECTRICAL CHARACTERISTICS
Parameter
Min Typical Max
Units
V
Conditions
Symbol
V
Reverse Stand-Off Voltage
5
WRM
V
I
=
=
=
6.2
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
1mA
5V
V
BR
BR
I
5
µA
V
V
R
R
V
10
15
3A
c
I
I
pp
pp
V
= 12A
20A
V
c
Clamping Voltage (8/20µs)
V
c
18
V
I
=
pp
0 Vdc Bias f = 1MHz
Between I/O pins and GND
Off State Junction Capacitance
4
2
5
3
pF
pF
Cj
0 Vdc Bias f = 1MHz
Between I/O pins
Surge Pulse Waveform Definition
TVS Clamping Voltage vs Ipp 8/20µs
100
90
80
70
60
50
40
30
20
10
0
30
25
20
15
10
5
50% of Ipp @ 20µs
TA = 25°C
Rise time 10-90% - 8µs
0
0
5
10
15
20
25
30
8
10
12
14
16
18
20
time, µsec
Clamping Voltage, V
Off-State Capacitance vs Vdc @ 1MHz (L-GND)
6
5
4
3
2
1
0
0
1
2
3
4
5
Bias Voltage, Vdc
9/1/2006
www.panjit.com
Page 2
PJSRV05-4
PACKAGE DIMENSIONS
TYPICAL APPLICATION CONFIGURATION
D + (1)
D - (1)
USB2.0 Port1
4
3
2
1
Vbus +
5
6
Gnd
PJSRV05-4
D + (2)
D - (2)
USB2.0 Port2
© Copyright PanJit International, Inc 2006
The information presented in this document is believed to be accurate and reliable. The specifications and information herein are
subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any
license under its patent rights or rights of others.
9/1/2006
www.panjit.com
Page 3
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