PI4IOE5V9536WEX [PERICOM]
SMBus low power I/O port;
| 型号： | PI4IOE5V9536WEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | SMBus low power I/O port |
| 文件： | 总12页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI4IOE5V9536
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4-bit I2C-bus and SMBus low power I/O port
Features
Description
Operation power supply voltage from 2.3V to 5.5V
4-bit I2C-bus GPIO with 5V tolerant I/Os
Polarity inversion register
The PI4IOE5V9536 provides 4 bits of General
Purpose parallel Input/Output (GPIO) expansion for I2C-
bus/ SMBus applications. It includes the features such as
higher driving capability, 5V tolerance, lower power
supply, individual I/O configuration, and smaller
packaging. It provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
The PI4IOE5V9536 consists of a 4-bit registers to
configure the I/Os as either inputs or outputs, and a 4-bit
polarity registers to change the polarity of the input port
register data The data for each input or output is kept in
the corresponding Input port or Output port register. All
registers can be read by the system master.
Low current consumption
0Hz to 1MHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
4 I/O pin which default to 4 inputs with 100kΩ pull-
up resistor
ESD protection (4KV HBM and 1KV CDM)
Offered in three different packages:SOIC-8,MSOP-8
and TDFN2x3-8
Pin Description
Pin Configuration
* I = Input; O = Output; P = Power; G = Ground
Pin Name Type
Description
1
2
3
4
5
6
7
8
IO0
IO1
I/O
I/O
I/O
G
input/output 0
input/output 1
input/output 2
Supply Ground
input/output 3
Serial clock line
Serial data line
Power supply
IO2
GND
IO3
Figure1 : SOIC-8 & MSOP-8
I/O
I
SCL
SDA
VCC
I/O
P
TDFN 2x3
Figure2 : TDFN 2x3-8
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PI4IOE5V9536
4-bit I2C-bus and SMBus
low power I/O port
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Maximum Ratings
Note:
Powersupply......................................................................................................-0.5Vto+6.0V
Voltageonan I/Opin..........................................................................GND-0.5Vto +6.0V
Inputcurrent.....................................................................................................................±20mA
Outputcurrenton anI/Opin ......................................................................................±50mA
Supplycurrent....................................................................................................................85mA
Groundsupplycurrent...................................................................................................100mA
Totalpowerdissipation................................................................................................200mW
Operationtemperature...............................................................................................-40~85℃
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storagetemperature ................................................................................................-65~150℃
Maximum Junctiontemperature,Tj(max) ................................................................125℃
Static characteristics
VCC = 2.3 V to 5.5 V; GND = 0 V; Tamb= -40 °C to +85 °C; unless otherwise specified.
Table 2: Static characteristic
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Power supply
VCC
ICC
Supply voltage
Supply current
2.3
-
5.5
400
350
1
V
μA
uA
μA
V
Operating mode; VCC = 5.5 V; no load;
fSCL= 100 kHz
Standby mode; VCC = 5.5 V; no load;
VI = GND; fSCL= 0 kHz; I/O = inputs
Standby mode; VCC = 5.5 V; no load;
VI = VCC; fSCL= 0 kHz; I/O = inputs
-
-
-
-
290
225
0.25
1.16
Istb
Standby current
[1]
VPOR
1.41
Power-on reset voltage
Input SCL, input/output SDA
Low level input voltage
V
IL
-0.5
-
-
+0.3VCC
V
V
V
High level input voltage
Low level output current
Leakage current
0.7VCC
5.5
-
IH
IOL
IL
VOL=0.4V
3
-1
-
6
-
mA
μA
pF
VI=VCC=GND
VI =GND
1
Ci
Input capacitance
6
10
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4-bit I2C-bus and SMBus
low power I/O port
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Conditions
Symbol
I/Os
Parameter
Min.
Typ.
Max.
Unit
VIL
VIH
Low level input voltage
High level input voltage
-0.5
+1.8
8
-
-
+0.81
V
V
5.5
-
VCC = 2.3 V; VOL = 0.5 V[2]
VCC = 2.3 V; VOL = 0.7 V[2]
VCC = 3.0 V; VOL = 0.5 V[2]
VCC = 3.0 V; VOL = 0.7 V[2]
VCC = 4.5 V; VOL = 0.5 V[2]
VCC =4.5 V; VOL = 0.7 V[2]
IOH=-8mA;VCC=2.3V[3]
10
13
14
19
17
24
-
mA
10
-
mA
mA
8
-
IOL
Low level output current
mA
mA
mA
10
-
8
-
10
-
1.8
1.7
2.6
2.5
4.1
4.0
-
V
V
V
V
V
V
IOH=-10mA;VCC=2.3V[3]
IOH=-8mA;VCC=3.0V[3]
-
-
-
-
VOH
High level output voltage
IOH=-10mA;VCC=3.0V[3]
IOH=-8mA;VCC=4.75V[3]
IOH=-10mA;VCC=4.75V[3]
-
-
-
-
-
-
High level input leakage
current
Low level input leakage
current
ILIH
ILIL
VCC=3.6V; VI=VCC
VCC=5.5V; VI=GND
-
-
-
-
1
μA
μA
-100
Ci
Input capacitance
Output capacitance
-
-
3.7
3.7
10
10
pF
pF
Co
Note:
[1]: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
[2]: Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA
[3]: The total current sourced by all I/Os must be limited to 85mA.
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4-bit I2C-bus and SMBus
low power I/O port
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Dynamic Characteristics
Table 3: Dynamic characteristics
Standard
mode I2C
Fast mode
I2C
Fast mode
Plus I2C
Unit
Test
Conditions
Symbol
Parameter
Min
0
Max Min Max
Min
0
Max
fSCL
tBUF
SCL clock frequency
100
0
1.3
0.6
0.6
0.6
-
400
1000 kHz
bus free time between a STOP
and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
4.7
4.0
-
-
0.5
0.26
-
μs
μs
μs
μs
μs
ns
us
ns
μs
μs
ns
ns
tHD;STA
tSU;STA
tSU;STO
-
-
-
-
4.7
4.0
-
-
-
0.26
-
set-up time for STOP
condition
-
0.26
-
0.45
-
[1]
tVD;ACK
data valid acknowledge time
data hold time
3.45
-
0.9
-
-
0
[2]
tHD;DAT
0
0
tVD;DAT
tSU;DAT
tLOW
tHIGH
tf
data valid time
-
3.45
-
0.9
-
-
0.45
-
data set-up time
250
-
100
1.3
0.6
-
50
0.5
0.26
-
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
-
-
-
-
-
-
-
fall time of both SDA and SCL
signals
rise time of both SDA and
SCL signals
300
1000
300
300
120
120
tr
-
-
-
pulse width of spikes that must
be suppressed by the input
filter
tSP
-
50
-
50
50
ns
Port timing
tv(Q)
Data output valid time[3]
Data input set-up time
Data input hold time
-
200
-
100
1
200
-
100
1
200
ns
ns
μs
tsu(D)
100
1
-
-
-
-
-
-
Th(D)
Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
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4-bit I2C-bus and SMBus
low power I/O port
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PI4IOE5V9536 Block Diagram
Fig3: Block diagram of PI4IOE5V9536
Note: All I/Os are set to inputs at reset.
Details Description
a. Device address
Table 4: Device address
b7(MSB) b6
b5
0
b4
0
b3
0
b2
0
b1
1
b0
Address Byte
1
0
R/W
Note: Read “1”, Write “0”
b. Registers
i. Command byte
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine
which of the following registers will be written or read.
Table 5: Command byte
Command
Register
0
1
2
3
Input port register
Output port register
Polarity inversion register
Configuration register
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4-bit I2C-bus and SMBus
low power I/O port
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ii.Register 0: input port registers
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an
input or an output by Register 2. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 6: Input port 0 register
Bit
7
I7
1
6
I6
1
5
I5
1
4
I4
1
3
2
1
0
Symbol
Default
I3
X
I2
X
I1
X
I0
X
iii. Register 1:Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 3. Bit values
in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop
controlling the output selection, not the actual pin value.
Table 8: Output port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
Default
iv. Register 2: Polarity inversion register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’),
the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 10: Polarity Inversion port 0 register
Bit
7
N7
0
6
N6
0
5
N5
0
4
N4
0
3
N3
0
2
N2
0
1
N1
0
0
N0
0
Symbol
Default
v.Register 3: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin
is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding
port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VCC
Table 12: Configuration port 0 register
Bit
7
C7
1
6
C6
1
5
C5
1
4
C4
1
3
C3
1
2
C2
1
1
C1
1
0
C0
1
Symbol
Default
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4-bit I2C-bus and SMBus
low power I/O port
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c. Power-on reset
When power is applied to VCC, an internal power-on reset holds the PI4IOE5V9536 in a reset condition until VCC has
reached VPOR. At that point, the reset condition is released and the PI4IOE5V9536 registers and SMBus state machine will
initialize to their default states. Thereafter, VCC must be lowered below 0.2 V to reset the device. For a power reset cycle, VCC
must be lowered below 0.2 V and then restored to the operating voltage.
d. I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be
raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should
be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists
between the pin and either VCC or GND.
Figure 4: Simplified schematic of I/Os
After power-on reset, all registers return to default values.
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PI4IOE5V9536
4-bit I2C-bus and SMBus
low power I/O port
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e. Bus Transaction
Data is transmitted to the PI4IOE5V9536 using the Write mode as shown in Figure 5.Data is read from the PI4IOE5V9536
using the read mode as shown in Figure 7.These devices do not implement an auto-increment function, so once a command byte
has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
Figure 5: Write to output registers
Figure 6: Write to polarity inversion registers
Figure 7: Read from registers
Note: Transfer can be stopped at any time by a STOP condition.
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PI4IOE5V9536
4-bit I2C-bus and SMBus
low power I/O port
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Figure 8: Read Input port register
Note: Transfer of data can be stopped at any moment by a STOP condition. It is assumed that the command byte has previously been set to ‘00’ (read
Input Port register).
Application design-in information
Figure 9: Typical application
IO0 configured as outputs.
IO1, IO2, IO3 configured as inputs.
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4-bit I2C-bus and SMBus
low power I/O port
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Mechanical Information
SOIC-8(W)
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PI4IOE5V9536
4-bit I2C-bus and SMBus
low power I/O port
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MSOP-8(U)
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PI4IOE5V9536
4-bit I2C-bus and SMBus
low power I/O port
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TDFN 2x3-8(ZE)
Ordering Information
Part No.
Package Code
Package
PI4IOE5V9536WE
PI4IOE5V9536WEX
PI4IOE5V9536UE
W
W
U
8-Pin,150 mil Wide SOIC
8-Pin,150 mil Wide SOIC, Tape & Reel
8-Pin, Mini Small Outline Package(MSOP)
8-Pin, Mini Small Outline Package(MSOP), Tape &
Reel
PI4IOE5V9536UEX
U
PI4IOE5V9536ZEEX
ZE
8-Pin,TDFN2x3, Tape & Reel
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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