PI6C2501WE [PERICOM]
PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, PLASTIC, SOIC-8;
| 型号： | PI6C2501WE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, PLASTIC, SOIC-8 时钟驱动器 |
| 文件： | 总4页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2501
Phase-Locked Loop Clock Driver
ProductFeatures
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
• High-Performance,Phase-Locked-LoopClockDistribution
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Zero Input-to-Output delay
• Lowjitter:Cycle-to-Cyclejitter±100psmax.
Application
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• Operatesat3.3VVCC
• Wide range of Clock Frequencies up to 80 MHz
• Package:Plastic8-pinSOIC(W)
ProductPinConfiguration
LogicBlockDiagram
8
7
6
5
AGND
GND
1
2
3
4
CLK_IN
CLK_IN
CLK_OUT
8-Pin
W
AV
CC
PLL
FB_IN
AVCC
CLK_OUT
GND
V
FB_IN
CC
Feedback
Zero Delay
Buffer
PI6C2501
18 Outputs
Non-PLL
Buffer
C
CLK_OUT
17
Reference
Clock
Signal
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
PS8381A
07/17/00
1
PI6C2501
Phase-Locked Loop Clock Driver
PinFunctions
Pin Name Pin No.
Type
Description
CLK_IN
FB_IN
8
5
I
I
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Clock output. This output provides a low-skew copy of CLK_IN. The output has an embedded
series-damping resistor.
CLK_OUT
AVCC
3
7
O
Analog power supply. AVCC can be also used to bypass the PLL for test purpose. When AVCC
is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs.
Power
AGND
VCC
1
4
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply.
Ground Ground.
GND
2, 6
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
Units
V
Input voltage range
Output voltage range
DC output current
I
-0.5
V
CC
+0.5
V
V
O
I
100
mA
W
O_DC
o
Power
Maximum power dissipation at T = 55 C in still air
1.0
A
o
T
STG
Storage temperature
65
150
C
Note:
Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parameter
Test Conditions
V
CC
Min.
Typ.
Max.
Units
(1)
I
CC
V = V or GND; I = 0
3.6V
10
µA
I
CC
O
C
V = V or GND
4
6
I
I
CC
3.3V
pF
C
V =V or GND
O CC
O
Note:
1. Continuous Output Current
Recommended Operating Conditions
Symbol
Parameter
Min.
Max.
Units
VCC
VIH
VIL
VI
Supply voltage
3.0
2.0
3.6
High level input voltage
Low level input voltage
Input voltage
V
0.8
VCC
70
0
0
TA
Operating free-air temperature
ºC
PS8381A
07/17/00
2
PI6C2501
Phase-Locked Loop Clock Driver
Electrical Characteristics (Over Recommended Operating Free-Air Temperature Range
Pull Up/Down Currents of PI6C2501, VCC = 3.0V)
Symbol Parameter
Condition
Vout = 2.4V
Min.
Max.
-18
Units
Pull-up current
Pull-up current
I
OH
Vout = 2.0V
Vout = 0.8V
-30
mA
Pull-down current
Pull-down current
25
17
I
OL
Vout = 0.55V
AC Specifications
(Timing requirements over recommended ranges of supply voltage and operating free-air temperature)
Symbol
Parameter
Clock frequency PI6C2501
Min.
25
Max.
80
Units
F
MHz
%
CLK
D
CYI
Input clock duty cycle
40
60
Stabilization Time after power up
1
ms
SwitchingCharacteristics
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF)
V
= 3.3V ±0.3V, 0-70°C
CC
Parameter
From (Input)
To (Output)
Units
Min.
Typ.
Max.
tphase error without jitter
CLK_IN↑ at 100 & 66 MHz
FB_IN↑
150
+150
ps
Jitter, cycle-to-cycle
Duty cycle
At 100 & 66 MHz
100
45
+100
55
%
ns
CLK_OUT
tr, rise-time, 0.4V to 2.0V
tf, fall-time, 2.0V to 0.4V
Note:
1.0
1.1
These switching parameters are guaranteed by design.
PS8381A
07/17/00
3
PI6C2501
Phase-Locked Loop Clock Driver
Package Mechanical Information: Plastic 8-pin SOIC Package.
8
.149
.157
3.78
3.99
0.25
0.50
.0099
.0196
x 45˚
1
0.19
0.25
.0075
.0098
.189
.196
4.80
5.00
0-8˚
0.40 .016
1.27
.050
.2284
.2440
5.80
6.20
.016
.026
0.406
0.660
1.35
1.75
.053
.068
SEATING PLANE
REF
.050
BSC
0.10
0.25
.0040
.0098
1.27
.013
.020
0.330
0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Ordering Code
Package Name
Package Type
8-pin 150-mil SOIC
Operating Range
PI6C2501W
W8
Commercial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8381A
07/17/00
4
相关型号：
PI6C2502WE
PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8
PERICOM
PI6C2502WEX
PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8
PERICOM
PI6C2502WX
PLL Based Clock Driver, 6C Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, PLASTIC, SOIC-8
PERICOM
PI6C2504AQE
PLL Based Clock Driver, 6C Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, LEAD FREE, PLASTIC, QSOP-16
PERICOM
©2020 ICPDF网 联系我们和版权申明