PI6C49004AAE [PERICOM]
PCIe Gen 2 Networking Clock Generator;
| 型号： | PI6C49004AAE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PCIe Gen 2 Networking Clock Generator 时钟 PC 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：730K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Description
Features
TheꢀPI6C49004AꢀisꢀaꢀclockꢀgeneratorꢀdeviceꢀintendedꢀforꢀPCIe®ꢀ
Gen2ꢀ networkingꢀ applications.ꢀ Theꢀ deviceꢀ includesꢀ twelveꢀ
100MHzꢀ differentialꢀ Hostꢀ Clockꢀ Signalꢀ Levelꢀ (HCSL)ꢀ outputsꢀ
forꢀPCIeꢀGenꢀ2,ꢀtwoꢀsingle-endedꢀ50MHzꢀoutputs,ꢀoneꢀsingle-
endedꢀ 32.256MHzꢀ output,ꢀ andꢀ oneꢀ selectableꢀ single-endedꢀ
33/66/133MHzꢀoutput.
•ꢀ 3.3Vꢀ+/-10%ꢀSupplyꢀVoltage
•ꢀ Usesꢀ25MHzꢀxtalꢀsuchꢀasꢀSaronix-eCera™ꢀSRX7278
•ꢀ TwelveꢀPCIe®ꢀGen.ꢀ2ꢀ100MHzꢀHCSLꢀoutputsꢀwithꢀoptionalꢀ
-0.5%ꢀspreadꢀspectrumꢀsupportꢀ
•ꢀ TwoꢀLVCMOSꢀ50MHzꢀoutputsꢀthatꢀsupportꢀ+/-ꢀ10%ꢀ
frequencyꢀmargining
UsingꢀaꢀseriallyꢀprogrammableꢀSMBUSꢀinterface,ꢀtheꢀPI6C49004Aꢀ
incorporatesꢀspreadꢀspectrumꢀmodulationꢀonꢀtheꢀtwelveꢀ100MHzꢀ
HCSLꢀPCIeꢀGenꢀ2ꢀoutputs,ꢀandꢀindependentꢀfrequencyꢀmarginingꢀ
onꢀ theꢀ 50MHzꢀ output,ꢀ 33.3333MHzꢀ andꢀ 66.6666MHzꢀ clockꢀ
outputs.
•ꢀ Oneꢀfrequencyꢀselectableꢀ33/66/133MHzꢀLVCMOSꢀoutput
•ꢀ Oneꢀ32.256MHzꢀLVCMOSꢀoutput
•ꢀ Industrialꢀtemperatureꢀ-40°Cꢀtoꢀ85°C
•ꢀ Package:ꢀ56-pinꢀTSSOPꢀpackage
Pin Configuration
VDD
IREF
1
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
VDD
NC
3
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
100M_Q11-
100M_Q11+
100M_Q10-
100M_Q10+
VDD
4
5
6
7
8
GND
VDD
9
VDD
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
100M_Q4+
100M_Q4-
100M_Q5+
100M_Q5-
VDD
100M_Q9-
100M_Q9+
100M_Q8-
100M_Q8+
100M_Q7-
100M_Q7+
SCLK
Block Diagram
VDD
12
25 MHz
Clock Buffer/
crystal or
Crystal
12
2
SDATA
clock input
Oscillator
100M_OUT(0-11)
GND
GND
50M_OUT1
50M_OUT2
VDD
VDD
50M_OUT(1-2)
PLL, Dividers,
Buffers, and
Logic
100M_Q6+
100M_Q6-
33/66/133M_OUT1
VDD
33/66/133M_OUT1
GND
SCLK
32.256M_OUT1
VDD
SDATA
PD_RESET
32.256M_OUT1
GND
GND
VDD
NC
X2
8
PD_RESET
X1
ISET
475 Ohms
1%
GND
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Pin Description
Pin # Pin Name
Pin Type Pin Description
1
V
Power
3.3V Supply Pin
DD
2
IREF
Output
Connect to 475-Ohm resistor to set HCSL output drive current
No connect. Leave open
100MHz HCSL output
3
NC
4
100M_Q11-
100M_Q11+
100M_Q10-
100M_Q10+
Output
Output
Output
Output
Power
Power
Power
Output
Output
Output
Output
Output
Output
Input
5
100MHz HCSL output
6
100MHz HCSL output
7
100MHz HCSL output
8
V
V
3.3V Supply Pin
DD
DD
9
3.3V Supply Pin
10
11
12
13
14
15
16
17
18
19
GND
Ground
100M_Q9-
100M_Q9+
100M_Q8-
100M_Q8+
100M_Q7-
100M_Q7+
SCLK
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
SMBus compatible input clock. Supports fast mode 400kHz input clock.
SMBus compatible data line
Ground
SDATA
I/O
GND
Power
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
20
21
50M_Out1
50M_Out2
Output
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal
110kOhm pull-down.
22
23
24
V
Power
Power
Power
3.3V Supply Pin
Ground
DD
GND
V
3.3V Supply Pin
DD
32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
25
32.256M_Out1
Output
Power
26
27
GND
NC
GND
No connect. Leave open
Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values. When Byte0-Bit 6 = 0 (Hardware Control
Mode) PD RESET = high, all outputs are enabled
28
PD_RESET
Input
29
30
31
32
X1
X2
Input
Crystal input. Integrated 6pF capacitance
Crystal output. Integrated 6pF capacitance
3.3V Supply Pin
Output
Power
Power
V
DD
GND
(Continued)
GND
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Pin Description (Cont..)
Pin # Pin Name
Pin Type Pin Description
33
V
Power
Connect to 3.3V
DD
33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
34
33/66/133M_Out1 Output
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
100M_Q6-
100M_Q6+
Output
Output
Power
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
V
DD
GND
Power
Ground
V
Power
3.3V Supply Pin
DD
100M_Q5-
100M_Q5+
100M_Q4-
100M_Q4+
100M_Q3-
100M_Q3+
100M_Q2-
100M_Q2+
Output
Output
Output
Output
Output
Output
Output
Output
Power
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
V
DD
GND
Power
Ground
V
Power
3.3V Supply Pin
DD
100M_Q1-
100M_Q1+
100M_Q0-
100M_Q0+
Output
Output
Output
Output
Power
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
V
DD
GND
Power
Ground
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
50MHz Frequency Margining Table
FS3 FS2
FS1
FS0 50M_OUT1,ꢀ50M_OUT2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
nominal
nominalꢀ+ꢀ1%
nominalꢀ+ꢀ2%
nominalꢀ+ꢀ3%
nominalꢀ+ꢀ4%
nominalꢀ+ꢀ5%
nominalꢀ+ꢀ6%
nominalꢀ+ꢀ8%
nominalꢀ+ꢀ10%
nominalꢀ-ꢀ1%
nominalꢀ-ꢀ2%
nominalꢀ-ꢀ3%
nominalꢀ-ꢀ4%
nominalꢀ-ꢀ6%
nominalꢀ-ꢀ8%
nominalꢀ-ꢀ10%
33/66/133 MHz Frequency Margining Table
FS6
FS5
FS4
33M/66M/133M_OUT1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33.3333MHz
66.6666MHz +2%
66.6666MHz +1%
66.6666MHz +0%
66.6666MHz -2%
66.6666MHz -4%
66.6666MHz -6%
133.3333MHz
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49004AꢀisꢀaꢀslaveꢀonlyꢀSMBusꢀdeviceꢀthatꢀsupportsꢀindexedꢀblockꢀreadꢀandꢀindexedꢀblockꢀwriteꢀprotocolꢀusingꢀaꢀsingleꢀ7-bitꢀad-
dressꢀandꢀread/writeꢀbitꢀasꢀshownꢀbelow.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0/1
How to Write
1 bit 8 bits
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start
D2H
bit
Register
offset
Byte Count
= N
Data Byte
0
Data Byte
N - 1
Ack
Ack
Ack
Ack
…
Ack Stop bit
Note:
1.
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M:ꢀabbreviationꢀforꢀMasterꢀorꢀController;ꢀS:ꢀabbreviationꢀforꢀslave/clock)
1 bit 8 bits
1 bit
8 bits
1 bit
1 bit 8 bits 1 bit
8 bits
1 bit
8 bits
1 bit
…
8 bits
1 bit
1 bit
S:
S:
M: send
starting
databyte
location:
N
sends #
of data
bytes
that
will be
sent: X
sends
start-
sends ing
S:
M: Not
Ac-
knowl-
edge
M:
Start
bit
S:
sends
Ack
S:
M:
M:
S:
sends
Ack
M:
M:
sends
Ack
sends
data
byte
N+X-1
M:
Stop
bit
M: Send
"D2h"
sends Start Send
Ack bit "D3h"
…
Ack
data
byte
N
Byte 0: Spread Spectrum Control Register
Output(s)
Condition Affected
Power Up
Bit
Description
Type
Notes
0=spread off
Spread Spectrum Selection for 100MHz HCSL PCI-
Express clocks
All 100MHz HCSL
PCI Express outputs
7
RW
0
1 = -0.5% down spread
0 = hardware cntl
1 = soꢀware ctrl
Enables hardware or soꢀware control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
6
5
RW
RW
0
PD_RESET pin, bit 5
Soꢀware PD_RESET bit. Enables or disables all out-
puts
0 = disabled
1 = enabled
1
All outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
Frequency margining select bit FS3
Frequency margining select bit FS2
Frequency margining select bit FS1
4
3
2
RW
RW
RW
1
0
1
See 50MHz Frequency
Margining Table on
Page 3
50M_Out1 and 50M_
Out2
1
0
Frequency margining select bit FS0
RW
RW
0
1
0 = disabled
1 = enabled
Single-ended 50MHz
output 50M_Out2
OE for single-ended 50MHz output 50M_Out2
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
Description
0
1
X
0
(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
Enable outputs according to the SMBus default values; SMBus can control each output.
PD_RESET HW pin/signal = DON'T CARE
1
1
Byte 1: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
7
OE for 32.256M_Out1
RW
1
1
1
1
0
0
0
0
32.256M_Out1
6
5
4
3
2
1
0
OE for 50M_Out1
RW
RW
RW
RW
RW
RW
RW
50M_Out1
33/66/133M_Out1
100M_Q11
100M_Q10
100M_Q9
OE for 33/66/133M_Out1
OE for 100M_Q11 HCSL output
OE for 100M_Q10 HCSL output
OE for 100M_Q09 HCSL output
OE for 100M_Q08 HCSL output
OE for 100M_Q07 HCSL output
100M_Q8
100M_Q7
Byte 2: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
7
Frequency margining select bit FS6 RW
Frequency margining select bit FS5 RW
Frequency margining select bit FS4 RW
1
See 33/66/133MHz
Frequency Margin-
ing Table on Page 3
6
0
33/66/133M_Out1
Not Applicable
5
0
4 to 0
Reserved
R
Undefined
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Byte 3: Control Register
Power Up
Condition
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
7
OE for 100M_Q6 HCSL Output
RW
0
0
0
0
0
1
100M_Q6
6
5
4
3
2
OE for 100M_Q5 HCSL Output
OE for 100M_Q4 HCSL Output
OE for 100M_Q3 HCSL Output
OE for 100M_Q2 HCSL Output
OE for 100M_Q1 HCSL Output
RW
RW
RW
RW
RW
100M_Q5
100M_Q4
100M_Q3
100M_Q2
100M_Q1
1
0
OE for 100M_Q0 HCSL Output
Reserved
RW
R
1
100M_Q0
Undefined
Not Applicable
Byte 4 & 5: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
Byte 6: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
7
6
5
4
3
2
1
0
Revivsion ID bit 3
Revivsion ID bit 2
Revivsion ID bit 1
Revivsion ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
1
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
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StorageꢀTemperature........................................................ –65°Cꢀtoꢀ+150°C
AmbientꢀOperatingꢀTemperature
....................................... –40°Cꢀtoꢀ+85°C
PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
1
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
Units
V
V
V
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
ESD Protection
-0.5
4.6
4.6
DD
IH
IL
V
-0.5
-65
Ts
150
°C
V
V
Note:
2000
ESD
1.ꢀ Stressꢀbeyondꢀthoseꢀlistedꢀunderꢀ“AbsoluteꢀMaximumꢀRatings”ꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.
Maximum Ratings
(Aboveꢀwhichꢀusefulꢀlifeꢀmayꢀbeꢀimpaired.ꢀꢀForꢀuserꢀguidelines,ꢀnotꢀtested.)
Note:
MaximumꢀSupplyꢀVoltage,ꢀV ꢀ............................................................ 7V
DD
StressesꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀMAXIMUMꢀRAT-
INGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀ
aꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀ
atꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀ
theꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀ
Exposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀex-
tendedꢀperiodsꢀmayꢀaffectꢀreliability.
AllꢀInputsꢀandꢀOutputsꢀ...............................................–0.5VꢀtoꢀV +0.5V
DDꢀ
JunctionꢀTemperatureꢀ........................................................................125°C
PeakꢀSolderingꢀTemperature..............................................................260°C
DC Electrical Characteristics
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Operating Supply
Voltage
V
3.0
3.6
DD
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
2
V
DD
IH
IL
V
–0.3
0.8
SDATA, SCLK
SDATA, SCLK
0.7V
V
DD
IH
IL
DD
0.3V
DD
Operating Supply Cur-
rent
I
320
3.0
DD
mA
IDD at Output Disable
Condition
PD_RESET = 0
PD_RESET
216
Internal Pull-Up/Pull-
Down Resistor
R
C
/R
k–Ohm
pF
PU PD
All single-ended outputs
All input pins
75
6
Input Capacitance
IN
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Clock Frequency
SCLK Frequency
F
25
MHz
kHz
IN
100
400
Minimum Pulse Width
of PD_RESET Input
100
ns
Output Frequency
Error
FS0, FS6 = 0
32.256MHz
0
ppm
Output Frequency
Error
7
Output Rise/Fall Time t t
V =3.3V, 0.8V to 2.4V
DD
0.5
50
1
ns
%
r,
f
Output Clock Duty
Cycle
Measured at V /2
45
55
DD
High-Level Output
V
I
= -4mA
= -8mA
= 8mA
V
-0.4
OH
OH
DD
Voltage
High-Level Output
Voltage
V
OH
I
OH
2.4
V
Low-Level Output
Voltage
V
OL
I
OL
0.4
50MHz clock output
140
125
200
175
Peak-to-Peak Jitter
Cycle-to-Cycle Jitter
33/66/133MHz clock output
ps
32.256MHz clock output
50MHz clock output
115
120
120
150
175
160
33/66/133 MHz clock output
Clock Stabilization
Time from Power Up
3
10
ms
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Frequency
100
150
MHz
Cycle-to-Cycle Jitter
T
CC/Jitter
ps
Peak-to-Peak Phase
Jitter
Using PCIe jitter measure-
ment method
86
3.1
0
PCIe 2.0 RMS Phase
Jitter
PCIe 2.0 Test Method @
100MHz Output
J
ps
%
RMS2.0
Spread Modulation
Percentage
-0.5
Spread Modulation
Frequency
32
50
kHz
Duty Cycle
T
45
55
%
DC
Rising/Falling Edge
Rate
Note 3, 4
0.6
4.5
V/ns
V = 50%(measurement
T
Output Skew
T
Z
200
ps
OSKEW
threshold)
Clock Source DC Im-
pedance, single ended
50
Ohm
C-DC
High-Level Output
Voltage
Note 2, (R =33-Ohm,
S
T
V
0.65
0.71
0.95
OH
R =50-Ohm)
V
Low-Level Output
Voltage
V
OL
–0.20
–13
0
0.05
-18.5
0.55
I
OH
@ 6*I
I
OH
–14.2
mA
V
REF
Absolute Crossing
Point Voltage
V
CROSS
Note 2, 5, 6
Note 2, 5, 8
Note 3, 9, 10
Note 3, 7
0.25
Variation of VCROSS
over all rising clock
edges
V
140
mV
ppm
ns
CROSS Delta
Average Clock Period
Accuracy
T
T
–300
9.847
2800
10.203
PERIOD AVG
PERIOD ABS
Absolute Period
(including jitter and
spread spectrum)
(Continued)
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Notes:
1.ꢀ Measuredꢀatꢀtheꢀendꢀofꢀanꢀ8-inchꢀtraceꢀwithꢀaꢀ5pFꢀload.
2.ꢀMeasurementꢀtakenꢀfromꢀaꢀsingle-endedꢀwaveform.
3.ꢀMeasurementꢀtakenꢀfromꢀaꢀdifferentialꢀwaveform.
4.ꢀMeasuredꢀfromꢀ-150ꢀmVꢀtoꢀ+150ꢀmVꢀonꢀtheꢀdifferentialꢀwaveform.ꢀTheꢀsignalꢀisꢀmonotonicꢀthroughꢀtheꢀmeasurementꢀregionꢀforꢀriseꢀandꢀfallꢀtime.ꢀꢀ
Theꢀ300ꢀmVꢀmeasurementꢀwindowꢀisꢀcenteredꢀonꢀtheꢀdifferentialꢀzeroꢀcrossing.
5.ꢀMeasuredꢀatꢀcrossingꢀpointꢀwhereꢀtheꢀinstantaneousꢀvoltageꢀvalueꢀofꢀtheꢀrisingꢀedgeꢀofꢀ100M+ꢀequalsꢀtheꢀfallingꢀedgeꢀ100M–.
6.ꢀRefersꢀtoꢀtheꢀtotalꢀvariationꢀfromꢀtheꢀlowestꢀcrossingꢀpointꢀtoꢀtheꢀhighest,ꢀregardlessꢀofꢀwhichꢀedgeꢀisꢀcrossing.ꢀꢀ
Refersꢀtoꢀallꢀcrossingꢀpointsꢀforꢀthisꢀmeasurement.
7.ꢀ Definesꢀasꢀtheꢀabsoluteꢀminimumꢀorꢀmaximumꢀinstantaneousꢀperiod.ꢀThisꢀincludesꢀcycle-to-cycleꢀjitter,ꢀrelativeꢀPPMꢀtolerance,ꢀꢀ
andꢀspreadꢀspectrumꢀmodulation.
8.ꢀDefinedꢀasꢀtheꢀtotalꢀvariationꢀofꢀallꢀcrossingꢀvoltagesꢀofꢀrisingꢀ100M+ꢀandꢀfallingꢀ100M–.
9.ꢀ Referꢀtoꢀsectionꢀ4.3.2.1ꢀofꢀtheꢀPCIꢀExpressꢀBaseꢀSpecification,ꢀRevisionꢀ1.1ꢀforꢀinformationꢀregardingꢀPPMꢀconsiderations.
10.ꢀ 10)ꢀPPMꢀrefersꢀtoꢀpartsꢀperꢀmillionꢀandꢀisꢀaꢀDCꢀabsoluteꢀperiodꢀaccuracyꢀspecification.ꢀ1ꢀPPMꢀisꢀ1/1,000,000thꢀofꢀ100ꢀMHzꢀexactlyꢀorꢀ100ꢀHz.ꢀForꢀ300ꢀPPMꢀ
thereꢀisꢀanꢀerrorꢀbudgetꢀofꢀ100Hz/PPMꢀ*ꢀ300ꢀPPMꢀ=ꢀ30ꢀkHz.ꢀTheꢀperiodꢀisꢀmeasuredꢀwithꢀaꢀfrequencyꢀcounterꢀwithꢀmeasurementꢀwindowꢀsetꢀatꢀ100ꢀmsꢀorꢀ
greater.ꢀWithꢀspreadꢀspectrumꢀturnedꢀoffꢀtheꢀerrorꢀisꢀlessꢀthanꢀ±300ꢀppm.ꢀWithꢀspreadꢀspectrumꢀturnedꢀonꢀthereꢀisꢀanꢀadditionalꢀ+2500ꢀPPMꢀnominalꢀshiftꢀinꢀ
maximumꢀperiodꢀresultingꢀfromꢀtheꢀ-0.5%ꢀdownꢀspread.
Crystal Load Capacitors
If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the
output frequency.
C = Crystal's load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) *2
L
For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) *2 =18.
Application Notes
Crystal circuit connection
e following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the
CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the
target ppm of crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
CG2500003
Crystal�(CL�=�18pF)
XTAL_OUT
C2
33pF
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
Recommended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
Configuration test load board termination for HCSL Outputs
Rs
Clock
33Ω
5%
TLA
PI6C49004A
Rs
Clock#
33Ω
5%
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
475Ω
1%
1%
Figure 4. Configuration Test Load Board Termination
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PI6C49004A
PCIe®ꢀGen 2 Networking Clock Generator
DATE: 09/11/06
Notes:
DESCRIPTION: 56-pin, 240-mil wide TSSOP
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/EE
PACKAGE CODE: A56
3. Package Outline Exclusive of Mold Flash and Metal Burr
REVISION: M
DOCUMENT CONTROL #: PD-1502
06-0736
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
(1-3)
Ordering Information
Ordering Code
Package Code
Package Description
PI6C49004AAE
A
56-pin, Pb-free & Green, TSSOP, (A56)
Notes:
1.ꢀThermalꢀcharacteristicsꢀcanꢀbeꢀfoundꢀonꢀtheꢀcompanyꢀwebꢀsiteꢀatꢀwww.pericom.com/packaging/
2.ꢀEꢀ=ꢀPb-freeꢀandꢀGreen
3.ꢀAddingꢀanꢀXꢀsuffixꢀ=ꢀTape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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All trademarks are property of their respective owners.
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