PT7C4363W [PERICOM]
Real-time Clock Module (I2C Bus); 实时时钟模块（ I2C总线）
| 型号： | PT7C4363W |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Real-time Clock Module (I2C Bus) |
| 文件： | 总22页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Description
•
•
•
Using external 32.768kHz quartz crystal
The PT7C4363 serial real-time clock is a low-power
clock/calendar with a programmable square-wave output.
Supports I2C-Bus's high speed mode (400 kHz)
Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
Address and data are transferred serially via a 2-wire
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in the 24-
hour format indicator.
•
•
•
Programmable square wave output signal
Oscillator stop flag
Low backup current: typ. 500nA at VDD=3.0V and
TA=25°C
•
Operating range: 1.8V to 5.5V
Table 1 shows the basic functions of PT7C4363. More
details are shown in section: overview of functions.
Ordering Information
Part Number
Package
8-Pin DIP
8-Pin SOIC
PT7C4363P
PT7C4363W
Note: Lead free package is available by adding “E” after each
part number. For example: PT7C4363PE.
Table 1. Basic functions of PT7C4363
Item
Function
PT7C4363
Source: Crystal: 32.768kHz
Oscillator enable/disable
Oscillator fail detect
√
1
Oscillator
-
√
12-hour
Time display
-
24-hour
√
2
Time
Century bit
√
Time count chain enable/disable
Alarm interrupt
√
√
3
4
Interrupt
Timer interrupt output
√
Programmable square wave output (Hz)
1, 32, 1.024k, 32.768k
2-wire I2C bus
√
-
Communicat
3-wire bus
ion
5
6
Burst mode
-
Write protection
-
Control
External clock test mode
Power-on reset override
√
√
PT0207(07/05)
Ver: 0
1
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Block
Alarm Register
PT7C4363
Comparator
Timer
(Min, Hour, Day, Date)
X1
X2
CD
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
32.768
kHz
OSC
Counter Chain
CG
Address
Decoder
Address
Register
I /O
Control Register
SCL
SDA
Interface
(I2C)
INT
SQW
Timer / Alarm Interrupt Control
Square Wave Output Control
Shift Register
Note: PT7C4363 need to add a 10pF ~ 30pF capacitor between X1 and GND to get the accurate 32k frequency.
Recommended Layout for Crystal
PT7C4363
X1
X2
32.768kHz
Crystal
Local Ground plane
Layer 2
Guard Ring
(connect to gound)
Crystal Specifications
Parameter
Symbol
fO
ESR
CL
Min
Typ
32.768
Max
40
Unit
kHz
kΩ
Nominal Frequency
Series Resistance
Load Capacitance
10
pF
The crystal, traces and crystal input pins should be isolated from RF generating signals.
PT0207(07/05)
Ver: 0
2
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Configuration
PT7C4363
8
1
X1
VCC
7
6
5
2
3
4
X2
SQW
SCL
INT
SDA
GND
DIP-8
SOIC-8
Pin Description
Pin no.
Pin
Type
Description
1
X1
I
Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them.
Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
Interrupt Output. Open drain, active low.
2
3
4
X2
O
O
P
INT
GND
Ground.
Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The
SDA pin is open-drain output and requires an external pull-up resistor.
5
6
SDA
SCL
I/O
I
Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface.
Clock Output. Open drain. Four frequencies selectable: 32.768k, 1.024k, 32, 1Hz when
SQWE bit is set to 1.
7
8
SQW
VCC
O
P
Power.
PT0207(07/05)
Ver: 0
3
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Description
Overview of Functions
1. Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2. Alarm function
These devices have one alarm system that outputs interrupt signals from INTA for PT7C4363 or INT/OUT/SQW for PT7C4341
to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt
signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm.
3. Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, 32.768k Hz.
4. Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is
also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
5. Oscillator fail detect
When oscillator fail, OSF bit will be set.
6. Oscillator enable/disable
Only time count chain can be enable or disable by STOP bit..
7. Timer function
The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/60 Hz) and
enables or disables the timer. The timer counts down from software loaded 8-bit binary value. At the end of every countdown, the
timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt.
The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the
condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
8. Reset function
The PT7C4363 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus
logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0,
TESTC and AE which are set to logic 1.
PT0207(07/05)
Ver: 0
4
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Registers
1. Allocation of registers
Register definition
Addr.
Function (time range
BCD format)
(hex) *1
Bit 7
Bit 6
Bit 5
STOP*3
-
Bit 4
-
Bit 3
TESTC*4
AF*6
S8
Bit 2
-
Bit 1
-
Bit 0
-
TEST1*
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Control/status 1
Control/status 2
Seconds (00-59)
Minutes (00-59)
Hours (00-23)
-
-
2
-
OSF*8
×
TI/TP*5
S10
M10
H10
D10
×
TF*6
S4
AIE*7
S2
TIE*7
S1
S40
M40
×
S20
M20
H20
D20
×
M8
H8
M4
H4
D4
W4
MO4
Y4
M4
H4
D4
W4
×
M2
H2
M1
H1
×
Dates (01-31)
D8
D2
D1
×
×
Days of the week (00-06)
Months (01-12)
Years (00-99)
W2
MO2
Y2
W1
MO1
Y1
×
×
×
Century
Y80
AE*9
AE*9
AE*9
AE*9
SQWE
TE*10
MO10
Y10
M10
H10
D10
×
MO8
Y8
×
×
Y40
M40
×
Y20
M20
H20
D20
×
Alarm: Minutes (00-59)
Alarm: Hours (01-12)
Alarm: Dates (01-31)
Alarm: Weekday (00-06)
SQW control
M8
H8
M2
H2
M1
H1
D8
D2
D1
×
W2
RS1
TD1*11
W1
RS0
TD0*11
×
×
×
×
×
×
Timer control
×
×
×
×
×
Timer
Timer count down value
Caution points:
*1. PT7C4363 uses 8 bits for address. For excess 0FH address, PT7C4363 will not respond.
*2. EXT_CLK test mode select bit.
*3. When the bit is logic 1, time count chain stops but oscillator still runs.
*4. Power-on reset override enable bit.
*5. Timer interrupt output select bit.
*6. Alarm and timer interrupt flag bits.
*7. Alarm and timer interrupt enable bits.
*8. Oscillator fail indicates. Indicate clock integrity.
*9. Alarm enable bit. Alarm will be active when related time is matching if AE = 0.
*10. Timer enable bit.
*11. Timer source clock frequency select.
*12. All bits marked with "×" are not implemented. All bits marked with "-" are not used bits and should always be written with
logic 0. If read them, they could be logic 0 or 1.
PT0207(07/05)
Ver: 0
5
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2. Control and status register
Addr.
Description
D7
D6
D5
D4
D3
D2
-
D1
-
D0
-
(hex)
Control/status 1
(default)
TEST1
0
-
STOP
0
-
TESTC
1
00
Undefined
Undefined
Undefined Undefined Undefined
Control/status 2
(default)
-
-
-
TI/TP
0
AF
TF
AIE
0
TIE
0
01
0D
0E
0F
Undefined Undefined Undefined
Undefined Undefined
SQW control
(default)
SQWE
1
×
×
×
×
×
RS1
0
RS0
0
Undefined Undefined Undefined Undefined Undefined
Timer control
(default)
TE
0
×
×
×
×
×
TD1
1
TD0
1
Undefined Undefined Undefined Undefined Undefined
Timer
Timer count down value
Undefined
(default)
a) Timer
•
TE: Timer Enable bit.
TE
Data
Description
Default
0
1
Timer disabled
Timer enabled
Read / Write
•
TD1, TD0: timer source clock frequency select. These bits determine the source clock for the countdown timer.
TD1, TD0
Data
Timer source clock freq. (Hz)
00
4.096k
64
01
Read / Write
10
1
When not in use, TD1 TD0 should be set to 11 for power saving.
11
1/60
•
Timer:
Timer
Data
Description
Countdown Period = n / Source Clock Frequency
Read / Write
00~FF
Count down value (n)
For example: If TE = 1, TD1 TD0 = 10, Timer = 03 are written into PT7C4363, timer counts down every 1 second from 03 to 01
then 03 cycled.
PT0207(07/05)
Ver: 0
6
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
b) Timer Interrupt
•
TIE: Timer Interrupt Enable bit.
TIE
Data
Description
Default
0
1
Timer interrupt disabled
Timer interrupt enabled
Read / Write
•
TF: Timer Flag
TF
Data
Description
0
1
0
1
Timer flag inactive
Read
Timer flag active. At the end of a timer countdown, TF is set to 1.
Timer flag is cleared
Write
Timer flag remains unchanged
•
TI/TP: Timer Interrupt output select
TI/TP
Data
Description
0
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to source clock frequency and timer count down value (subject to
the status of TIE).
INT negative pulse width (s)
Source clock
(Hz)
n = 1
n > 1
1
1
4096
64
1
/
/
8192
4096
Read / Write
1
1
/
/
128
64
1
1
1
/
/
64
64
1
1
1/60
/
/
64
64
Note: TF and INT become active simultaneously.
n = loaded countdown value. Timer stopped when n = 0.
Example 1: If TE = 1, TD1 TD0 = 00, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer register counts
down every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/4096 seconds width. See Fig.1.
4.096kHz internal clock
Timer=02
Timer=01
Timer=03
Set TF=1
Timer=02
Timer=01
Timer=03
INT
Fig.1 Example 1 of timer interrupts
PT0207(07/05)
Ver: 0
7
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Example 2: If TE = 1, TD1 TD0 = 10, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer counts down
every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/64 seconds width. See Fig.2.
1Hz internal clock
Timer=02
Timer=01
Timer=03
Set TF=1
Timer=02
1/64
INT
Fig.2 Example 2 of timer interrupts
c) Alarm Interrupt
•
AIE: Alarm Interrupt Enable bit.
AIE
Data
Description
Description
Default
0
1
Alarm interrupt disabled
Alarm interrupt enabled
Read / Write
•
AF: Alarm Flag
AF
Data
0
1
0
1
Alarm flag inactive
Read
Alarm flag active
Alarm flag is cleared
Alarm flag remains unchanged
Write
d) SQW control
•
SQWE: SQW output clock enable bit.
SQWE
Data
Description
0
1
the SQW output is inhibited and SQW output is set to high-impedance
the SQW output is activated
Read / Write
Default
Default
•
RS1, RS0: SQW output frequency select.
RS1, RS0
Data
SQW output freq. (Hz)
00
32.768k
1.024k
32
01
Read / Write
10
11
1
PT0207(07/05)
Ver: 0
8
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
e) Time count
•
STOP
STOP
Data
0
Description
Default
RTC source clock runs.
Read / Write
All RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped
(SQW at 32.768 kHz is still available)
1
f) Test
•
TEST1
TEST1
Data
Description
Default
0
1
Normal mode.
Read / Write
EXT_CLK test mode.
•
TESTC
TESTC
Data
Description
0
1
Power-on reset override facility is disabled; set to logic 0 for normal operation.
Power-on reset override may be enabled
Read / Write
Default
3. Time Counter
Time digit display (in BCD code):
•
•
•
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Seconds
(default)
OSF*1
1
S40
S20
S10
S8
S4
S2
S1
02
03
04
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
M40 M20 M10 M8 M4 M2 M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Minutes
(default)
×
0
Hours
×
0
×
0
H20
H10
H8
H4
H2
H1
(default)
Undefined Undefined Undefined Undefined Undefined Undefined
*1 Note: Indicate clock integrity. When the bit is 1, the clock integrity is no longer guaranteed and the time need be adjusted.
PT0207(07/05)
Ver: 0
9
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4. Days of the week Counter
The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that
correspond to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on).
Illogical time and date entries result in undefined operation.
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
Days of the week
(default)
×
0
×
0
×
0
×
0
×
0
W4
W2
W1
06
Undefined Undefined Undefined
5. Calendar Counter
The data format is BCD format.
•
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
•
•
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D8
D2
D4
D1
D2
D0
D1
Dates
×
0
×
0
D20
D10
05
07
08
(default)
Undefined Undefined Undefined Undefined Undefined Undefined
Months
Century*1
Undefined
×
0
×
0
M10
Undefined Undefined Undefined Undefined Undefined
Y10 Y8 Y4 Y2 Y1
M8
M4
M2
M1
(default)
Years
Y80
Y40
Y20
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
*1: The century bit is toggled when the years register overflows from 99 to 00.
6. Alarm Register
PT7C4363: Alarm Register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Alarm: Minutes
(default)
AE*1
M40
M20
M10
M8
M4
M2
M1
09
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Alarm: Hours
(default)
AE*2
H20
Undefined Undefined Undefined Undefined Undefined Undefined
D20 D10 D8 D4 D2 D1
Undefined Undefined Undefined Undefined Undefined Undefined
H10
H8
H4
H2
H1
×
0A
0B
0C
Undefined
AE*3
0
Alarm: Dates
(default)
×
0
Undefined
AE*4
Alarm: Weekday
(default)
W4
W2
W1
×
×
×
×
Undefined
0
0
0
0
Undefined Undefined Undefined
*1 Note: Minute alarm enable bit.
*2 Note: Hour alarm enable bit.
*3 Note: Date alarm enable bit.
*4 Note: Weekday alarm enable bit.
PT0207(07/05)
Ver: 0
10
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Alarm Function
Related register
Register definition
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TF
Bit 1
AIE
Bit 0
TIE
01
02
03
04
05
06
09
0A
0B
0C
Control/status 2
Seconds
-
-
-
TI/TP
AF
OSF
×
S40
M40
×
S20
M20
H20
D20
×
S10
M10
H10
D10
×
S8
M8
H8
D8
×
S4
M4
H4
D4
W4
M4
H4
D4
S2
M2
H2
D2
W2
M2
H2
D2
W2
S1
M1
H1
D1
W1
M1
H1
D1
W1
Minutes
Hours
×
Dates
×
×
Days of the week
Alarm: Minutes
Alarm: Hours
Alarm: Dates
Alarm: Weekday
×
×
AE
M40
×
M20
H20
D20
×
M10
H10
D10
×
M8
H8
D8
×
AE
AE
AE
×
×
W4
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable
(AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled
comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it
will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE
at logic 1 will be ignored.
EXT_CLK Test Mode and POR override
1. EXT_CLK Test Mode
A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the
operation of the RTC. The test mode is entered by setting bit TEST1 in control/status1 register. Then pin SQW becomes an input.
The test mode replaces the internal 64 Hz signal with the signal applied to pin SQW. Every 64 positive edges applied to pin SQW
will then generate an increment of one second.
The signal applied to pin SQW should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64
Hz clock, now sourced from SQW, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into
a known state by using bit STOP. When bit STOP is set, the pre-scaler is
reset to 0 (STOP must be cleared before the pre-scaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive edges on SQW. Thereafter, every 64 positive
edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no
assumption as to the state of the pre-scaler can be made.
PT0207(07/05)
Ver: 0
11
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Operation example:
1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1)
2. Set STOP (control/status 1, bit STOP = 1)
3. Clear STOP (control/status 1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to SQW
6. Read time registers to see the first change
7. Apply 64 clock pulses to SQW
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
2. Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these
types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of
this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Fig 6.4.2. All timings are
required minimums.
Once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e.
entry into the EXT_CLK test mode via I2C-bus access.
The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override
mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent from entering the POR
override mode.
Power up
Override active
Fig.3 POR override sequence
PT0207(07/05)
Ver: 0
12
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Communication
1. I2C Bus Interface
a) Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
b) System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Vcc
RP
RP
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
Fig.4 System configuration
PT0207(07/05)
Ver: 0
13
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
c) Starting and Stopping I2C Bus Communications
Fig.5 Starting and stopping on I2C bus
START condition, repeated START condition, and STOP condition
•
•
•
START condition
SDA level changes from high to low while SCL is at high level
STOP condition
SDA level changes from low to high while SCL is at high level
Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
d) Data Transfers and Acknowledge Responses during I2C-BUS Communication
•
Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
PT0207(07/05)
Ver: 0
14
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
•
Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
8
9
2
1
SDA from transmitter
(sending side)
Release SDA
Low active
ACK signal
SDA from receiver
(receiving side)
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
e) Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Slave address
Operation
Transfer data
R / W bit
bit 0
bit 7
1
bit 6
0
bit 5
1
bit 4
0
bit 3
0
bit 2
0
bit 1
1
Read
A3 h
A2 h
1 (= Read)
0 (= Write)
Write
2. I2C Bus’s Basic Transfer Format
S
Start indication
P
Stop indication
A
A
RTC Acknowledge
Sr
Restart indication
Master Acknowledge
PT0207(07/05)
Ver: 0
15
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
a) Write via I2C bus
Addr. setting
bit
bit
bit
bit
bit
bit
bit
bit
Slave address (7 bits)
S
A
A
A
P
write
0
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
Start
Stop
A
C
K
A
C
K
A
C
K
Slave address + write specification
Write data
Address
Specifies the write start address.
b) Read via I2C bus
•
Standard read
Slave address (7 bits)
Addr. setting
S
A
A
write
1
0
1
0
0
0
1
0
Start
A
C
K
A
C
K
Slave address + write specification
Address
Specifies the read start address.
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
/
A
Slave address (7 bits)
Sr
A
A
P
Read
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
Restart
A
C
K
A
C
K
Stop
N
O
Data read (1)
Data is read from the specified start
address and address auto increment.
Data read (2)
Address auto increment to set the
address for the next data to be read.
Slave address + read specification
A
C
K
•
Simplified read
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
/
A
Slave address (7 bits)
S
A
A
P
Read
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
Start
A
C
K
A
C
K
Stop
N
O
Data read (2)
Data read (1)
Slave address + read specification
Address register auto increment to set
the address for the next data to be
read.
Data is read from the address pointed
by the internal address register and
address auto increment.
A
C
K
Note:
1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications.
2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
PT0207(07/05)
Ver: 0
16
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Maximum Ratings
o
o
Storage Temperature....................................................................................................................... -65 Cto +150 C
o
o
Ambient Temperature with Power Applied........................................................................... -40 Cto +85 C
Supply Voltage to Ground Potential (Vcc to GND) ..........................................................-0.3V to +6.5V
DC Input (All Other Inputs except Vcc & GND)................................................................-0.3V to (Vcc+0.3V)
DC Output Voltage (SDA, /INTA, /INTB pins).................................................................. -0.3V to +6.5V
Power Dissipation............................................................................................................................ 320mW (Depend on package)
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol
Description
Min
Type
Max
Unit
V
VCC
VIH
VIL
TA
Power voltage
1.8
0.7 VCC
-0.3
-
-
-
-
5.5
VCC+0.3
0.3 VCC
85
Input high level
Input low level
Operating temperature
-40
ºC
PT0207(07/05)
Ver: 0
17
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical Characteristics
Unless otherwise specified, GND =0V, VCC = 1.8 ~ 5.5 V, TA = -40 °C to +85 °C, fOSC = 32.768kHz.
Sym.
Description
Pin
Conditions
Min Typ
Max Unit
Interface inactive. TA = 25°C 1)
Interface active. fSCL = 400kHz 1)
1.0
1.8
5.5
Supply voltage
VCC
5.5
V
VCC
Supply voltage for clock
data integrity
VCC
1.0
0.9
fSCL = 400kHz
fSCL = 100kHz
VCC = 5.0V
800
µA
Interface active
200
275
250
225
500
400
400
825
550
425
950
650
500
550
TA = 25°C
Interface
nA
nA
nA
nA
VCC = 3.0V
500
450
inactive (fSCL
0Hz), pin 7
disabled 2)
=
VCC = 2.0V
VCC = 5.0V
VCC = 3.0V
750
TA = -40 ~
85°C
650
ICC Supply current
VCC
VCC = 2.0V
600
VCC = 5.0V
VCC = 3.0V
1600
1000
800
Interface
TA = 25°C
inactive (fSCL
0Hz), pin 7
enabled at
32kHz 2)
=
VCC = 2.0V
VCC = 5.0V
VCC = 3.0V
VCC = 2.0V
1700
1100
900
TA = -40 ~
85°C
VIL1 Low-level input voltage
SCL
0
0.7VCC
-3
0.3VCC
VCC
V
VIH1 High-level input voltage SCL
SDA
VOL = 0.4V, VCC = 5V
IOL Low-level output voltage
mA
/INT, SQW VOL = 0.4V, VCC = 5V
SCL
-1
IIL Input leakage current
±1
±1
µA
µA
IOZ Output current when OFF
Note:
1) For reliable oscillator start-up at power-up: VCC(min)power-up = VCC(min) + 0.3 V.
2) Timer source clock = 1/60 Hz, voltage of SCL and SDA is VCC or GND.
PT0207(07/05)
Ver: 0
18
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AC Electrical Characteristics
Sym
VHM
VHL
Description
Rising and falling threshold voltage high
Rising and falling threshold voltage low
Value
0.8 VCC
0.2 VCC
Unit
V
V
Signal
VHM
VLM
tr
tf
Over the operating range
Symbol
Item
Min.
Typ.
Max.
Unit
kHz
µs
fSCL
SCL clock frequency
400
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT1
tHD;DAT2
tSU;STO
tBUF
START condition set-up time
START condition hold time
0.6
0.6
200
35
µs
ns
Data set-up time (RTC read/write)
Data hold time (RTC write)
Data hold time (RTC read)
STOP condition setup time
Bus idle time between a START and STOP condition
When SCL = "L"
ns
0
µs
0.6
1.3
1.3
0.6
µs
µs
tLOW
tHIGH
tr
µs
When SCL = "H"
µs
Rise time for SCL and SDA
Fall time for SCL and SDA
Allowable spike time on bus
Capacitance load for each bus line
0.3
0.3
50
µs
tf
µs
ns
tSP*
CB
400
pF
* Note: Only reference for design.
tSU;STA
S
Sr
P
SCL
tLOW
tHIGH
tHD;STA
tSP
fSCL
tBUF
SDA
tSU;DAT
tHD;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;STA
S
P
Start condition
Stop condition
Sr
Restart condition
PT0207(07/05)
Ver: 0
19
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Information
P/PE PDIP-8
8
.240
.280
6.09
7.11
1
.355
7.62
8.25
.400
9.01
.300
10.16
.325
.210
Max
5.33
0O
15o
.008
.014
SEATING
PLANE
0.20
0.35
.430
Max
.015 Min 0.381
.356
10.92
.115
.150
.100
typical
.014
.022
2.921
3.81
DENOTES DIMENSIONS
IN MILLIMETERS
X.XX
X.XX
.558
2.54
Note
1) Controlling dimensions in inches.
2) Ref: JDDEC MS-001 BA
PT0207(07/05)
Ver: 0
20
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
W/WE SOIC-8
8
.0099
.0196
x 45o
0.25
0.50
.149
.157
3.78
3.99
0-8o
0.19
0.25
.0075
.0098
.016
.050
0.40
1.27
1
.2284
.189
.196
4.80
5.00
.2440
5.80
6.20
.016
.026
0.406
0.660
1.35
1.75
.053
.068
DENOTES DIMENSIONS
IN MILLIMETERS
X.XX
X.XX
SEATING
PLANE
REF
Note:
1) Controlling dimensions in
millimeters.
2) Ref: JDDEC MS-012 AA
.050
BSC
.0040
.0098
0.10
0.25
1.27
.013
.020
0.330
0.508
PT0207(07/05)
Ver: 0
21
Data Sheet
PT7C4363
Real-time Clock Module (I2C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes
Pericom Technology Inc.
Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com
China:
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China
Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181
Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong
Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.:
3545 North First Street, San Jose, California 95134, USA
Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the
circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other
rights, of Pericom Technology Incorporation.
PT0207(07/05)
Ver: 0
22
相关型号：
PT7C4363WE
Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, PDSO8, GREEN, MS-012E/AA, SOIC-8
PERICOM
PT7C4363WEX
Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, PDSO8, GREEN, MS-012E/AA, SOIC-8
PERICOM
©2020 ICPDF网 联系我们和版权申明