PT7C4372A [PERICOM]
Real-time Clock Module;
| 型号： | PT7C4372A |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Real-time Clock Module |
| 文件： | 总30页 (文件大小：716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PT7C4372A/4372C
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Real-time Clock Module (I2C Bus)
Product Features
Product Description
PT7C4372A/C are I2C bus interface-compliant real-time
clocks that have been adjusted for high precision. In
addition to providing a function for generating six types
of interrupts, a dual alarm function, an oscillation stop
detection function (used to determine presence of valid
internal data at power-on), they includes a digital clock
precision adjustment function that can be used to set
various levels of precision.
• External quartz oscillator 32.000kHz and 32.768kHz
selectable.
• Supports I2C-Bus's high speed mode (400 kHz)
• Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
• Select between 12-hr and 24-hr clock display
• Auto calculation of leap years until 2099
• Built-in high-precision clock precision control logic
• Interrupt generation function (cycle time range: 1
month to 0.5 seconds, includes interrupt flags and
interrupt stop function)
Since the internal oscillation circuit is driven at a
constant voltage, 32-kHz clock output is stable and free
of voltage fluctuation effects.
• Alarm functions (Alarm_A: Day/Hour/Min)
• 32-kHz clock output (/INTB output)
• Oscillation stop detection function (used to determine
presence of internal data)
Table 1 shows the diverse functions of the two RTC
circuits. More details are shown in section Overview of
Functions.
• Wide Time keeping voltage range: 1.3 V to 6 V
• Wide interface voltage range: 1.8 V to 6 V
• Low current consumption: 0.4 µA/3.0 V (Typ.)
Table 1. Diverse functions of RTC circuits
Item
Function
PT7C4372A/4372C
1
Clock
Unit 3.051ppm for 32.768kHz crystal;
3.125ppm for 32.000kHz crystal
2
Clock adjustment
3
4
Period interrupt
Alarm
Output from /INTA and /INTB
/INTA: Alarm_A; /INTB: Alarm_B
5
6
Oscillation detect
32-kHz clock output
via /INTB enabled by register
7
8
I2C bus interface with CPU
Crystal
External, 32.768kHz or 32.000kHz selectable
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Pin Assignment
PT7C4372A/C
1
8
INTB
SCL
Vcc
2
3
4
7
6
5
OSCIN
SDA OSCOUT
GND
INTA
8 pin TSSOP
8 pin SOIC
Pin Description
Pin
Pin No
Type
Description
Name
1
2
3
/INTB
SCL
O
Interrupt B (Open Drain). It outputs alarm interrupts and periodic interrupts.
Serial Clock Line. It is for I2C communication. Data input and output across SDA pin is
synchronized with this clock. Up to 6V beyond Vcc may be input.
Serial Data Line (Open Drain output). This line is for transferring I2C bus format data.
When input, up to 6V beyond VCC may be used. When output, it is an open drain output
pin.
I
SDA
I/O
4
5
6
7
8
GND
/INTA
OSCOUT
OSCIN
Vcc
P
O
O
I
Ground
Interrupt A (Open Drain). It outputs alarm interrupts and periodic interrupts.
Oscillator Circuit Output. Together with OSCIN, an crystal oscillator is connected
between them.
Oscillator Circuit Input. See OSCOUT pin description.
P
Power
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Function Block
Alarm_A Register
Comparator_A
(Week,Min,Hour)
32kHz Output Control
Divider
Alarm_B Register
(WEEK,MIN,HOUR)
Comparator_B
OSCIN
CG
CD
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
OSC
Div
Correction
OSCOUT
Address
Decoder
Address
Register
OSC
Detect
SCL
SDA
I /O
Control
/INTA
Interrupt Control
Shift Register
/INTB
Maximum Ratings
o
o
StorageTemperature...............................................................................................................-65 Cto +150 C
o
o
AmbientTemperaturewithPowerApplied......................................................................-40 Cto +85 C
SupplyVoltagetoGroundPotential(VcctoGND) ......................................................-0.3Vto +6.5V
DCInput(AllOtherInputsexceptVcc&GND)...........................................................-0.3Vto (Vcc+0.3V)
DCOutputVoltage(SDA,/INTA,/INTBpins)..............................................................-0.3Vto +6.5V
DCOutputCurrent(FOUT).................................................................................................-0.3Vto (Vcc+0.3V)
PowerDissipation.................................................................................................................... 320mW(dependon package)
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol
Description
Min
Type
Max
Unit
VCC
1.8
-
6
Power voltage
V
VOSC
VPUP
TA
Timekeeping voltage
1.3
-0.3
-40
-
-
-
5.5
5.5
85
Applied voltage when OFF (SCL, SDA, /INTA, /INTB pins)
Operating temperature
ºC
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Frequency Characteristics
Conditions
TA = +25°C
Vcc = 3.0 V
Rating
Unit
Symbol
Description
10 -6
Frequency tolerance
Stability AC: 0 ± 5
f / f
Frequency voltage
characteristics
TA = +25°C
Vcc = 2 V to 5 V
10 -6 / V
10 -6
f / V
Top
tSTA
fa
± 2 Max.
+10 / -120
3 Max.
Frequency temperature
characteristics
TA = -10°C to +70°C ,
Vcc = 3.0 V; +25°C reference
TA = +25°C
Vcc = 3 V
Oscillation start up time
Aging
s
TA = +25°C
VCC=3.0 V; first year
10 -6 / year
± 5 Max.
DC Electrical Characteristics
Unless otherwise specified, GND = 0 V, VCC = 3 V, TA = -40 °C to +85 °C
Sym.
Item
Pin
Conditions
Min
Typ Max Unit
ICC1
Interface is active at 400kHz
-
-
150
A
Interface is inactive, enable 32768Hz
ICC2
ICC3
-
-
500
1000
nA
Current consumption
Vcc
SQW wave output
Interface is inactive, disable 32768Hz
400
800
nA
SQW wave output
VIL Low-level input voltage
VIH High-level input voltage
-
-0.3
0.8VCC
1.0
-
-
-
-
-
0.2VCC
V
V
SCL, SDA,
FOE
-
6.0
-
/INTA,/INTB
SDA
VOL = 0.4
IOL Low-level output current
IIL Input leakage current
mA
A
A
VOL = 0.6
6.0
-
SCL
VI = 5.5V or GND, VCC = 5.5V
-1
1
SDA,
IOZ Output current when OFF
VO = 5.5V or GND, VCC = 5.5V
-1
-
1
/INTA,/INTB
AC Electrical Characteristics
Sym
VHM
VHL
Description
Rising and falling threshold voltage high
Rising and falling threshold voltage low
Value
0.8 VCC
0.2 VCC
Unit
V
V
Signal
VHM
VLM
tr
tf
*
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Unless otherwise specified: GND = 0 V, VCC = 2 V to 5.5 V, TA = -40 °C to +85 °C, CL = 50 pF
Symbol
fSCL
Item
Min.
-
Typ.
Max.
Unit
kHz
s
s
ns
SCL clock frequency
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT1
tHD;DAT2
tSU;STO
tBUF
START condition set-up time
START condition hold time
0.6
0.6
200
35
0
-
-
Data set-up time (RTC read/write)
Data hold time (RTC write)
Data hold time (RTC read)
STOP condition setup time
Bus idle time between a START and STOP condition
When SCL = "L"
-
-
ns
-
s
s
s
s
s
s
s
ns
0.6
1.3
1.3
0.6
-
-
-
tLOW
tHIGH
tr
-
When SCL = "H"
-
Rise time for SCL and SDA
Fall time for SCL and SDA
Allowable spike time on bus
Duration of staring to stopping
0.3
0.3
50
0.5
tf
-
tSP*
-
tD
-
s
* Note: only reference for design
tSU;STA
S
Sr
P
SCL
tLOW
tHIGH
tHD;STA
tSP
fSCL
tBUF
SDA
tSU;DAT
tHD;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;STA
tD
S
P
Start condition
Stop condition
Sr
Restart condition
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Function Description
Alarm function
Overview of Functions
PT7C4372A/C
This module is has two alarm system (Alarm_A and
Alarm_B) that outputs interrupt signals from /INTA or
/INTB to CPU when the day of the week, hour or minute
corresponds to the setting. Each of them may output
interrupt signal separately at a specified time. The alarm
may be selectable between on and off for each day of the
week, thus allowing outputting alarm everyday or on a
specific day of the week.
Clock function
CPU can read or write data including the year (last two
digits), month, date, day, hour, minute, and second. Any
(two-digit) year that is a multiple of 4 is treated as a leap
year and calculated automatically as such until the year 2099.
Clock precision adjustment function
They have two internal oscillation circuit capacitors, so that
an oscillation circuit may be configured simply by
externally connecting a crystal. Either 32.768kHz or
32.000kHz crystal may be selected to setting the internal
register appropriately.
The Alarm_A is output from the /INTA pin while the
Alarm_B is output from either the /INTA or the /INTB pins.
Polling is possible separately for each alarm function.
Oscillation stop detection function, power drop detection
function (voltage monitoring function), and power-on
reset detection function
The clock precision can be adjusted forward or back in units
of ±3.051 ppm (32.768kHz crystal) or ±3.125 ppm
(32.000kHz crystal) and oscillation frequency can be
adjusted in ±189 ppm (32.768kHz crystal) or ±194 ppm
(32.000kHz crystal).
PT7C4372A/ C have only oscillation stop detection function.
The oscillation stop detection function uses registers to
record if clock data is valid or invalid. This function may be
used to determine if the PT7C4372A/C supply power has
been booted from 0V and if it has been backed up.
This function can be used to implement a higher-precision
clock function, such as by:
Enabling higher clock precision throughout the year by
taking seasonal clock precision adjustments into
account in advance, or
Enabling correction of temperature-related clock
Interface with CPU
Data is read and written via the I2C bus interface using two
signal lines: SCL (clock) and SDA (data).
precision variation in systems that include
temperature detecting function.
a
Since the output of the I/O pin of SDA is open drain, a pull-
up resistor should be used on the circuit board if the CPU
output I/O is also open drain.
Periodic interrupt
PT7C4372A/C
Periodic interrupts can be output via the /INTA and /INTB
The SCL's maximum clock frequency is 400 kHz, which
supports the I2C bus's high-speed mode.
pins.
Select among five Periodic frequency settings: 2 Hz (every
0.5 seconds), 1 Hz (every second), 1/60 Hz (every minute),
1/3600Hz (every hour), or monthly.
Select among two output waveforms for periodic interrupts:
ordinary pulse waveform (2 Hz or 1 Hz) or waveforms
(every second, minute, hour, or month) for CPU-level
interrupts that can support CPU interrupts.
32-kHz clock output
The 32.768 kHz clock (32.768kHz crystal) or 32.000kHz
clock (32.000kHz crystal) can be output via the /INTB by
setting corresponding register.
Note: The precision of this 32.768 kHz clock output via the
FOUT pin can not be adjusted (even when using the clock
precision adjustment function).
A polling function is also provided to enable monitoring of
pin states via registers.
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Registers
Allocation of registers
Addr.
0
Function
Bit 7
Bit 6
S40
Bit 5
S20
Bit 4
S10
Bit 3
S8
Bit 2
S4
Bit 1
S2
Bit 0
S1
*5
Second
-
1
2
Minutes
-
M40
M20
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
H20 or
P, /A
Hours
-
-
3
Days of the week
Days
-
-
-
D20
-
-
-
W4
W2
W1
4
-
-
-
D10
D8
D4
D2
D1
5
Months
-
M10
Y10
M8
M4
M2
M1
6
Years
Y80
Y40
F6
Y20
F5
Y8
Y4
Y2
Y1
7
Time Trimming
Alarm_A: Minute
Alarm_A: Hour
Alarm_A: Day
Alarm_B: Minute
Alarm_B: Hour
Alarm_B: Day
Control 1
/XSL
F4
F3
F2
F1
F0
8
-
AM40
-
AM20
AM10
AH10
AW4
BM10
BH10
BW4
SL1
AM8
AH8
AW3
BM8
BH8
BW3
TEST*2
/CLEN
AM4
AH4
AW2
BM4
BH4
BW2
CT2
CTFG
AM2
AH2
AW1
BM2
BH2
BW1
CT1
AAFG
AM1
AH1
AW0
BM1
BH1
BW0
CT0
BAFG
AH20 or
AP, /A
9
-
A
B
C
D
E
F
-
AW6
BM40
-
AW5
-
BM20
BH20 or
BP, /A
-
-
AALE
-
BW6
BALE
-
BW5
SL2
ADJ or
XSTP*3
Control 2
/12, 24
Caution points:
*1. All bits marked with "-" are read-only bits. Their value when read is always "0".
*2. The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit.
*3. ADJ is for write and XTSP is for read operation. The XTSP bit is set to “0” by writing data into the control register 2 for
normal oscillation. When XSTP is set to “1”, the Time Trimming register, Control 1 register, /CLEN and TEST bits are reset
to “0”.
*4. All bits marked with "-" are read-only bits. Their value when read is always "0".
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Control register 1
PT7C4372A
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
(default)
AALE
0
BALE
0
SL2
0
SL1
0
TEST
0
CT2
0
CT1
0
CT0
0
E
PT7C4372C
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
(default)
AALE
0
BALE
0
SL2
0
SL1
0
TEST
0
CT2
0
CT1
1
CT0
1
E
AALE, BALE
Alarm_A, Alarm_B enable bits.
AALE, BALE
Read / Write
Data
Description
Default
0
1
Alarm_A (Alarm_B) correspondence action invalid
Alarm_A (Alarm_B) correspondence action valid
See section “Alarm Function” for more detail.
SL2, SL1
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
0
SL1
0
Description
Default
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
0
1
1
0
1
1
TEST
TEST
Data
Description
Default
0
1
Ordinary operation mode
Test mode
Read / Write
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0
Periodic interrupt output select bits.
Description
Cycle / Falling Timing
CT2
CT1
CT0
Wave Form Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
Off (“H”)
Default
-
Fixed at “L”
2Hz (duty 50%)
1Hz (duty 50%)
Pulse
Pulse
Level
Level
Level
Level
Every second (synchronized with second count up)
Every minute (Occurs when seconds reach ":00")
Every hour (Occurs when minutes and seconds reach "00:00")
Every month (Occurs at 00:00:00 on first day of month)
See section 6.5 for more detail.
Control Register 2
PT7C4372A
Addr. Description
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
(default)
-
-
/12, 24
ADJ or XSTP
1
/CLEN
0
CTFG
0
AAFG
0
BAFG
0
F
0
0
Undefined
D4 when read is used as ADJ, when write is used as XSTP.
PT7C4372C
Addr. Description
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
F
-
-
/12, 24 ADJ or XSTP /CLEN
CTFG
0
AAFG
0
BAFG
0
(default)
0
0
1
1
1
D4 when read is used as ADJ, when write is used as XSTP.
/12, 24
/12, 24 time display selection bit.
/12, 24 Data
Description
* Default
0
1
12-hour time display
24-hour time display
Read/
Write
See section “Alarm Function” for more detail.
PT7C4372C
/12, 24 time display selection bit.
/12, 24 Data
Description
0
1
12-hour time display
24-hour time display
Read/
Write
* Default
See section “Alarm Function” for more detail.
12-07-0001
PT0150-8 07/04/12
9
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
ADJ or XSTP
ADJ: 30 second adjust bit. Second is adjusted within 122s (within 125s when 32.000kHz crystal is used) from writing
operation to ADJ.
ADJ
Data
0
Description
Ordinary operation.
Write
Second adjustment. 1) For second range from “00” to “29”, second is reset to “00”;
1
2) For second range from “30” to “59”, second is reset to “00” and minute is incremented by 1.
XSTP: oscillator halt sensing bit.
XSTP
Data
0
Description
Ordinary oscillation.
Read
Default
1
Oscillator halts sensing.
See section “Oscillation Stop Detection”.
/CLEN
PT7C4372A FOUT 32-kHz clock output enabled bit.
Data
0
Description
/CLEN
Default
32-kHz clock (frequency same as crystal’s) output enabled.
Read
1
32-kHz clock output disabled.
PT7C4372C FOUT 32-kHz clock output enabled bit.
Data
0
Description
/CLEN
32-kHz clock (frequency same as crystal’s) output enabled.
Read
1
32-kHz clock output disabled.
Default
CTFG
CTFG
Data
0
Description
Default
Default
Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read
Read
1
0
1
Periodic interrupt output ON status; /INTA or /INTB= "L"
A "0" can be written only when the periodic interrupt is in level mode, at which time the
/INTA or /INTB pin is set to OFF (“H”) status. After a "0" is written, the value still becomes
"1" again at the next cycle.
Write
Setting prohibited
See section “Related Registers” for more detail.
12-07-0001
PT0150-8 07/04/12
10
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AAFG, BAFG
AAFG,BAFG Data
0
Description
Alarm register does not match current time
Alarm register match current time
Default
Default
Read
1
0
/INTA or /INTB pin = OFF (H)
Setting prohibited
Write
1
See section “Alarm Function” for more detail.
Time Counter
Time digit display (in BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Seconds
(default)
-
S40
S20
S10
S8
S4
S2
S1
0
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
M40 M20 M10 M8 M4 M2 M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Minutes
(default)
-
1
2
0
Hours
-
-
H20 or P,/A
H10
H8
H4
H2
H1
(default)
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction.
Days of the week Counter
Addr. Description
D7
D6
D5
D4
D3
D2
D1
D0
Days of the week
3
-
-
-
-
-
W4
W2
W1
(default)
0
0
0
0
0
Undefined Undefined Undefined
“-“ indicates write-protected bits. A zero is always read from these bits.
The day counter is a divide-by-7 counter that counts from 00 to 01 and up 06 before starting again from 01.
The correspondence between days and count values is shown below.
Days
W4
0
0
0
0
1
1
1
1
W2
0
0
1
1
0
0
1
1
W1
0
1
0
1
0
1
0
1
Day
Sunday
Remark
00 h
01 h
02 h
03 h
04 h
05 h
06 h
Monday
Tuesday
Wednesday
Thursday
Friday
Write / Read
Write prohibit
Saturday
-
Do not enter a setting for this bit.
12-07-0001
PT0150-8 07/04/12
11
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Calendar Counter
The data format is BCD format.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
4
Description
D7
D6
D5
D4
D3
D8
D2
D4
D1
D2
D0
D1
Days
-
-
D20
D10
(default)
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
Months
-
-
-
M10
Undefined Undefined Undefined Undefined Undefined
Y10 Y8 Y4 Y2 Y1
M8
M4
M2
M1
5
6
(default)
0
0
0
Years
Y80
Y40
Y20
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction.
Time Trimming Register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Time trimming
(default)
/XSL
0
F6
0
F5
0
F4
0
F3
0
F2
0
F1
0
F0
0
7
Note: Time trimming function only adjusts clock timing. Oscillation frequency and 32-kHz clock output is not adjusted.
/XSL bit
The /XSL bit is used to select frequency of the crystal.
/XSL
Frequency of the crystal (kHz)
0
1
32.768
32.000
F6 to F0
Implement a higher-precision clock function. See section “Clock Precision Adjustment Function”.
12-07-0001
PT0150-8 07/04/12
12
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Alarm Register
See section “Alarm Function” for more details.
Alarm_A, Alarm_B Register
Alarm_A, Alarm_B can output alarm pulses at the time set as the day-of-the-week, hour, minute (e.g. Monday 7:00 a.m. every
day of weeks).
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
Alarm_A: Minute
(default)
-
AM40
AM20
AM10
AM8
AM4
AM2
AM1
8
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
AH20, or
Alarm_A: Hour
(default)
-
-
AH10
AH8
AH4
AH2
AH1
AP,/A
Undefined Undefined Undefined Undefined Undefined Undefined
AW5 AW4 AW3 AW2 AW1 AW0
9
0
0
Alarm_A: Day
(default)
-
AW6
A
B
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
BM40 BM20 BM10 BM8 BM4 BM2 BM1
Alarm_B: Minute
(default)
-
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
BH20, or
Alarm_B: Hour
(default)
-
-
BH10
BH8
BH4
BH2
BH1
BP,/A
Undefined Undefined Undefined Undefined Undefined Undefined
BW5 BW4 BW3 BW2 BW1 BW0
C
D
0
0
Alarm_B: Day
(default)
-
BW6
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
12-07-0001
PT0150-8 07/04/12
13
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Clock Precision Adjustment Function
Adjustment range
Adjustment range (ppm)
Adjustment unit (ppm)
Internal timing of adjustment
3.05 *
-189.1 to +189.1
Once every 20 seconds at “00”, “20”, “40” seconds
* note: add or decrement 2 clock pulses every 20s: 2/(32,76820) = 3.051ppm (or 3.125ppm when 32.000kHz crystal is used).
Adjustment amount and adjustment value
Adjustment data
bit 6
F6
0
0
0
bit 5
F5
1
1
1
bit 4
F4
1
1
1
bit 3
F3
1
1
1
bit 2
F2
1
1
1
bit 1
F1
1
1
0
bit 0
F0
1
0
1
Adjustment amount
(ppm)
Decimal
Hexadecimal
3F h
-189.10
-186.05
-183.00
+63
+62
+61
3E h
3D h
-9.15
-6.10
-3.05
OFF
+4
+3
+2
+1
0
-1
-2
-3
04 h
03 h
02 h
01 h
00 h
7F h
7E h
7D h
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
OFF
+3.05
+6.10
+9.15
+183.00
+186.05
+189.10
OFF
-60
-61
-62
-63
-64
44 h
43 h
42 h
41 h
40 h
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
OFF
Examples:
(1) Setting time forward
Adjust (advance) the clock precision when FOUT clock output is 32767.7 Hz
Determine the current amount of variance
(32767.7 -32768) / 32768 = -9.16 × 10 -6
*[ 32768 ] = Reference values
Calculate the optimum adjustment data (decimal value) relative to the current variance.
Adjustment data = variance / adjustment resolution = -9.16 / 3.05 -3
Calculate the setting adjustment data (hexadecimal)
Setting adjustment data = 128 -3 (80 h – 03h) = 125 (7D h)
(2) Setting time backward
Adjust (set back) the clock precision when FOUT clock output is 32768.3 Hz
Determine the current amount of variance
(32768.3 -32768) / 32768 = +9.16 × 10 -6
Calculate the optimum adjustment data (decimal value) relative to the current variance.
Adjustment data = (variance / adjustment resolution) + 1 = (+9.16 / 3.05) + 1 +4
*Add 1 since reference value is 01h
Calculate the setting adjustment data (hexadecimal)
Setting adjustment data = 04 h
12-07-0001
PT0150-8 07/04/12
14
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Alarm Function
These part no have Alarm A and Alarm B functions which can all output alarm pulses at the preset days of the week, hours and
minutes.
Related register
Addr.
Function
Bit 7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Minutes
M40
M20
M10
M8
M4
M2
M1
H20 or
P, /A
2
3
Hours
-
-
H10
-
H8
-
H4
W4
H2
W2
H1
W1
Days of the week
Alarm_A: Minute
Alarm_A: Hour
Alarm_A: Day
Alarm_B: Minute
Alarm_B: Hour
Alarm_B: Day
Control 1
-
-
AM40
-
-
8
-
AM20
AM10
AH10
AW4
BM10
BH10
BW4
SL1
AM8
AH8
AW3
BM8
BH8
BW3
TEST
CLEN
AM4
AH4
AW2
BM4
BH4
BW2
CT2
AM2
AH2
AW1
BM2
BH2
BW1
CT1
AM1
AH1
AW0
BM1
BH1
BW0
CT0
AH20 or
AP, /A
9
-
A
B
C
D
E
F
-
AW6
BM40
-
AW5
-
BM20
BH20 or
BP, /A
-
-
AALE
-
BW6
BALE
-
BW5
SL2
ADJ or
XSTP
Control 2
/12, 24
CTFG
AAFG
BAFG
AALE, BALE:
This bit is used to set up the Alarm A/B function (to generate alarms matching day, hour, or minute settings).
AALE, BALE
Read / Write
Data
Description
Alarm_A (Alarm_B) correspondence action invalid
Alarm_A (Alarm_B) correspondence action valid
0
1
Default
* When using the Alarm A (or B) function, first set this AALE (or BALE) bit value as "0" to stop the function. Next, set the day,
hour, minute, and set the AAFG (or BAFG) bit to 0. Finally, set "1" to the AALE (or BALE) bit to set the Alarm A (or B) function
as valid. The reason for first setting the AALE (or BALE) bit value as "0" is to prevent /INTB or /INTA = "L" output in the event
that a match between the current time and alarm setting occurs while the alarm setting is still being made.
12-07-0001
PT0150-8 07/04/12
15
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AAFG, BAFG:
These bits are valid only when the AALE, BALE bits value are "1". When a match occurs between the Alarm A or Alarm B
setting and the current time, the AAFG or BAFG bit value becomes "1" approximately 61 µs afterward. (There is no effect when
the AALE or BALE bit becomes "0".) The /INTB or /INTA = "L" status that is set at this time can be set to OFF by writing a "0"
to these bits.
AAFG,BAFG Data
Description
0
Alarm register does not match current time
Alarm register match current time
Default
Default
Read
1
0
/INTA or /INTB pin = OFF (H)
Setting prohibited
Write
1
SL2, SL1:
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
0
SL1
0
Description
Default
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
0
1
1
0
1
1
/12, 24:
This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12/24
Description
Time
24-hour clock
12-hour clock
12 ( AM 12)
01 ( AM 01 )
02 ( AM 02 )
03 ( AM 03 )
04 ( AM 04 )
05 ( AM 05 )
06 ( AM 06 )
07 ( AM 07 )
08 ( AM 08 )
09 ( AM 09 )
10 ( AM 10 )
11 ( AM 11 )
24-hour clock
12-hour clock
32 ( PM 12 )
21 ( PM 01 )
22 ( PM 02 )
23 ( PM 03 )
24 ( PM 04 )
25 ( PM 05 )
26 ( PM 06 )
27 ( PM 07 )
28 ( PM 08 )
29 ( PM 09 )
30 ( PM 10 )
31 ( PM 11 )
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
12-hour time display
1
24-hour time display
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
12-07-0001
PT0150-8 07/04/12
16
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Examples:
Alarm_A/B: Day-of-the-week
Alarm_A/B: Hour
24-hour 12-hour
(Hexadecimal) (Hexadecimal)
Alarm_A/B: Minute
Alarm time settings
Minute
Sun. Mon. Tue. Wed. Thu. Fri. Sat.
AW0 AW1 AW2 AW3 AW4 AW5 AW6
(Hexadecimal)
AM 00:00 every day
AM 01:30 every day
AM 11:59 on Mon.
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
00
01
11
12
13
23
00
01
11
32
21
31
00
30
59
00
30
59
PM 00:00 on Mon. to Fri.
PM 01:30 on Sun.
PM 11:59 on Mon, Wed.
WAFG, DAFG and /INTA, /INTB output
61us (approx)
61us (approx)
AAFG (BAFG) bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Set AAFG (BAFG)
to 0
Set AAFG (BAFG)
to 0
Matched alarm time
Matched alarm time
Matched alarm time
12-07-0001
PT0150-8 07/04/12
17
PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Periodic Interrupt Function
Periodic interrupt output can be obtained via PT7C4372A/C: /INTA or /INTB pin. Select among five periodic-cycle settings: 2 Hz
(once per 0.5 seconds), 1 Hz (once per second), 1/60 Hz (once per minute), 1/3600 Hz (once per hour), or monthly (on the 1 st of
each month).
Select between two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform (every
second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts.
A polling function is also provided to enable monitoring of pin states via registers.
Related registers
Period interrupts output via PT7C4372A/C: /INTA, /INTB
Addr.
Function
Bit 7
Bit 6
Bit 5
Bit 4
SL1
Bit 3
Bit 2
CT2
Bit 1
CT1
Bit 0
CT0
E
Control 1
AALE
BALE
SL2
TEST
ADJ or
XSTP
F
Control 2
-
-
/12, 24
/CLEN
AAFG
BAFG
CTFG
SL2, SL1
Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may
be output to the /INTA or /INTB pins selectively by SL1 and SL2.
SL2
0
SL1
0
Description
Default
Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB.
Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB.
Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB.
Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB.
0
1
1
0
1
1
CTFG:
During a read operation, this bit indicates the /INTA or /INTB pin's periodic interrupt output status. This status can be set as OFF
by writing a "0" to this bit when /INTA or /INTB = "H".
CTFG
Data
Description
Default
Default
0
Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read
Read
1
0
1
Periodic interrupt output ON status; /INTA or /INTB= "L"
A "0" can be written only when the periodic interrupt is in level mode, at which time the
/INTA or /INTB pin is set to OFF (“H”) status. After a "0" is written, the value still becomes
"1" again at the next cycle.
Write
Setting prohibited
12-07-0001
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0:
Periodic interrupt output select bits.
Description
Cycle / Falling Timing
CT2
CT1
CT0
Wave Form Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
Off (“H”)
Default
-
Fixed at “L”
2Hz (duty 50%)
1Hz (duty 50%)
Pulse
Pulse
Level
Level
Level
Level
Every second (synchronized with second count up)
Every minute (Occurs when seconds reach ":00")
Every hour (Occurs when minutes and seconds reach "00:00")
Every month (Occurs at 00:00:00 on first day of month)
Mode-specific output waveforms
1) Pulse mode:
Output 2Hz, 1Hz clock pulse.
CTFG bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Approx. 92us (32.768kHz crystal is used)
94us (32.000kHz crystal is used)
Counting up of seconds
Since counting up of seconds and the falling edge has a time lag of approx. 92us (at 32.768kHz) (Approx.
94us when 32.000kHz is used), time with apparently approx. one second of delay from time of the real-time
clock may be read when time is read in synchronization with the falling edge of output.
12-07-0001
PT0150-8 07/04/12
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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2) Level mode:
One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge
of interrupt output.
CTFG bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Write 0 to CTFG
Second count-up
Write 0 to CTFG
Second count-up
Second count-up
3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.
Pulse mode: The period during which the output pulse is low can be adjusted backward or forward up to ±3.784ms (±3.875ms
when 32.000kHz crystal is used).
For example, the duty for the 1-Hz setting can be adjusted ±0.3784% (or ±0.3875% when 32.000kHz crystal is
used) from 50%.
Level mode: a one-second period can be adjusted backward or forward up to ±3.784 ms (±3.875ms when 32.000kHz crystal
is used).
Various Detection Function
PT7C4372A/C detection function includes oscillation stop detection as well as reporting of detection results in corresponding bits
of Control 2 register.
The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results.
*Note with caution that detection functions may not operate correctly when power flickers occur.
Related register
Addr.
Function
Bit 7
-
Bit 6
-
Bit 5
Bit 4
ADJ or
XSTP
Bit 3
Bit 2
Bit 1
Bit 0
F
Control 2
/12, 24
/CLEN
AAFG
BAFG
CTFG
Oscillation stop detection
When read control register is 2 bit 4, this bit is as XSTP bit sensing oscillator halt. This bit is as 30 second adjust bit when write.
XSTP
Data
Description
0
1
Ordinary oscillation.
Read
Default
Oscillator halts sensing.
This bit senses the oscillator halt. When oscillation is halted after initial power on from 0V or drop in supply voltage, the bit is set
to “1” and remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after
power on or supply voltage drop. When this bit is set to “1”, the Time Trimming register, Control 1 register, /CLEN and TEST
bits are reset to “0”. /INTA will stop output and the /INTB will output 32-kHz clock pulses. This bit is set to “0” by setting the
control register 2 during ordinary oscillation.
12-07-0001
PT0150-8 07/04/12
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Reading / Writing Data via the I2C Bus Interface
Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the Vcc line via a pull-up resistance. Consequently, SCL and SDA are both held at high level
when the bus is released (when communication is not being performed).
Fig 4. System configuration
Vcc
RP
RP
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When the master is one, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Starting and Stopping I2C Bus Communications
Fig 5. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which
case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Caution points
a) The master device always controls the START, RESTART, and STOP conditions for communications.
b) The master device does not impose any restrictions on the timing by which STOP conditions affect transmissions, so
communications can be forcibly stopped at any time while in progress. (However, this is only when this RTC module is in
receiver mode (data reception mode = SDA released).
c) When communicating with this RTC module, the series of operations from transmitting the START condition to
transmitting the STOP condition should occur within 0.5 seconds. (A RESTART condition may be sent between a START
condition and STOP condition, but even in such cases the series of operations from transmitting the START condition to
transmitting the STOP condition should still occur within 0.5 seconds.)
If this series of operations requires 0.5 to 1.0 seconds or longer, the I2C bus interface will be automatically cleared and set to
standby mode by this RTC module's bus timeout function. Note with caution that both write and read operations are invalid for
communications that occur during or after this auto clearing operation. (When the read operation is invalid, all data that is read has
a value of "1").
Restarting of communications begins with transfer of the START condition again.
d) When communicating with this RTC module, wait at least 1.3 µs between transferring a STOP condition (to stop
communications) and transferring the next START condition (to start the next round of communications). (If any carries occur in
the time data during this communication period, corrections are made during this period.)
Fig 6. Interval between start and st
1.3
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Data Transfers and Acknowledge Responses during I2C-BUS Communication
1) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no
longer than 0.5 seconds and access to the Address Dh (Reserved) register is prohibited.)
The address auto increment function operates during both write and read operations. After address Fh, increment goes to address
0h. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver
(receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
2) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
8
9
2
1
SDA from transmitter
(sending side)
Release SDA
Low active
ACK signal
SDA from receiver
(receiving side)
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
12-07-0001
PT0150-8 07/04/12
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [ 0110 010 ].
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.
Table
Slave address
bit 4
R / W bit
bit 0
Transfer data
bit 7
0
bit 6
1
bit 5
1
bit 3
0
bit 2
1
bit 1
0
Read
65 h
64 h
1 (= Read)
0 (= Write)
0
Write
I2C Bus’s Basic Transfer Format
S
Start indication
P
Stop indication
A
RTC Acknowledge
Sr
Restart indication
A
Master Acknowledge
1) Write via I2C bus
Addr. setting
0 h ~ F h
bit
bit bit bit bit bit bit bit
Slave address (7 bits)
Transfer mode
S
A
A
A
P
write
0
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
0
0
0
Start
Stop
A
C
K
A
C
K
A
C
K
Slave address + write specification
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=0h fixed)
Write data
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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2) Read via I2C bus
a) Standard read
Addr. setting
0 h ~ F h
Slave address (7 bits)
Transfer mode
S
A
A
write
0
0
1
1
0
0
1
0
0
0
0
0
Start
A
C
K
A
C
K
Slave address + write specification
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=0h fixed)
bit bit bit bit bit bit bit bit
bit bit bit bit bit bit bit bit
Slave address (7 bits)
Sr
A
A
/A
P
Read
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Restart
A
C
K
A
C
K
Stop
N
O
Slave address + read specification
indicating next byte will be read.
Data read (1)
Data is read from the specified start
address and address auto increment.
Data read (2)
Address auto increment to set the
address for the next data to be read.
A
C
K
b) Simplified read
Addr. setting
0 h ~ F h
Slave address (7 bits)
Transfer mode
S
A
A
write
0
0
1
1
0
0
1
0
0
1
0
0
Start
A
C
K
A
C
K
Slave address + write specification
Address + transfer mode specification
1) Specifies the write start address;
2) Specifies the write mode (=4h fixed)
bit bit bit bit bit bit bit bit
bit bit bit bit bit bit bit bit
A
/A
P
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
C
K
Stop
N
O
Data read (1)
Data is read from the specified start
address and address auto increment.
Data read (2)
Address auto increment to set the
address for the next data to be read.
A
C
K
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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c) Simplified read with no start address indicating
Only when reading from address Fh (Fh 0h 1h 2h, etc.), a read operation can be performed without specifying the
read start address or the transfer mode.
bit bit bit bit bit bit bit bit
bit bit bit bit bit bit bit bit
Slave address (7 bits)
S
A
A
/A
P
Read
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Start
A
C
K
A
C
K
Stop
N
O
Slave address + read specification
indicating next byte will be read.
Data read (1)
Data is read from the specified start
address and address auto increment.
Data read (2)
Address auto increment to set the
address for the next data to be read.
A
C
K
Note: The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications. (However, the transfer time must be no longer than 0.5 seconds.)
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Real-time Clock Module (I2C Bus)
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Configuration of Oscillating Circuit and Timing Trimming
Recommended Layout for Crystal
OSCIN
OSCOUT
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Considerations in Mounting Components Surrounding Oscillating Circuit
1) Mount the crystal oscillators in the closest possible position to the IC.
2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with “←A→” in the
above figure).
3) Apply the highest possible insulation resistance between the OSCOUT pin and the PCB.
4) Avoid using any long parallel line to wire the OSCIN and OSCOUT pin.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
CG
Typ
20
5
Unit
pF
pF
pF
pF
OSCIN to GND
OSCOUT to GND
OSCIN to GND
OSCOUT to GND
Build-in capacitors
CD
C1
C2
4
18
Recommended External capacitors
for crystal CL=12.5pF
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768kHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Symbol
fO
ESR
CL
Min
Typ
32.768
-
Max
Unit
kHz
k
Nominal Frequency
Series Resistance
Load Capacitance
-
-
-
-
70
-
12.5
pF
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Measurement of Oscillation Frequency
PT7C4372A
*1. Clock pulse of 32.768kHz or 32.000kHz is
output from the /INTB output pin on powering on
(XSTP is set to 1).
*2. Use a frequency counter having at least 6 digits
(7 digits or more recommended).
*3. Pull-up the /INTB output pin to Vcc for the
4372A.
/INTB
*4. /INTB applies to the 4372A
GND
Oscillation Frequency Adjustment please refers to page 12, Clock Precision Adjustment Function.
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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Mechanical Information
LE (8-pin TSSOP)
PKG. DIMENSIONS(MM)
SYMBOL
MIN
MAX
1.20
0.15
1.00
0.30
0.20
3.10
A
A1
A2
b
0.02
0.80
0.19
0.09
2.90
Note:
1) Controlling dimensions in millimeters.
c
D
E
E1
e
4.30
6.25
4.50
6.55
0.65 BSC
L
θ
0.50
1°
0.70
7°
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PT7C4372A/4372C
Real-time Clock Module (I2C Bus)
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WE (8-pin SOIC)
Dimensions In Millimeters
Symbol
Min
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
Max
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
A
A1
A2
b
Note:
c
D
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012E/AA
E
E1
e
L
θ
1.27 BSC
0.400
0°
1.270
8°
Ordering Information
Part Number
PT7C4372ALE
PT7C4372CLE
PT7C4372AWE
PT7C4372CWE
Package Code
Package
L
L
Lead free and Green 8-Pin TSSOP
Lead free and Green 8-Pin TSSOP
Lead free and Green 8-Pin SOIC
Lead free and Green 8-Pin SOIC
W
W
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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