PT7C4501 [ETC]
Frequency Multiplier? ; 倍频器？\n
| 型号： | PT7C4501 |
| 厂家： | 
ETC |
| 描述： | Frequency Multiplier?
|
| 文件： | 总7页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
PT7C4501/4501A Frequency Multiplier
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Features
electronic systems, clock multiplier and frequency
translation.
• Low cost frequency multiplier
• Zero ppm multiplication error
Using Phase-Locked-Loop (PLL) techniques, the
device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to
180 MHz.
• Input crystal frequency of 5 - 30 MHz
• Input clock frequency of 4 - 50 MHz
• Output clock frequencies up to 180 MHz
• Cycle to cycle jitter less than 150ps (70~180MHz)
• Duty cycle of 45/55 up to 180 MHz
• 9 selectable frequencies controlled by S0, S1 pins
• Operating voltages of 3.0 to 5.5V
The complex Logic divider is the ability to generate
nine different popular multiplication factors, allowing
one chip to output many common frequencies.
• Tri-state output for board level testing
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken low.
This product is intended for clock generation and
frequency translation with low output jitter (variation
in the output period)
General
The PT7C4501/4501A is a high performance frequency
multiplier, which integrates Analog Phase Lock Loop
techniques.
Ordering Information
The PT7C4501/4501A is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most
Part Number
PT7C4501W
PT7C4501AW
Package
8 - Pin SOIC
8 - Pin SOIC
Block Diagram
OE
S0
S1
PLL Clock Synthesis
and
Output
Buffer
CLK
Control Circuit
X1/ICLK
X2
Crystal
Oscillator
VCC
GND
PT0139(12/03)
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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Pin Assignment
PT7C4501/4501A
1
8
X1/ICLK X2
2
3
7
6
VDD
GND
OE
S0
4
5
S1
CLK
SOIC-8 package
Pin Description
Pin
1
Name
X1/ICLK
Vcc
Type
XI
P
Description
Crystal connection or clock input.
Connect to +3.3V or +5V.
Connect to ground.
2
3
GND
S1
P
4
TI
O
Multiplier select pin 1. Connect to GND or Vcc or float (no connection).
Clock output per Table below.
5
CLK
S0
6
TI
I
Multiplier select pin 0. Connect to GND or Vcc or float (no connection).
Output Enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
7
OE
8
X2
XO
Note: XI/XO = crystal connections, TI = tri-level input, O = output, P = power supply connection
Clock Output Table
S1
0
0
S0
CLK
´ 4 1)
´ (16/3)
´ 5
´ 2.5
´ 2
0
M
2)
0
1
0
M
1
M
M
M
1
´ (10/3)
´ 6
0
1
1
M
1
´ 3
´ 8
1)
2)
Note: CLK output frequency = ICLK ´ 4.
Note: M = leave unconnected (self-biases to Vcc/2).
PT0139(12/03)
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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Common Output Frequencies Example (MHz)
Telecom Application
Output
Input
Selection(S1,S0)
16.384 32.768
8.192 16.384
30
10
1,M
38.88
19.44
M,M
51.2
25.6
M,M
37.5
15
M,0
32.768
8.192
0,0
52
13
0,0
60
10
1,0
M,M
M,M
Output
Input
Selection(S1,S0)
77.76
19.44
0,0
72
12
1,0
75
25
1,M
51.84
6.48
1,1
90
15
1,0
100
20
0,1
155.52
19.44
1,1
125
25
0,1
180
30
1,0
Output
Input
Selection(S1,S0)
20
10
M,M
24
12
M,M
30
10
1,M
32
16
M,M
33.33
16.66
M,M
37.5
15
M,0
40
10
0,0
48
12
0,0
60
10
1,0
Output
Input
64
16
72
12
75
25
80
10
90
15
100
20
120
15
125
25
150
25
Selection(S1,S0)
0,0
1,0
1,M
1,1
1,0
0,1
1,1
0,1
1,0
Note: All of the above outputs are achieved by using a common, inexpensive 10MHz to 30MHz crystal.
Consult PTI on how to achieve other output frequencies.
PT0139(12/03)
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Storage temperature ................................................................. -65 to 150OC
Ambient Operating Temperature ..................................................0 to 70OC
Supply Voltage to Ground Potential (VCC) ............................. -0.3 to +7.0V
Inputs (Referenced to GND) ............................................ -0.5 to Vcc+0.5V
Clock Output (Referenced to GND) ................................ -0.5 to Vcc+0.5V
Soldering Temperature (Max of 10 seconds) ................................... 260OC
Recommended Operation Conditions
Sym.
Description
Test condition
Min
Typ
Max
Unit
V
VCC
Supply Voltage
3
2
5.5
V
IH
H-Level Input Voltage
L-Level Input Voltage
Operating Temperature
V
V
IL
0.8
70
V
°
C
TA
0
DC Electrical Characteristics (Vcc = 3.3V unless otherwise noted)
Sym.
Vcc
Icc
Parameter
Supply Voltage
Test Condition
Pin
Vcc
Min.
Typ.
Max.
Unit
V
3
5.5
20
Supply Current
no load, 20MHz crystal
Vcc
12
mA
V
ICLK
OE
(Vcc/2)+1
2
Vcc/2
V
IH
Input Logic High
V
ICLK
OE
Vcc/2
Vcc/2
(Vcc/2)-1
0.8
V
V
Input Logic Low
IL
V
V
IH
Input Logic High
S0, S1
S0, S1
S0, S1
CLK
CLK
Vcc-0.5
2.4
V
V
IM
Input mid-level
V
V
IL
Input Logic Low
0.5
0.4
V
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = -12mA
IOL = 12mA
V
V
PT0139(12/03)
Ver:0
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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AC Electrical Characteristics (Vcc = 3.3V unless otherwise noted)
Part
No.
Sym.
Parameter
Test Condition
Pin
Min. Typ. Max.
Unit
fIN
Input Frequency
crystal
ICLK
5
30
MHz
VCC: 3.0 to 5.5V
VCC: 3.0 to 5.5V
0.8 to 2.0V
4501
CLK
CLK
CLK
CLK
20
20
180
150
fOUT Output frequency
MHz
4501A
tr
tf
Output clock rise time
Output clock fall time
1
1
ns
ns
2.0 to 0.8V
At
VCC
/2
VCC: 3V, up to 120MHz
VCC: 5V, up to 150MHz
Output clock duty cycle
PLL bandwidth*
Duty
CLK
45
10
50
55
%
kHz
ns
Output enable time
Output disable time
Period Jitter
OE high to output on
OE low to tri-state
15
15
50
50
50
ns
70MHz~200MHz, 25C
CLK
CLK
100
200
ps
Jitter over 200ns interval 100MH~200MHz, 25C
ps
* Note: only reference for design.
PT0139(12/03)
Ver:0
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC pub. no. 95.)
8 Pin SOIC
Inches
Millimeters
Symbol
Min
Max
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.24
0.51
0.24
5.00
4.00
A
A1
B
C
D
E
0.0532
0.0040
0.0130
0.0075
0.1890
0.1497
0.0688
0.0098
0.0200
0.0098
0.1968
0.1574
E
0.50BSC
1.27BSC
H
H
L
0.2284
0.0099
0.0160
0.2440
0.0195
0.0500
5.80
0.25
0.41
6.20
0.50
1.27
PT0139(12/03)
Ver:0
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Data Sheet
PT7C4501/4501A Frequency Multiplier
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Notes
Pericom Technology Inc.
Email: support@pti.com.cn
Web Site: www.pti.com.cn, www.pti-ic.com
China:
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China
Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181
Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong
Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.:
2380 Bering Drive, San Jose, California 95131, USA
Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to
improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry
described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
PT0139(12/03)
Ver:0
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