PT7C4502DE [PERICOM]
PLL Clock Multiplier;
| 型号： | PT7C4502DE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Clock Multiplier 时钟 外围集成电路 晶体 |
| 文件： | 总6页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PT7C4502
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PLL Clock Multiplier
Features
Description
The PT7C4502 is a high performance frequency
Low cost frequency multiplier
multiplier, which integrates Analog Phase Lock Loop
techniques.
Zero ppm multiplication error
Input crystal frequency of 5 - 30 MHz
Input clock frequency of 4 - 50 MHz
Output clock frequencies up to 180 MHz
Period jitter 50ps (100~180MHz)
Duty cycle of 45/55% up to 160MHz
Operating voltages of 3.0 to 5.5V
Tri-state output for board level testing
Die form, Wafer form
The PT7C4502 is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multiplier and frequency translation.
Using Phase-Locked-Loop (PLL) techniques, the
device uses a standard fundamental mode, inexpensive
crystal to produce output clocks up to 180 MHz.
The complex Logic divider is the ability to
generate nine different popular multiplication factors,
allowing one chip to output many common frequencies.
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken low.
This product is intended for clock generation and
frequency translation with low output jitter (variation in
the output period)
Applications
Used for crystal oscillator
Block Diagram
S0
S1
PLL Clock Synthesis
and
Output
CLK
Buffer
Control Circuit
X1/ICLK
X2
Crystal
Oscillator
VCC
GND
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PT7C4502
PLL Clock Multiplier
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Pin/Pad Configuration
1520um
OE
AVDD DVDD
X1 -ICLK
X2
Part No.
S1
DGND
CLK S0
AGND
Pin/Pad Description
Pin Name
Pad Name
Type
Description
X1/ICLK
X1-ICLK
I
O
I
Crystal connection or clock input.
X2
S0
Crystal connection. Leave unconnected for clock input.
Multiplier select pin 0. Connect to Vcc or float.
S1
I
Multiplier select pin 1. Connect to GND or float. Internal pull-up.
OE
CLK
I
Output Enable. Tri-states CLK output when low.
Clock output.
Analog Power.
Digital power.
Analog Ground
O
P
P
P
AVDD
DVDD
AGND
VCC
GND
DGND
P
Digital ground.
Pad Coordinate File
Pad Name
X Coordinate
Y Coordinate
Pad Name
X Coordinate
Y Coordinate
X1-ICLK
X2
S1
AGND
DGND
120.90
120.90
117.70
111.50
698.40
892.90
641.50
401.10
225.80
118.60
CLK
S0
DVDD
AVDD
OE
1098.90
1322.10
1303.50
1063.10
470.70
118.60
118.60
973.30
973.30
981.70
Note: Substrate is connected to GND.
Die Size: 1670m*1180m (Including scribe line size 150m*80m.)
Die Thickness: PT7C4502DE: 35025m without coating; PT7C4502-2WF: 22020m with coating
Pad Size: 75m*75m
S1
0
S0
M Note 2
1
CLK
×2 Note 1
×3
0
1 Note 3
M Note 2
×4 (default)
×5
1 Note 3
1
Note 1: CLK output frequency=ICLK×2;
2. M=Leave unconnected (self-biases to Vcc/2);
3. Internal pull-up on S1, unconnected = 1
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PT0140-6
09/23/14
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PT7C4502
PLL Clock Multiplier
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External Components
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground. The value (in pF) of these crystal
caps should equal CL*2. In this equation, CL= crystal
load capacitance in pF. Example: For a crystal with a 15
pF load capacitance, each crystal capacitor would be
30pF.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
PT7C4502 must be isolated from system power supply
noise to perform optimally. A decoupling capacitor of
0.01μF or 0.1uF must be connected between VCC and
the GND. It must be connected close to the PT7C4502
to minimize lead inductance. No external power supply
filtering is required for the PT7C4502.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the
CLK pin for trace lengths over one inch.
Crystal Load Capacitors
There is no on-chip capacitance build-in chip. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
Maximum Ratings
Note:
o
o
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
StorageTemperature...................................................................................-65 Cto+150 C
SupplyVoltagetoGroundPotential(VCC).................................................-0.3Vto+7.0V
Inputs(Reference to GND) ............................................. -0.5Vto Vcc +0.5V
Clock Output (Reference to GND).........................-0.5Vto Vcc +0.5V
Soldering Temperature (Max of 10 seconds) ..............................260OC
Recommended operation conditions
Symbol
Description
Operation Temperature
Supply voltage
Min
-40
Type
Max
+85
5.5
Unit
TA
-
C
VDD
3.0
-
V
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PT0140-6
09/23/14
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PT7C4502
PLL Clock Multiplier
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DC Electrical Characteristics
(VCC = 3.3V± 0.3V, TA = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Supply Voltage
Test Condition
Pin
Min.
Typ.
Max.
Unit
Vcc
-
Vcc
3
3.3
3.6
V
no load, 20MHz crystal,
OE = Vcc
Icc
Supply Current
Vcc
-
12
20
mA
VIH
VIL
VIH
VIM
VIL
VOH
VOL
IS
Input Logic High
-
ICLK, OE
ICLK, OE
S0, S1
S0, S1
S0, S1
CLK
2
-
-
0.8
-
V
V
Input Logic Low
-
-
-
Input Logic High
-
Vcc-0.5
-
V
Input mid-level
-
-
-
Vcc/2
-
V
Input Logic Low
-
-
-
0.5
-
V
High-level output voltage
Low-level output voltage
Short Circuit Current
IOH = -12mA
2.4
-
V
IOL = 12mA
CLK
-
0.4
-
V
-
-
-
CLK
-
mA
A
A
30
OE
-
1
II
Input Leakage Current
S1
-
-7.5
-20
(VCC = 5.0V± 0.5V, TA = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Supply Voltage
Test Condition
Pin
Min.
Typ.
Max.
Unit
Vcc
-
Vcc
4.5
5.0
5.5
V
no load, 20MHz crystal,
OE = Vcc
Icc
Supply Current
Vcc
-
20
30
mA
VIH
VIL
VIH
VIM
VIL
VOH
VOL
IS
Input Logic High
-
ICLK, OE 0.65Vcc
-
-
0.8
-
V
V
Input Logic Low
-
ICLK, OE
S0, S1
S0, S1
S0, S1
CLK
-
-
Input Logic High
-
Vcc-0.4
-
V
Input mid-level
-
-
Vcc/2
-
V
Input Logic Low
-
-
-
-
0.4
-
V
High-level output voltage
Low-level output voltage
Short Circuit Current
IOH = -12mA
Vcc-0.5
V
IOL = 12mA
CLK
-
-
-
-
-
0.4
-
V
-
-
-
CLK
mA
A
A
70
OE
1
II
Input Leakage Current
S1
-7.5
-20
2014-09-0002
PT0140-6
09/23/14
4
PT7C4502
PLL Clock Multiplier
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AC Electrical Characteristics
(VCC = 3.3V± 0.3V, TA = -40 ~ 85ºC, unless otherwise noted)
Sym.
fIN
Parameter
Input Frequency
Test Condition
Crystal
Pin
ICLK
CLK
CLK
CLK
Min.
Typ.
Max.
Unit
MHz
MHz
ns
5
20
-
-
-
30
180
-
fOUT
tr
Output frequency
Vcc: 3.0 to 3.6V
Output clock rise time
Output clock fall time
0.8 to 2.0V, 15pF load
2.0 to 0.8V, 15pF load
1
1
tf
-
-
ns
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
CLK
CLK
45
40
50
55
60
%
%
Duty
Output clock duty cycle
PLL bandwidth
Output enable time
Output disable time
Period Jitter
-
-
10
-
-
-
-
kHz
ns
OE high to output on
OE low to tri-state
100MHz~180MHz
-
-
50
-
-
50
ns
CLK
-
50
100
ps
(VCC = 5.0V± 0.5V, TA = -40 ~ 85ºC, unless otherwise noted)
Sym.
fIN
Parameter
Input Frequency
Test Condition
Crystal
Pin
ICLK
CLK
Min.
5
Typ.
Max.
30
Unit
MHz
MHz
-
-
fOUT
Output frequency
Vcc: 4.5 to 5.5V
20
180
20%Vcc to 80%Vcc,
15pF load
20%Vcc to 80%Vcc,
15pF load
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
tr
tf
Output clock rise time
CLK
CLK
CLK
CLK
-
1.2
1.2
50
-
ns
ns
%
%
Output clock fall time
Output clock duty cycle
-
-
45
40
55
60
Duty
PLL bandwidth
Output enable time
Output disable time
Period Jitter
-
-
10
-
-
-
-
kHz
ns
OE high to output on
OE low to tri-state
100MHz~180MHz
-
-
50
-
-
50
ns
CLK
-
50
100
ps
Test circuits
1>Load circuit for output clock duty cycle, rise and fall time Measurement
33om
From Output
Under Test
15pF
2>Timing Definitions for output clock rise and fall time Measurement
2014-09-0002
PT0140-6
09/23/14
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PT7C4502
PLL Clock Multiplier
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Ordering Information
Package Code
Part Number
PT7C4502DE
PT7C4502-2WF
Package
350±25µm without coating Die form
220±20µm with coating Wafer form
DE
WF
Note:
E = Pb-free and Green
“-2” shows die thickness is 220±20µm with coating; PT7C4502DE die thickness is 350±25µm with coating.
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2014-09-0002
PT0140-6
09/23/14
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