935312743518 [NXP]
RISC Microcontroller;
| 型号： | 935312743518 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总31页 (文件大小：937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number S9KEA128P80M48SF0
Rev 4, 09/2014
Freescale Semiconductor
Data Sheet: Technical Data
S9KEA128P80M48SF0
KEA128 Sub-Family Data
Sheet
Supports the following:
S9KEAZ64AMLK(R),
S9KEAZ128AMLK(R),
S9KEAZ64AVLK(R),
S9KEAZ128AVLK(R),
S9KEAZ64ACLK(R),
S9KEAZ128ACLK(R),
S9KEAZ64AMLH(R),
S9KEAZ128AMLH(R),
S9KEAZ64AVLH(R),
S9KEAZ128AVLH(R),
S9KEAZ64ACLH(R) and
S9KEAZ128ACLH(R)
Key features
• System peripherals
– Power management module (PMC) with three power
modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or interrupt,
selectable trip points
– Watchdog with independent clock source (WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Aliased SRAM bitband region (BIT-BAND)
– Bit manipulation engine (BME)
• Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 125°C
• Performance
– Up to 48 MHz ARM® Cortex-M0+ core
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 128 KB flash
• Security and integrity modules
– Up to 16 KB RAM
– 80-bit unique identification (ID) number per chip
• Clocks
• Human-machine interface
– Oscillator (OSC) - supports 32.768 kHz crystal or 4
MHz to 24 MHz crystal or ceramic resonator; choice
of low power or high gain oscillators
– Up to 71 general-purpose input/output (GPIO)
– Two 32-bit keyboard interrupt modules (KBI)
– External interrupt (IRQ)
– Internal clock source (ICS) - internal FLL with
internal or external reference, 37.5 kHz pre-trimmed
internal reference for 48 MHz system clock
– Internal 1 kHz low-power oscillator (LPO)
• Analog modules
– One up to 16-channel 12-bit SAR ADC, operation in
Stop mode, optional hardware trigger (ADC)
– Two analog comparators containing a 6-bit DAC
and programmable reference input (ACMP)
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2014 Freescale Semiconductor, Inc.
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One pulse width timer (PWT)
– One real-time clock (RTC)
• Communication interfaces
– Two SPI modules (SPI)
– Up to three UART modules (UART)
– Two I2C modules (I2C)
– One MSCAN module (MSCAN)
• Package options
– 80-pin LQFP
– 64-pin LQFP
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts.......................................................................................4
4.2.2 FTM module timing....................................................... 16
4.3 Thermal specifications.................................................................17
4.3.1 Thermal characteristics.................................................. 17
5 Peripheral operating requirements and behaviors................................ 19
5.1 Core modules............................................................................... 19
5.1.1 SWD electricals .............................................................19
5.2 External oscillator (OSC) and ICS characteristics.......................20
5.3 NVM specifications..................................................................... 22
5.4 Analog..........................................................................................23
5.4.1 ADC characteristics....................................................... 23
5.4.2 Analog comparator (ACMP) electricals.........................25
5.5 Communication interfaces........................................................... 26
5.5.1 SPI switching specifications.......................................... 26
5.5.2 MSCAN......................................................................... 29
6 Dimensions...........................................................................................29
6.1 Obtaining package dimensions.................................................... 29
7 Pinout................................................................................................... 30
7.1 Signal multiplexing and pin assignments.................................... 30
8 Revision History...................................................................................30
1.1 Determining valid orderable parts............................................... 4
2 Part identification................................................................................. 4
2.1 Description...................................................................................4
2.2 Format..........................................................................................4
2.3 Fields............................................................................................4
2.4 Example....................................................................................... 5
3 Ratings..................................................................................................5
3.1 Thermal handling ratings.............................................................5
3.2 Moisture handling ratings............................................................ 5
3.3 ESD handling ratings...................................................................6
3.4 Voltage and current operating ratings..........................................6
4 General................................................................................................. 7
4.1 Nonswitching electrical specifications........................................ 7
4.1.1 DC characteristics.......................................................... 7
4.1.2 Supply current characteristics........................................ 13
4.1.3 EMC performance..........................................................15
4.2 Switching specifications.............................................................. 15
4.2.1 Control timing................................................................ 15
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: KEAZ128.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q B KEA A C FFF M T PP N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• S = Automotive qualified
• P = Prequalification
B
KEA
A
Memory type
Kinetis Auto family
Key attribute
• 9 = Flash
• KEA
• Z = M0+ core
• F = M4 W/ DSP & FPU
• C= M4 W/ AP + FPU
C
CAN availability
• N = CAN not available
• (Blank) = CAN available
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
4
Freescale Semiconductor, Inc.
Ratings
Field
FFF
M
Description
Program flash memory size
Maskset revision
Values
• 128 = 128 KB
• A = 1st Fab version
• B = Revision after 1st version
T
Temperature range (°C)
• C = –40 to 85
• V= –40 to 105
• M = –40 to 125
PP
N
Package identifier
Packaging type
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (14 mm x 14 mm)
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
S9KEAZ128AMLK
3 Ratings
3.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
3.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
5
Ratings
3.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
–6000
–500
–100
Max.
+6000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of °C
1
2
3
V
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. The test produced the following results:
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass +100/-100 mA I-test with IDD current limit at 400 mA (VDD collapsed during positive injection).
• I/O pins pass +50/-100 mA I-test with IDD current limit at 1000 mA for VDD
• Supply groups pass 1.5 Vccmax
.
.
• RESET_B pin was only tested with negative I-test due to product conditioning requirement.
3.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in the following table may
affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Table 1. Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
Unit
V
Digital supply voltage
6.0
IDD
Maximum current into VDD
Input voltage except true open drain pins
Input voltage of true open drain pins
120
VDD + 0.31
mA
V
VIN
–0.3
–0.3
–25
6
V
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Maximum rating of VDD also applies to VIN.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
6
Freescale Semiconductor, Inc.
General
4 General
4.1 Nonswitching electrical specifications
4.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 2. DC characteristics
Symbol
—
Descriptions
Operating voltage
Min
2.7
Typical1
Max
5.5
—
Unit
V
—
—
—
—
VOH
Output
high
voltage
All I/O pins, except PTA2
and PTA3, standard-drive
strength
5 V, Iload = –5 mA
3 V, Iload = –2.5 mA
VDD – 0.8
VDD – 0.8
V
—
V
High current drive pins,
high-drive strength2
5 V, Iload = –20 mA
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
V
V
3 V, Iload = –10 mA
IOHT
Output
high
Max total IOH for all ports
5 V
3 V
–100
–60
mA
—
current
VOL
Output All I/O pins, standard-drive
5 V, Iload = 5 mA
3 V, Iload = 2.5 mA
5 V, Iload =20 mA
3 V, Iload = 10 mA
5 V
—
—
—
—
—
—
—
—
—
—
—
—
0.8
0.8
0.8
0.8
100
60
V
V
low
strength
voltage
High current drive pins,
high-drive strength2
V
V
IOLT
Output
low
Max total IOL for all ports
mA
3 V
current
VIH
VIL
Input high
voltage
All digital inputs
All digital inputs
4.5≤VDD<5.5 V
2.7≤VDD<4.5 V
4.5≤VDD<5.5 V
0.65 × VDD
0.70 × VDD
—
—
—
—
—
—
V
V
Input low
voltage
0.35 ×
VDD
2.7≤VDD<4.5 V
—
—
0.06 × VDD
—
—
—
0.30 ×
VDD
Vhys
|IIn|
Input
hysteresis
All digital inputs
—
mV
µA
Input
Per pin (pins in high
VIN = VDD or VSS
0.1
1
leakage
current
impedance input mode)
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
7
Nonswitching electrical specifications
Table 2. DC characteristics (continued)
Symbol
|IINTOT
Descriptions
Min
Typical1
Max
Unit
|
Total
leakage
combined
for all port
pins
Pins in high impedance
input mode
VIN = VDD or VSS
—
—
2
µA
RPU
Pullup
All digital inputs, when
—
30.0
30.0
—
—
50.0
60.0
kΩ
resistors enabled (all I/O pins other
than PTA2 and PTA3)
3
RPU
Pullup
PTA2 and PTA3 pins
—
kΩ
resistors
IIC
DC
Single pin limit
VIN < VSS, VIN > VDD
-2
-5
—
—
2
mA
injection
Total MCU limit, includes
sum of all stressed pins
25
current4,
5, 6
CIn
Input capacitance, all pins
RAM retention voltage
—
—
—
—
—
7
pF
V
VRAM
2.0
—
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true
open drain I/O pins that are internally clamped to VSS
.
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger value.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate
is very low (which would reduce overall power consumption).
Table 3. LVD and POR specification
Symbol
VPOR
Description
Min
1.5
4.2
Typ
1.75
4.3
Max
2.0
Unit
V
POR re-arm voltage1
VLVDH
Falling low-voltage detect
threshold—high range (LVDV =
1)2
4.4
V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
Falling low-
voltage warning
threshold— high
range
Level 1 falling
(LVWV = 00)
4.3
4.5
4.6
4.7
—
4.4
4.5
4.6
4.7
100
4.5
4.6
4.7
4.8
—
V
V
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
V
Level 4 falling
(LVWV = 11)
V
High range low-voltage detect/
warning hysteresis
mV
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
8
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 3. LVD and POR specification (continued)
Symbol
Description
Min
Typ
Max
Unit
VLVDL
Falling low-voltage detect
2.56
2.61
2.66
V
threshold—low range (LVDV = 0)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
VHYSDL
VHYSWL
VBG
Falling low-
voltage warning
threshold—low
range
Level 1 falling
(LVWV = 00)
2.62
2.72
2.82
2.92
—
2.7
2.8
2.9
3.0
40
2.78
2.88
2.98
3.08
—
V
V
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
V
Level 4 falling
(LVWV = 11)
V
Low range low-voltage detect
hysteresis
mV
mV
V
Low range low-voltage warning
hysteresis
Buffered bandgap output 3
—
80
—
1.14
1.16
1.18
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 125 °C
VDD-VOH(V)
IOH(mA)
Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
9
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)
VDD-VOH(V)
IOH(mA)
Figure 3. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 5 V)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
10
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 4. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
11
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 7. Typical VOL Vs. IOL (high drive strength) (VDD = 5 V)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
12
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)
4.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 4. Supply current characteristics
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max
Unit
Temp
Run supply current FEI
mode, all modules clocks
enabled; run from flash
RIDD
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
5
11.1
8
—
—
—
—
—
—
—
—
—
—
—
—
mA
-40 to 125 °C
5
2.4
11
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
3
5
7.9
4.9
2.3
7.8
5.5
3.8
2.3
Run supply current FEI
mode, all modules clocks
disabled and gated; run from
flash
RIDD
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
mA
-40 to 125 °C
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
Table 4. Supply current characteristics (continued)
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max
Unit
Temp
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
3
7.7
5.4
3.7
2.2
14.7
9.8
6
—
—
—
—
Run supply current FBE
mode, all modules clocks
enabled; run from RAM
RIDD
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
5
3
5
3
5
3
—
14.92
mA
-40 to 125 °C
—
2.4
14.6
9.6
5.9
2.3
11.4
7.7
4.7
2.3
11.3
7.6
4.6
2.2
8.4
6.5
4.3
2.4
8.3
6.4
4.2
2.3
2
—
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
12.82
—
—
Run supply current FBE
mode, all modules clocks
disabled and gated; run from
RAM
RIDD
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
12.52
mA
-40 to 125 °C
—
—
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
9.52
—
—
Wait mode current FEI
mode, all modules clocks
enabled
WIDD
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
7.22
mA
-40 to 125 °C
—
—
48/24 MHz
24/24 MHz
12/12 MHz
1/1 MHz
—
7.12
—
—
Stop mode supply current no
clocks active (except 1 kHz
LPO clock)3
SIDD
—
—
5
3
1702
1602
µA
µA
-40 to 125 °C
-40 to 125 °C
—
1.9
ADC adder to Stop
ADLPC = 1
—
5
3
86
82
—
—
-40 to 125 °C
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
ACMP adder to Stop
—
—
5
3
12
12
—
—
µA
-40 to 125 °C
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
14
Freescale Semiconductor, Inc.
Switching specifications
Table 4. Supply current characteristics (continued)
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max
Unit
Temp
LVD adder to Stop4
—
—
5
3
130
125
—
—
µA
-40 to 125 °C
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. The high current is observed at high temperature.
3. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.
4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
4.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must consult
the following Freescale applications notes, available on freescale.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
4.2 Switching specifications
4.2.1 Control timing
Table 5. Control timing
Num
Rating
System and core clock
Bus frequency (tcyc = 1/fBus
Symbol
fSys
Min
DC
Typical1
Max
48
Unit
MHz
MHz
KHz
ns
1
2
3
4
—
—
)
fBus
DC
24
Internal low power oscillator frequency
External reset pulse width2
fLPO
0.67
1.5 ×
tcyc
1.0
—
1.25
—
textrst
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
15
Switching specifications
Num
Table 5. Control timing (continued)
Rating
Symbol
trstdrv
tILIH
Min
34 × tcyc
100
Typical1
—
Max
—
Unit
ns
5
6
Reset low drive
IRQ pulse width
Asynchronous path2
Synchronous path3
Asynchronous path2
Synchronous path
—
—
—
ns
tIHIL
1.5 × tcyc
100
—
—
ns
7
8
Keyboard interrupt pulse
width
tILIH
—
—
ns
tIHIL
1.5 × tcyc
—
—
—
ns
Port rise and fall time -
Normal drive strength (load
= 50 pF)4
tRise
tFall
10.2
9.5
—
ns
—
—
ns
Port rise and fall time - high
drive strength (load = 50
pF)4
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C.
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 10. KBIPx timing
4.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 6. FTM input timing
Function
Symbol
fTimer
Min
fBus
0
Max
fSys
Unit
Hz
Timer clock frequency
External clock
frequency
fTCLK
fTimer/4
Hz
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
16
Freescale Semiconductor, Inc.
Thermal specifications
Table 6. FTM input timing (continued)
Function
Symbol
tTCLK
tclkh
Min
4
Max
—
Unit
tcyc
tcyc
tcyc
tcyc
External clock period
External clock high time
External clock low time
1.5
1.5
1.5
—
tclkl
—
Input capture pulse
width
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 11. Timer external clock
tICPW
FTMCHn
FTMCHn
tICPW
Figure 12. Timer input capture pulse
4.3 Thermal specifications
4.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
17
Thermal specifications
Table 7. Thermal attributes
Board type
Symbol
Description
64 LQFP
80 LQFP
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
71
53
59
46
35
57
°C/W
1, 2
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
RθJA
RθJMA
RθJMA
RθJB
Thermal resistance, junction to
ambient (natural convection)
44
47
38
28
°C/W
°C/W
°C/W
°C/W
1, 3
1, 3
1, 3
4
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Thermal resistance, junction to
board
—
—
RθJC
Thermal resistance, junction to case
20
5
15
3
°C/W
°C/W
5
6
ΨJT
Thermal characterization parameter,
junction to package top outside
center (natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
18
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can
be obtained by solving the above equations iteratively for any value of TA.
5 Peripheral operating requirements and behaviors
5.1 Core modules
5.1.1 SWD electricals
Table 8. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
24
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
3
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
35
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 13. Serial wire clock input timing
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
SWD_CLK
J9
J10
Input data valid
SWD_DIO
J11
Output data valid
SWD_DIO
J12
SWD_DIO
J11
Output data valid
SWD_DIO
Figure 14. Serial wire data timing
5.2 External oscillator (OSC) and ICS characteristics
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient)
Num
Characteristic
Low range (RANGE = 0)
High range (RANGE = 1)
Symbol
Min
31.25
4
Typical1
32.768
—
Max
39.0625
24
Unit
kHz
1
Crystal or
resonator
frequency
flo
fhi
MHz
2
3
Load capacitors
C1, C2
RF
See Note2
—
Feedback
resistor
Low Frequency, Low-Power
Mode3
—
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
MΩ
Low Frequency, High-Gain
Mode
10
1
High Frequency, Low-Power
Mode
High Frequency, High-Gain
Mode
1
4
5
Series resistor -
Low Frequency
Low-Power Mode 3
High-Gain Mode
Low-Power Mode3
RS
RS
—
—
—
0
200
0
—
—
—
kΩ
kΩ
kΩ
Series resistor -
High Frequency
Series resistor -
High Frequency,
High-Gain Mode
4 MHz
8 MHz
—
—
0
0
—
—
kΩ
kΩ
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 9. OSC and ICS specifications (temperature range = -40 to 125 °C ambient) (continued)
Num
Characteristic
16 MHz
Symbol
Min
—
Typical1
Max
—
Unit
kΩ
0
1000
800
3
6
Crystal start-up
time low range =
32.768 kHz
crystal; High
range = 20 MHz
crystal4,5
Low range, low power
Low range, high gain
High range, low power
High range, high gain
tCSTL
—
—
ms
ms
ms
ms
—
—
tCSTH
—
—
—
1.5
—
7
8
Internal reference start-up time
tIRST
fint_t
—
20
—
50
µs
Internal reference clock (IRC) frequency trim
range
31.25
39.0625
kHz
9
Internal
T = 125 °C, VDD = 5 V
fint_ft
—
37.5
—
kHz
reference clock
frequency,
factory trimmed,
10
11
DCO output
frequency range
FLL reference = fint_t, flo, or
fhi/RDIV
fdco
40
—
—
50
MHz
%
Factory trimmed
internal oscillator
accuracy
T = 125 °C, VDD = 5 V
Δfint_ft
-0.8
0.8
12
13
Deviation of IRC Over temperature range from
Δfint_t
-1
—
—
0.8
0.8
%
%
over temperature
when trimmed at
-40 °C to 125°C
T = 25 °C, VDD
5 V
=
Frequency
accuracy of DCO
output using
Over temperature range from
-40 °C to 125°C
Δfdco_ft
-2.3
factory trim value
14
15
FLL acquisition time4,6
tAcquire
CJitter
—
—
—
2
ms
Long term jitter of DCO output clock (averaged
over 2 ms interval)7
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
OSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical crystal or resonator circuit
5.3 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash memories.
Table 10. Flash characteristics
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
Supply voltage for program/erase –40 °C
to 125 °C
Vprog/erase
2.7
—
5.5
V
Supply voltage for read operation
NVM Bus frequency
NVM Operating frequency
Erase Verify All Blocks
Erase Verify Flash Block
Erase Verify Flash Section
Read Once
VRead
fNVMBUS
fNVMOP
tVFYALL
tRD1BLK
tRD1SEC
tRDONCE
tPGM2
2.7
1
—
—
5.5
24
V
MHz
MHz
tcyc
0.8
1
1.05
2605
2579
485
—
—
—
—
tcyc
—
—
tcyc
—
—
464
tcyc
Program Flash (2 word)
Program Flash (4 word)
Program Once
0.12
0.21
0.20
95.42
95.42
19.10
95.42
—
0.13
0.21
0.21
100.18
100.18
20.05
100.19
—
0.31
0.49
0.21
100.30
100.30
20.09
100.31
482
ms
tPGM4
ms
tPGMONCE
tERSALL
tERSBLK
tERSPG
tUNSECU
tVFYKEY
tMLOADU
nFLPE
ms
Erase All Blocks
ms
Erase Flash Block
ms
Erase Flash Sector
ms
Unsecure Flash
ms
Verify Backdoor Access Key
Set User Margin Level
tcyc
—
—
415
tcyc
FLASH Program/erase endurance TL to TH
= -40 °C to 125 °C
10 k
100 k
—
Cycles
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 10. Flash characteristics (continued)
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
15
100
—
years
1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. tcyc = 1 / fNVMBUS
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Flash Memory Module section in the reference manual.
5.4 Analog
5.4.1 ADC characteristics
Table 11. 5 V 12-bit ADC operating conditions
Characteri
stic
Conditions
Symbol
Min
Typ1
Max
Unit
Comment
Reference
potential
• Low
• High
VREFL
VREFH
VDDA
VSSA
VDDA/2
2.7
—
—
—
0
VDDA/2
VDDA
5.5
V
—
Supply
voltage
Absolute
V
mV
V
—
—
—
Delta to VDD (VDD-VDDA
)
ΔVDDA
VADIN
-100
+100
VREFH
Input
VREFL
—
voltage
Input
capacitance
CADIN
RADIN
RAS
—
—
4.5
3
5.5
5
pF
kΩ
kΩ
—
—
Input
resistance
Analog
source
resistance
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
External to
MCU
—
—
—
—
2
5
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
—
—
5
•
•
10
10
8-bit mode
(all valid fADCK
)
ADC
conversion
clock
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
0.4
0.4
—
—
8.0
4.0
MHz
—
frequency
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
SIMPLIFIED
INPUT PIN EQUIVALENT
z ADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
R AS
R ADIN
protection
v ADIN
C AS
v AS
R ADIN
R ADIN
R ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 12. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Characteristic
Supply current
ADLPC = 1
Conditions
Symbol
Min
Typ1
Max
Unit
IDDA
—
133
—
µA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
IDDA
IDDA
IDDA
IDDA
—
—
—
—
218
327
—
—
µA
µA
µA
µA
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
582
990
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset, module off
0.011
1
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
Symbol
Min
Typ1
Max
Unit
ADC asynchronous
clock source
High speed (ADLPC =
0)
fADACK
2
3.3
5
MHz
Low power (ADLPC =
1)
1.25
—
2
20
3.3
—
—
—
—
Conversion time
Short sample
(including sample time) (ADLSMP = 0)
tADC
ADCK cycles
ADCK cycles
Long sample
(ADLSMP = 1)
—
40
Sample time
Short sample
(ADLSMP = 0)
tADS
—
3.5
23.5
Long sample
—
(ADLSMP = 1)
Total unadjusted Error2 12-bit mode
ETUE
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
LSB3
LSB3
LSB3
LSB3
LSB3
10-bit mode
8-bit mode
0.8
Differential Non-
Liniarity
12-bit mode
10-bit mode
8-bit mode
1.5
0.4
0.15
1.5
Integral Non-Linearity 12-bit mode
10-bit mode
0.4
8-bit mode
0.15
1.0
Zero-scale error4
Full-scale error5
12-bit mode
10-bit mode
8-bit mode
12-bit mode
10-bit mode
8-bit mode
≤12 bit modes
all modes
EZS
0.2
0.35
2.5
EFS
0.3
0.25
—
Quantization error
Input leakage error6
Temp sensor slope
EQ
EIL
m
LSB3
mV
IIn x RAS
3.266
3.638
1.396
-40 °C–25 °C
25 °C–125 °C
25 °C
—
—
—
—
—
—
mV/°C
Temp sensor voltage
VTEMP25
V
1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization
3. 1 LSB = (VREFH - VREFL)/2N
4. VADIN = VSSA
5. VADIN = VDDA
6. IIn = leakage current (refer to DC characteristics)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
5.4.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
Characteristic
Supply voltage
Symbol
VDDA
IDDA
Min
2.7
Typical
—
Max
5.5
Unit
V
Supply current (Operation mode)
Analog input voltage
—
10
20
µA
V
VAIN
VSS - 0.3
—
—
VDDA
40
Analog input offset voltage
VAIO
VH
—
mV
mV
Analog comparator hysteresis
(HYST=0)
—
15
20
Analog comparator hysteresis
(HYST=1)
VH
—
20
30
mV
Supply current (Off mode)
Propagation Delay
IDDAOFF
tD
—
—
60
—
1
nA
µs
0.4
5.5 Communication interfaces
5.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 80% VDD, unless noted, and 25 pF load on all SPI pins. All timing assumes slew
rate control is disabled and high-drive strength is enabled for SPI output pins.
Table 14. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
4
5
6
7
8
9
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
2 x tBus
2048 x tBus
ns
tSPSCK
tSPSCK
ns
tBus = 1/fBus
1/2
—
—
—
—
—
—
—
—
1/2
—
tWSPSCK Clock (SPSCK) high or low time
tBus – 30
1024 x tBus
tSU
tHI
tv
Data setup time (inputs)
Data hold time (inputs)
8
8
—
—
25
—
ns
ns
Data valid (after SPSCK edge)
Data hold time (outputs)
—
20
ns
tHO
ns
Table continues on the next page...
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
10
tRI
tFI
Rise time input
Fall time input
Rise time output
Fall time output
—
tBus – 25
ns
—
11
tRO
tFO
—
25
ns
—
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in Control timing.
2
3
4
5
6
7
8
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
4 x tBus
—
—
ns
tBus
tBus
ns
tBus = 1/fBus
1
1
—
—
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
15
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
25
—
ns
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
12
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
28
Freescale Semiconductor, Inc.
Dimensions
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA=1)
5.5.2 MSCAN
Table 16. MSCAN wake-up pulse characteristics
Parameter
Symbol
tWUP
Min
Typ
Max
1.5
-
Unit
µs
MSCAN wakeup dominant pulse filtered
MSCAN wakeup dominant pulse pass
-
-
-
tWUP
5
µs
6 Dimensions
6.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
64-pin LQFP
Then use this document number
98ASS23234W
80-pin LQFP
98ASS23237W
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
Freescale Semiconductor, Inc.
29
Pinout
7 Pinout
7.1 Signal multiplexing and pin assignments
For the pin muxing details see section Signal Multiplexing and Signal Descriptions of
KEA128 Reference Manual.
8 Revision History
The following table provides a revision history for this document.
Table 17. Revision History
Rev. No.
Date
Substantial Changes
Initial Release
Rev. 1
Rev. 2
11 March 2014
18 June 2014
• Parameter Classification section is
removed.
• Classification column is removed
from all the tables in the
document.
• New section added - Supply
current characteristics.
Rev. 3
Rev. 4
18 July 2014
• Added supported part numbers.
• ESD handling ratings section is
updated.
• Figures in DC characteristics
section are updated.
• Specs updated in following tables:
• Table 9.
03 Sept 2014
• Data Sheet type changed to
"Technical Data".
KEA128 Sub-Family Data Sheet, Rev4, 09/2014.
30
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Document Number S9KEA128P80M48SF0
Revision 4, 09/2014
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