SAA7105H [NXP]
Digital video encoder; 数字视频编码器
| 型号： | SAA7105H |
| 厂家： | 
NXP |
| 描述： | Digital video encoder |
| 文件： | 总71页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7104H; SAA7105H
Digital video encoder
Product specification
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
CONTENTS
8
BOUNDARY SCAN TEST
8.1
8.2
Initialization of boundary scan circuit
Device identification codes
1
2
3
4
5
6
7
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
9
LIMITING VALUES
10
11
11.1
12
THERMAL CHARACTERISTICS
CHARACTERISTICS
Teletext timing
PINNING
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
12.1
12.2
12.3
Reconstruction filter
Analog output voltages
Suggestions for a board layout
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Reset conditions
Input formatter
RGB LUT
Cursor insertion
RGB Y-CB-CR matrix
Horizontal scaler
Vertical scaler and anti-flicker filter
FIFO
13
PACKAGE OUTLINE
SOLDERING
14
14.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
14.2
14.3
14.4
14.5
7.9
Border generator
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
RGB processor
Triple DAC
HD data path
Timing generator
Pattern generator for HD sync pulses
I2C-bus interface
Power-down modes
Programming the SAA7104H; SAA7105H
Input levels and formats
Bit allocation map
I2C-bus format
Slave receiver
Suitability of surface mount IC packages for
wave and reflow soldering methods
15
16
17
18
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
Slave transmitter
2004 Mar 04
2
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
1
FEATURES
• Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
• Supports Intel Digital Video Out (DVO) low voltage
interfacing to graphics controller
• 27 MHz crystal-stable subcarrier generation
• Programmable border colour of underscan area
• Programmable 5 line anti-flicker filter
• Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
• On-chip 27 MHz crystal oscillator (3rd-harmonic or
• Programmable assignment of clock edge to bytes (in
fundamental 27 MHz crystal)
double edged mode)
• Fast I2C-bus control port (400 kHz)
• Encoder can be master or slave
• Adjustable output levels for the DACs
• Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well)
• Programmable horizontal and vertical input
synchronization phase
• PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
• Programmable horizontal sync output phase
• Internal Colour Bar Generator (CBG)
• Hot-plug detection through dedicated interrupt pin
• Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280 × 1024 graphics data at
60 or 50 Hz frame rate
• Optional support of various Vertical Blanking Interval
(VBI) data insertion
• Supported VGA resolutions for HDTV output up to
1920 × 1080 interlaced graphics data at 60 or 50 Hz
frame rate
• Macrovision (1) Pay-per-View copy protection system
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this
applies to the SAA7104H only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
• Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at
27 MHz sample rate (signals in parenthesis are
optionally), all at 10-bit resolution
• Non-interlaced CB-Y-CR or RGB input at maximum
4 : 4 : 4 sampling
• Downscaling and upscaling from 50 to 400%
• Optional cross-colour reduction for PAL and NTSC
• Optional interlaced CB-Y-CR input of Digital Versatile
CVBS outputs
Disk (DVD) signals
• Power-save modes
• Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
• Joint Test Action Group (JTAG) boundary scan test
• Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
• QFP64 package.
• 3 × 256 bytes RGB Look-Up Table (LUT)
• Support for hardware cursor
• HDTV up to 1920 × 1080 interlaced and 1280 × 720
progressive, including 3-level sync pulses
(1) Macrovision is a trademark of the Macrovision Corporation.
2004 Mar 04
3
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
2
GENERAL DESCRIPTION
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 1280 × 1024
resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this
port can provide Y, PB and PR signals for HDTV monitors.
The SAA7104H; SAA7105H is an advanced
next-generation video encoder which converts PC
graphics data at maximum 1280 × 1024 resolution
(optionally 1920 × 1080 interlaced) to PAL (50 Hz) or
NTSC (60 Hz) video signals. A programmable scaler and
anti-flicker filter (maximum 5 lines) ensures properly sized
and flicker-free TV display as CVBS or S-video output.
The device includes a sync/clock generator and on-chip
DACs.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
All inputs intended to interface to the host graphics
controller are designed for low-voltage signals between
down to 1.1 V and up to 3.6 V.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
3.15
TYP.
3.3
MAX.
3.45
UNIT
VDDA
analog supply voltage
V
V
VDDD
IDDA
IDDD
Vi
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
3.15
1
3.3
3.45
115
200
110
175
mA
mA
1
TTL compatible
Vo(p-p)
analog CVBS output signal voltage for a 100/100
−
1.23
−
V
colour bar at 75/2 Ω load (peak-to-peak value)
RL
load resistance
−
−
−
0
37.5
−
Ω
ILElf(DAC)
DLElf(DAC)
Tamb
low frequency integral linearity error of DACs
low frequency differential linearity error of DACs
ambient temperature
−
−
−
±3
±1
70
LSB
LSB
°C
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SAA7104H
SAA7105H
QFP64
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
SOT393-1
2004 Mar 04
4
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V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDA1
43
DDA2
DDA3
DDA4
SSA1
SSA2
DDD1
DDD2
DDD3
DDD4
SSD1
SSD2
SSD3
SSD4
57
44
52
53
48
49
6
12
25
58
7
13
26
55
47
46
56
10
9
TRST
DUMP
RSET
TDI
5 to 2,
64 to 61,
21 to 24
LUT
+
CURSOR
FIFO
+
UPSAMPLING
PD11 to
PD0
INPUT
FORMATTER
RGB TO Y-C -C
B
R
MATRIX
TDO
TMS
TCK
DECIMATOR
4 : 4 : 4 to
4 : 2 : 2
HORIZONTAL
SCALER
VERTICAL
SCALER
VERTICAL
FILTER
11
20
19
36
38
PIXCLKI
PIXCLKI
LLC
45
42
41
BLUE_CB_CVBS
BORDER
GENERATOR
VIDEO
ENCODER
TRIPLE
DAC
FIFO
GREEN_VBS_CVBS
RED_CR_C_CVBS
35
HD
OUTPUT
OUT_EN
SAA7104H
SAA7105H
SRES
39
40
54
VSM
27
2
PIXEL CLOCK
SYNTHESIZER
CRYSTAL
OSCILLATOR
TIMING
GENERATOR
HSM_CSYNC
TVD
I C-BUS
PIXCLKO
CONTROL
1, 16, 30 to 34
37
51
50
XTALO
60
17 18 28 29
59
15
14
8
mhc683
XTALI
n.c.
RTCI
FSVGC CBO
VSVGC HSVGC
TTXRQ_XCLKO2 SDA
SCL RESET
27 MHz
TTX_SRES
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
6
PINNING
SYMBOL
PIN TYPE(1)
DESCRIPTION
n.c.
1
2
3
4
5
6
−
I
not connected
PD8
see Tables 8 to 13 for pin assignment
see Tables 8 to 13 for pin assignment
see Tables 8 to 13 for pin assignment
see Tables 8 to 13 for pin assignment
PD9
I
PD10
PD11
VDDD1
I
I
S
digital supply voltage 1 for pins PD11 to PD0, PIXCLKI, PIXCLKI, PIXCLKO,
FSVGC, VSVGC, HSVGC, CBO and TVD
VSSD1
7
S
I
digital ground 1
RESET
TMS
8
reset input; active LOW
9
I/pu
O
test mode select input for Boundary Scan Test (BST); note 2
test data output for BST; note 2
test clock input for BST; note 2
digital supply voltage 2 (3.3 V for I/Os)
digital ground 2
I2C-bus serial clock input
I2C-bus serial data input/output
TDO
10
11
12
13
14
15
16
17
TCK
I/pu
S
VDDD2
VSSD2
SCL
S
I
SDA
I/O
−
n.c.
not connected
FSVGC
I/O
frame synchronization output to Video Graphics Controller (VGC)
(optional input); note 3
VSVGC
PIXCLKI
PIXCLKI
PD3
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I
vertical synchronization output to VGC (optional input); note 3
inverted pixel clock input
I
pixel clock input (looped through)
I
MSB − 4 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB − 5 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB − 6 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB − 7 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
digital supply voltage 3 (3.3 V for core)
digital ground 3
PD2
I
PD1
I
PD0
I
VDDD3
VSSD3
PIXCLKO
CBO
S
S
O
I/O
I/O
−
pixel clock output to VGC
composite blanking output to VGC; active LOW; note 3
horizontal synchronization output to VGC (optional input); note 3
not connected
HSVGC
n.c.
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
OUT_EN
I/pu
if HIGH (default by pull-up): LLC, RTCI and SRES are outputs;
if LOW: LLC, RTCI and SRES are inputs
LLC
36
37
I/O
I/O
line-locked clock
RTCI
real-time control input
2004 Mar 04
6
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
SYMBOL
PIN TYPE(1)
DESCRIPTION
SRES
VSM
38
39
40
I/O
O
sync reset input
vertical synchronization output to monitor (non-interlaced auxiliary RGB)
HSM_CSYNC
O
horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or
composite sync for RGB-SCART
RED_CR_C_CVBS
41
O
O
S
analog output of RED or CR or C or CVBS signal
analog output of GREEN or VBS or CVBS signal
analog supply voltage 1 (3.3 V for DACs)
analog supply voltage 2 (3.3 V for DACs)
analog output of BLUE or CB or CVBS signal
GREEN_VBS_CVBS 42
VDDA1
43
44
45
46
VDDA2
S
BLUE_CB_CVBS
RSET
O
O
DAC reference pin; connected via 1 kΩ resistor to analog ground (do not use
capacitor in parallel with 1 kΩ resistor)
DUMP
VSSA1
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O
S
S
O
I
DAC reference pin; connected via 12 Ω resistor to analog ground
analog ground 1
VSSA2
analog ground 2
XTALO
XTALI
VDDA3
VDDA4
TVD
crystal oscillator output
crystal oscillator input
S
S
O
I/pu
I
analog supply voltage 3 (3.3 V for oscillator)
analog supply voltage 4 (3.3 V)
interrupt if TV is detected at DAC output
test reset input for BST; active LOW; notes 2, 4 and 5
test data input for BST; note 2
TRST
TDI
VSSD4
VDDD4
TTXRQ_XCLKO2
TTX_SRES
PD4
S
S
O
I
digital ground 4
digital supply voltage 4 (3.3 V for core)
teletext request output or 13.5 MHz clock output of the crystal oscillator; note 3
teletext input or sync reset input
I
MSB − 3 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB − 2 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB − 1 with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
MSB with CB-Y-CR 4 : 2 : 2; see Tables 8 to 13 for pin assignment
PD5
I
PD6
I
PD7
I
Notes
1. Pin type: I = input, O = output, S = supply, pu = pull-up.
2. In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCK and TRST are input pins with an internal
pull-up resistor and TDO is a 3-state output pin.
3. The pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
4. For board design without boundary scan implementation connect TRST to ground.
5. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
2004 Mar 04
7
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
n.c.
PD8
1
2
3
4
5
6
7
8
9
48
V
SSA1
47 DUMP
PD9
46 RSET
PD10
PD11
45 BLUE_CB_CVBS
44
43
V
V
DDA2
DDA1
V
DDD1
V
42 GREEN_VBS_CVBS
41 RED_CR_C_CVBS
40 HSM_CSYNC
39 VSM
SSD1
RESET
TMS
SAA7104H
SAA7105H
TDO 10
TCK 11
38 SRES
V
12
37 RTCI
DDD2
V
13
36 LLC
SSD2
SCL 14
SDA 15
n.c. 16
35 OUT_EN
34 n.c.
33 n.c.
MHC684
Fig.2 Pin configuration.
2004 Mar 04
8
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7
FUNCTIONAL DESCRIPTION
For ease of analog post filtering the signals are twice
oversampled to 27 MHz before digital-to-analog
conversion.
The digital video encoder encodes digital luminance and
colour difference signals (CB-Y-CR) or digital RGB signals
into analog CVBS, S-video and, optionally, RGB or
CR-Y-CB signals. NTSC M, PAL B/G and sub-standards
are supported.
The total filter transfer characteristics (scaler and
anti-flicker filter are not taken into account) are illustrated
in Figs 4 to 9. All three DACs are realized with full 10-bit
resolution. The CR-Y-CB to RGB dematrix can be
bypassed (optionally) in order to provide the upsampled
CR-Y-CB input signals.
The SAA7104H; SAA7105H can be directly connected to
a PC video graphics controller with a maximum resolution
of 1280 × 1024 (progressive) or 1920 × 1080 (interlaced)
at a 50 or 60 Hz frame rate. A programmable scaler scales
the computer graphics picture so that it will fit into a
standard TV screen with an adjustable underscan area.
Non-interlaced-to-interlaced conversion is optimized with
an adjustable anti-flicker filter for a flicker-free display at a
very high sharpness.
The 8-bit multiplexed CB-Y-CR formats are “ITU-R BT.656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. For assignment of the input data to the rising
or falling clock edge see Tables 8 to 13.
In order to display interlaced RGB signals through a
euro-connector TV set, a separate digital composite sync
signal (pin HSM_CSYNC) can be generated; it can be
advanced up to 31 periods of the 27 MHz crystal clock in
order to be adapted to the RGB processing of a TV set.
Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input
format (using 8 pins with double edge clocking), other
CB-Y-CR and RGB formats are also supported; see
Tables 8 to 13.
A complete 3 × 256 bytes Look-Up Table (LUT), which can
be used, for example, as a separate gamma corrector, is
located in the RGB domain; it can be loaded either through
the video input port PD (Pixel Data) or via the I2C-bus.
The SAA7104H; SAA7105H synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.
It is also possible to connect a Philips digital video decoder
(e.g. SAA7114H), using its line-locked clock for
re-encoding. Information containing actual subcarrier,
PAL-ID etc. is provided via pin RTCI which is connected to
pin RTCO of the decoder.
The SAA7104H; SAA7105H supports a 32 × 32 × 2-bit
hardware cursor, the pattern of which can also be loaded
through the video input port or via the I2C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video
signals such as PC-DVD; for that the anti-flicker filter, and
in most cases the scaler, will simply be bypassed.
Wide screen signalling data can be loaded via the I2C-bus
and is inserted into line 23 for standards using a 50 Hz
field rate.
Besides the applications for video output, the SAA7104H;
SAA7105H can also be used for generating a kind of
auxiliary VGA output, when the RGB non-interlaced input
signal is fed to the DACs. This may be of interest for
example, when the graphics controller provides a second
graphics window at its video output port.
VPS data for program dependent automatic start and stop
of such featured VCRs is loadable via the I2C-bus.
The IC also contains Closed Caption and extended data
services encoding (line 21), and supports teletext insertion
for the appropriate bit stream format at a 27 MHz clock rate
(see Fig.15). It is also possible to load data for the copy
generation management system into line 20 of every field
(525/60 line counting).
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals at a crystal-stable clock rate of
13.5 MHz (independent of the actual pixel clock used at
the input side), corresponding to an internal 4 : 2 : 2
bandwidth in the luminance/colour difference domain.
Luminance and chrominance signals are filtered in
accordance with the standard requirements of “RS-170-A”
and “ITU-R BT.470-3”.
A number of possibilities are provided for setting different
video parameters such as:
• Black and blanking level control
• Colour subcarrier frequency
• Variable burst amplitude etc.
2004 Mar 04
9
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.1
Reset conditions
If Y-CB-CR is being applied as a 27 Mbyte/s data stream,
the output of the input formatter can be used directly to
feed the video encoder block.
To activate the reset a pulse at least of 2 crystal clocks
duration is required.
The horizontal upscaling is supported via the input
formatter. According to the programming of the pixel clock
dividers (see Section 7.10), it will sample up the data
stream to 1 ×, 2 × or 4 × the input data rate. An optional
interpolation filter is available. The clock domain transition
is handled by a 4 entries wide FIFO which gets initialized
every field or explicitly at request. A bypass for the FIFO is
available, especially for high input data rates.
During reset (RESET = LOW) plus an extra 32 crystal
clock periods, FSVGC, VSVGC, CBO, HSVGC and
TTX_SRES are set to input mode and HSM_CSYNC and
VSM are set to 3-state. A reset also forces the I2C-bus
interface to abort any running bus transfer and sets it into
receive condition.
After reset, the state of the I/Os and other functions is
defined by the strapping pins until an I2C-bus access
redefines the corresponding registers; see Table 1.
7.3
RGB LUT
The three 256 byte RAMs of this block can be addressed
by three 8-bit wide signals, thus it can be used to build any
transformation, e.g. a gamma correction for RGB signals.
In the event that the indexed colour data is applied, the
RAMs are addressed in parallel.
Table 1 Strapping pins
PIN
FSVGC
TIED
PRESET
LOW NTSC M encoding, PIXCLK
fits to 640 × 480 graphics
input
The LUTs can either be loaded by an I2C-bus write access
or can be part of the pixel data input through the PD port.
In the latter case, 256 × 3 bytes for the R, G and B LUT are
expected at the beginning of the input video line, two lines
before the line that has been defined as first active line,
until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT
data, and so on.
HIGH PAL B/G encoding, PIXCLK
fits to 640 × 480 graphics
input
VSVGC
CBO
LOW 4 : 2 : 2 Y-CB-CR graphics
input (format 0)
HIGH 4 : 4 : 4 RGB graphics input
(format 3)
LOW input demultiplex phase:
LSB = LOW
7.4
Cursor insertion
A 32 × 32 dots cursor can be overlaid as an option; the bit
map of the cursor can be uploaded by an I2C-bus write
access to specific registers or in the pixel data input
through the PD port. In the latter case, the 256 bytes
defining the cursor bit map (2 bits per pixel) are expected
immediately following the last RGB LUT data in the line
preceding the first active line.
HIGH input demultiplex phase:
LSB = HIGH
HSVGC
LOW input demultiplex phase:
MSB = LOW
HIGH input demultiplex phase:
MSB = HIGH
TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and
HSVGC are inputs, internal
The cursor bit map is set up as follows: each pixel
occupies 2 bits. The meaning of these bits depends on the
CMODE I2C-bus register as described in Table 4.
Transparent means that the input pixels are passed
through, the ‘cursor colours’ can be programmed in
separate registers.
colour bar is active)
HIGH master (FSVGC, VSVGC
and HSVGC are outputs)
7.2
Input formatter
The bit map is stored with 4 pixels per byte, aligned to the
least significant bit. So the first pixel is in bits 0 and 1, the
next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left
corner.
The input formatter converts all accepted PD input data
formats, either RGB or Y-CB-CR, to a common internal
RGB or Y-CB-CR data stream.
When double-edge clocking is used, the data is internally
split into portions PPD1 and PPD2. The clock edge
assignment must be set according to the I2C-bus control
bits SLOT and EDGE for correct operation.
2004 Mar 04
10
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 2 Layout of a byte in the cursor bit map
Table 4 Cursor modes
D7
pixel n + 3
D1 D0
D6
D5
pixel n + 2
D1 D0
D4
D3
pixel n + 1
D1 D0
D2
D1
D0
CURSOR MODE
CMODE = 0 CMODE = 1
second cursor colour second cursor colour
CURSOR
PATTERN
pixel n
D1
D0
00
01
10
11
first cursor colour
transparent
first cursor colour
transparent
For each direction, there are 2 registers controlling the
position of the cursor, one controls the position of the
‘hot spot’, the other register controls the insertion position.
The hot spot is the ‘tip’ of the pointer arrow. It can have any
position in the bit map. The actual position registers
describe the co-ordinates of the hot spot. Again 0,0 is the
upper left corner. While it is not possible to move the
hot spot beyond the left respectively upper screen border
this is perfectly legal for the right respectively lower border.
It should be noted that the cursor position is described
relative to the input resolution.
inverted input
auxiliary cursor
colour
7.5
RGB Y-CB-CR matrix
RGB input signals to be encoded to PAL or NTSC are
converted to the Y-CB-CR colour space in this block. The
colour difference signals are fed through low-pass filters
and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream
for further processing.
A gain adjust option corrects the level swing of the
graphics world (black-to-white as 0 to 255) to the required
range of 16 to 235.
Table 3 Cursor bit map
BYTE
D7 D6 D5 D4 D3 D2 D1 D0
row 0 row 0 row 0 row 0
column 3 column 2 column 1 column 0
row 0 row 0 row 0 row 0
column 7 column 6 column 5 column 4
0
1
2
The matrix and formatting blocks can be bypassed for
Y-CB-CR graphics input.
When the auxiliary VGA mode is selected, the output of the
cursor insertion block is immediately directed to the triple
DAC.
row 0
column
11
row 0
column
10
row 0
column 9 column 8
row 0
7.6
Horizontal scaler
...
6
...
...
...
...
The high quality horizontal scaler operates on the 4 : 2 : 2
data stream. Its control engines compensate the colour
phase offset automatically.
row 0
column
27
row 0
column
26
row 0
column
25
row 0
column
24
The scaler starts processing after a programmable
horizontal offset and continues with a number of input
pixels. Each input pixel is a programmable fraction of the
current output pixel (XINC/4096). A special case is
XINC = 0, this sets the scaling factor to 1.
7
row 0
column
31
row 0
column
30
row 0
column
29
row 0
column
28
...
...
...
...
...
254
row 31
column
27
row 31
column
26
row 31
column
25
row 31
column
24
If the SAA7104H; SAA7105H input data is in accordance
with “ITU-R BT.656”, the scaler enters another mode.
In this event, XINC needs to be set to 2048 for a scaling
factor of 1. With higher values, upscaling will occur.
255
row 31
column
31
row 31
column
30
row 31
column
29
row 31
column
28
The phase resolution of the circuit is 12 bits, giving a
maximum offset of 0.2 after 800 input pixels. Small FIFOs
rearrange a 4 : 2 : 2 data stream at the scaler output.
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.7
Vertical scaler and anti-flicker filter
7.10 Oscillator and Discrete Time Oscillator (DTO)
The functions scaling, Anti-Flicker Filter (AFF) and
re-interlacing are implemented in the vertical scaler.
The master clock generation is realized as a 27 MHz
crystal oscillator, which can operate with either a
fundamental wave crystal or a 3rd-harmonic crystal.
Besides the entire input frame, it receives the first and last
lines of the border to allow anti-flicker filtering.
The crystal clock supplies the DTO of the pixel clock
synthesizer, the video encoder and the I2C-bus control
block. It also usually supplies the triple DAC, with the
exception of the auxiliary VGA or HDTV mode, where the
triple DAC is clocked by the pixel clock (PIXCLK).
The circuit generates the interlaced output fields by scaling
down the input frames with different offsets for odd and
even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off;
see Table 85.
The DTO can be programmed to synthesize all relevant
pixel clock frequencies between circa 40 and 85 MHz.
Two programmable dividers provide the actual clock to be
used externally and internally. The dividers can be
programmed to factors of 1, 2, 4 and 8. For the internal
pixel clock, a divider ratio of 8 makes no sense and is thus
forbidden.
An additional, programmable vertical filter supports the
anti-flicker function. This filter is not available at upscaling
factors of more than 2.
The programming is similar to the horizontal scaler. For the
re-interlacing, the resolutions of the offset registers are not
sufficient, so the weighting factors for the first lines can
also be adjusted. YINC = 0 sets the scaling factor to 1;
YIWGTO and YIWGTE must not be 0.
The internal clock can be switched completely to the pixel
clock input. In this event, the input FIFO is useless and will
be bypassed.
Due to the re-interlacing, the circuit can perform upscaling
by a maximum factor of 2. The maximum factor depends
on the setting of the anti-flicker function and can be derived
from the formulae given in Section 7.20.
The entire pixel clock generation can be locked to the
vertical frequency. Both pixel clock dividers get
re-initialized every field. Optionally, the DTO can be
cleared with each V-sync. At proper programming, this will
make the pixel clock frequency a precise multiple of the
vertical and horizontal frequencies. This is required for
some graphic controllers.
An additional upscaling mode allows to increase the
upscaling factor to maximum 4 as it is required for the old
VGA modes like 320 × 240.
7.8
FIFO
7.11 Low-pass Clock Generation Circuit (CGC)
The FIFO acts as a buffer to translate from the PIXCLK
clock domain to the XTAL clock domain. The write clock is
PIXCLK and the read clock is XTAL. An underflow or
overflow condition can be detected via the I2C-bus read
access.
This block reduces the phase jitter of the synthesized pixel
clock. It works as a tracking filter for all relevant
synthesized pixel clock frequencies.
7.12 Encoder
In order to avoid underflows and overflows, it is essential
that the frequency of the synthesized PIXCLK matches to
the input graphics resolution and the desired scaling
factor.
7.12.1 VIDEO PATH
The encoder generates luminance and colour subcarrier
output signals from the Y, CB and CR baseband signals,
which are suitable for use as CVBS or separate Y and C
signals.
7.9
Border generator
Input to the encoder, at 27 MHz clock (e.g. DVD), is either
originated from computer graphics at pixel clock, fed
through the FIFO and border generator, or a ITU-R BT.656
style signal.
When the graphics picture is to be displayed as interlaced
PAL, NTSC, S-video or RGB on a TV screen, it is desired
in many cases not to lose picture information due to the
inherent overscanning of a TV set. The desired amount of
underscan area, which is achieved through appropriate
scaling in the vertical and horizontal direction, can be filled
in the border generator with an arbitrary true colour tint.
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Luminance is modified in gain and in offset (the offset is
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level, in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process, such as additional insertion of AGC super-white
pulses (programmable in height), are supported by the
SAA7104H only.
for both fields. The internal insertion window for text is set
to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.15.
Alternatively, this pin can be provided with a buffered
crystal clock (XCLK) of 13.5 MHz.
7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
Five bytes of VPS information can be loaded via the
I2C-bus and will be encoded in the appropriate format into
line 16.
To enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
The transfer characteristics of the luminance interpolation
filter are illustrated in Figs 6 and 7. Appropriate transients
at start/end of active video and for synchronization pulses
are ensured.
7.12.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification
of Closed Caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
Chrominance is modified in gain (programmable
separately for CB and CR), and a standard dependent
burst is inserted, before baseband colour signals are
interpolated from a 6.75 MHz data rate to a 27 MHz data
rate. One of the interpolation stages can be bypassed,
thus providing a higher colour bandwidth, which can be
used for the Y and C output. The transfer characteristics of
the chrominance interpolation filter are illustrated in
Figs 4 and 5.
The actual line number in which data is to be encoded, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC M standard 32 times horizontal line
frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
The amplitude (beginning and ending) of the inserted
burst, is programmable in a certain range that is suitable
for standard signals and for special effects. After the
succeeding quadrature modulator, colour is provided on
the subcarrier in 10-bit resolution.
It is also possible to encode Closed Caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
The numeric ratio between the Y and C outputs is in
accordance with the standards.
7.12.5 ANTI-TAPING (SAA7104H ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
7.12.2 TELETEXT INSERTION AND ENCODING (NOT
SIMULTANEOUSLY WITH REAL-TIME CONTROL)
7.13 RGB processor
Pin TTX_SRES receives a WST or NABTS teletext
bitstream sampled at the crystal clock. At each rising edge
of the output signal (TTXRQ) a single teletext bit has to be
provided after a programmable delay at input pin
TTX_SRES.
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, CB and CR signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 8 and 9.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request
signal to the teletext source, indicating the insertion period
of bitstream at lines which can be selected independently
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.14 Triple DAC
In slave mode, the circuit accepts sync pulses on the
bidirectional FSVGC (frame sync), VSVGC (vertical sync)
and HSVGC (horizontal sync) pins: the polarities of the
signals can be programmed. The frame sync signal is only
necessary when the input signal is interlaced, in other
cases it may be omitted. If the frame sync signal is present,
it is possible to derive the vertical and the horizontal phase
from it by setting the HFS and VFS bits. HSVGC and
VSVGC are not necessary in this case, so it is possible to
switch the pins to output mode.
Both Y and C signals are converted from digital-to-analog
in a 10-bit resolution at the output of the video encoder.
Y and C signals are also combined into a 10-bit CVBS
signal.
The CVBS output signal occurs with the same processing
delay as the Y, C and optional RGB or CR-Y-CB outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by 15
⁄16 with respect to Y and C DACs to make
maximum use of the conversion ranges.
Alternatively, the device can be triggered by auxiliary
codes in a ITU-R BT.656 data stream via PD7 to PD0.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 10-bit resolution.
Only vertical frequencies of 50 and 60 Hz are allowed with
the SAA7104H; SAA7105H. In slave mode, it is not
possible to lock the encoders colour carrier to the line
frequency with the PHRES bits.
The reference currents of all three DACs can be adjusted
individually in order to adapt for different output signals.
In addition, all reference currents can be adjusted
commonly to compensate for small tolerances of the
on-chip band gap reference voltage.
In the (more common) master mode, the time base of the
circuit is continuously free-running. The IC can output a
frame sync at pin FSVGC, a vertical sync at pin VSVGC, a
horizontal sync at pin HSVGC and a composite blanking
signal at pin CBO. All of these signals are defined in the
PIXCLK domain. The duration of HSVGC and VSVGC are
fixed, they are 64 clocks for HSVGC and 1 line for VSVGC.
The leading slopes are in phase and the polarities can be
programmed.
Alternatively, all currents can be switched off to reduce
power dissipation.
All three outputs can be used to sense for an external load
(usually 75 Ω) during a pre-defined output. A flag in the
I2C-bus status byte reflects whether a load is applied or
not. In addition, an automatic sense mode can be
activated which indicates a 75 Ω load at any of the three
outputs at the dedicated interrupt pin TVD.
The input line length can be programmed. The field length
is always derived from the field length of the encoder and
the pixel clock frequency that is being used.
If the SAA7104H; SAA7105H is required to drive a second
(auxiliary) VGA monitor or an HDTV set, the DACs receive
the signal coming from the HD data path. In this event, the
DACs are clocked at the incoming PIXCLKI instead of the
27 MHz crystal clock used in the video encoder.
CBO acts as a data request signal. The circuit accepts
input data at a programmable number of clocks after CBO
goes active. This signal is programmable and it is possible
to adjust the following (see Figs 13 and 14):
7.15 HD data path
• The horizontal offset
This data path allows the SAA7104H; SAA7105H to be
used with VGA or HDTV monitors. It receives its data
directly from the cursor generator and supports RGB and
Y-PB-PR output formats (RGB not with Y-PB-PR input
formats). No scaling is done in this mode.
• The length of the active part of the line
• The distance from active start to first expected data
• The vertical offset separately for odd and even fields
• The number of lines per input field.
A gain adjustment either leads the full level swing to the
digital-to-analog converters or reduces the amplitude by a
factor of 0.69. This enables sync pulses to be added to the
signal as it is required for display units expecting signals
with sync pulses, either regular or 3-level syncs.
In most cases, the vertical offsets for odd and even fields
are equal. If they are not, then the even field will start later.
The SAA7104H; SAA7105H will also request the first input
lines in the even field, the total number of requested lines
will increase by the difference of the offsets.
As stated above, the circuit can be programmed to accept
the look-up and cursor data in the first 2 lines of each field.
The timing generator provides normal data request pulses
for these lines; the duration is the same as for regular lines.
7.16 Timing generator
The synchronization of the SAA7104H; SAA7105H is able
to operate in two modes; slave mode and master mode.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
The additional request pulses will be suppressed with
LUTL set to logic 0; see Table 108. The other vertical
timings do not change in this case, so the first active line
can be number 2, counted from 0.
image, the lines as well as fractions of lines. Figure 3
illustrates the context between the various tables.
The first table serves as an array to hold the correct
sequence of lines that compose the synchronization
raster; it can contain up to 16 entries. Each entry holds a
4-bit index to the next table and a 10-bit counter value
which specifies how often this particular line is invoked.
If the necessary line count for a particular line exceeds the
10 bits, it has to use two table entries.
7.17 Pattern generator for HD sync pulses
The pattern generator provides appropriate
synchronization patterns for the video data path in
auxiliary monitor or HDTV mode. It provides maximum
flexibility in terms of raster generation for all interlaced and
non-interlaced computer graphics or ATSC formats. The
sync engine is capable of providing a combination of
event-value pairs which can be used to insert certain
values in the outgoing data stream at specified times.
It can also be used to generate digital signals associated
with time events. These can be used as digital horizontal
and vertical synchronization signals on pins HSM_CSYNC
and VSM.
The 4-bit index in the line count array points to the line type
array. It holds up to 15 entries (index 0 is not used),
index 1 points to the first entry, index 2 to the second entry
of the line type array etc.
Each entry of the line type array can hold up to 8 index
pointers to another table. These indices point to portions of
a line pulse pattern: A line could be split up e.g. into a sync,
a blank, and an active portion followed by another blank
portion, occupying four entries in one table line.
The picture position is adjustable through the
programmable relationship between the sync pulses and
the video contents.
Each index of this table points to a particular line of the
next table in the linked list. This table is called the line
pattern array and each of the up to seven entries stores up
to four pairs of a duration in pixel clock cycles and an index
to a value table. The table entries are used to define
portions of a line representing a certain value for a certain
number of clock cycles.
The generation of embedded analog sync pulses is bound
to a number of events which can be defined for a line.
Several of these line timing definitions can exist in parallel.
For the final sync raster composition a certain sequence of
lines with different sync event properties has to be defined.
The sequence specifies a series of line types and the
number of occurrences of this specific line type. Once the
sequence has been completed, it restarts from the
beginning. All pulse shapes are filtered internally in order
to avoid ringing after analog post filters.
The value specified in this table is actually another 3-bit
index into a value array which can hold up to eight 8-bit
values. If bit 4 (MSB) of the index is logic 1, the value is
inserted into the G or Y signal, only; if bit 4 = 0, the
associated value is inserted into all three signals.
The sequence of the generated pulse stream must fit
precisely to the incoming data stream in terms of the total
number of pixels per line and lines per frame.
Two additional bits of the entries in the value array (LSBs
of the second byte) determine if the associated events
appear as a digital pulse on the HSM_CSYNC and/or VSM
outputs.
The sync engines flexibility is achieved by using a
sequence of linked lists carrying the properties for the
2004 Mar 04
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4-bit line type index
10-bit line count
line
count
pointer
LINE COUNT ARRAY
16 entries
line type pointer
3
3
3
3
3
3
3
3
3
3
3
3
pattern pointer
LINE TYPE ARRAY
15 entries
3
3
3
3
event type pointer
10-bit duration
10-bit duration
10-bit duration
4-bit value index
10-bit duration
4-bit value index
4-bit value index
4-bit value index
LINE PATTERN ARRAY
7 entries
8 + 2-bit value
VALUE ARRAY
8 entries
line pattern pointer
MHC573
Fig.3 Context between the pattern generator tables for DH sync pulses.
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
To ease the trigger set-up for the sync generation module,
a set of registers is provided to set up the screen raster
which is defined as width and height. A trigger position can
be specified as an x,y co-ordinate within the overall
dimensions of the screen raster. If the x,y counter matches
the specified co-ordinates, a trigger pulse is generated
which pre-loads the tables with their initial values.
Important note:
Due to a problem in the programming interface, writing to
the line pattern array (address D2) might destroy the data
of the line type array (address D1). A work around is to
write the line pattern array data before writing the line type
array. Reading of the arrays is possible but all address
pointers must be initialized before the next write operation.
The listing in Table 5 outlines an example on how to set up
the sync tables for a 1080i HD raster.
Table 5 Example for set-up of the sync tables
SEQUENCE
COMMENT
Write to subaddress D0H
00
points to first entry of line count array (index 0)
05 20
generate 5 lines of line type index 2 (this is the second entry of the line type array); will be
the first vertical raster pulse
01 40
generate 1 line of line type index 4; will be sync-black-sync-black sequence after the first
vertical pulse
0E 60
1C 12
02 60
01 50
generate 14 lines of line type index 6; will be the following lines with sync-black sequence
generate 540 lines of line type index 1; will be lines with sync and active video
generate 2 lines of line type index 6; will be the following lines with sync-black sequence
generate 1 line of line type index 5; will be the following line (line 563) with
sync-black-sync-black-null sequence (null is equivalent to sync tip)
04 20
01 30
generate 4 lines of line type index 2; will be the second vertical raster pulse
generate 1 line of line type index 3; will be the following line with sync-null-sync-black
sequence
0F 60
1C 12
02 60
generate 15 lines of line type index 6; will be the following lines with sync-black sequence
generate 540 lines of line type index 1; will be lines with sync and active video
generate 2 lines of line type index 6; will be the following lines with sync-black sequence;
now, 1125 lines are defined
Write to subaddress D2H (insertion is done into all three analog output signals)
00 points to first entry of line pattern array (index 1)
6F 33 2B 30 00 00 00 00 880 × value(3) + 44 × value(3); (subtract 1 from real duration)
6F 43 2B 30 00 00 00 00 880 × value(4) + 44 × value(3)
3B 30 BF 03 BF 03 2B 30 60 × value(3) + 960 × value(0) + 960 × value(0) + 44 × value(3)
2B 10 2B 20 57 30 00 00 44 × value(1) + 44 × value(2) + 88 × value(3)
3B 30 BF 33 BF 33 2B 30 60 × value(3) + 960 × value(3) + 960 × value(3) + 44 × value(3)
Write to subaddress D1H
00
points to first entry of line type array (index 1)
34 00 00 00
24 24 00 00
24 14 00 00
14 14 00 00
use pattern entries 4 and 3 in this sequence (for sync and active video)
use pattern entries 4, 2, 4 and 2 in this sequence (for 2 × sync-black-null-black)
use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null)
use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black)
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
SEQUENCE
COMMENT
14 24 00 00
54 00 00 00
use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null)
use pattern entries 4 and 5 in this sequence (for sync-black)
Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM)
00
points to first entry of value array (index 0)
black level, to be added during active video
sync level LOW (minimum output voltage)
sync level HIGH (3-level sync)
CC 00
80 00
0A 00
CC 00
80 00
black level (needed elsewhere)
null (identical to sync level LOW)
Write to subaddress DCH
0B
insertion is active, gain for signal is adapted accordingly
7.18 I2C-bus interface
Because the analog power-down mode turns off the pixel
clock synthesizer, there are limitations in some
applications. If there is no pixel clock, the IC is not able to
set its outputs to LOW. So, in most cases, DOWNA and
DOWND should be set to logic 1 simultaneously. If the
EIDIV bit is logic 1, it should be set to logic 0 before
power-down.
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
read, except two read only status bytes.
The register bit map consists of an RGB Look-Up Table
(LUT), a cursor bit map and control registers. The LUT
contains three banks of 256 bytes, where each RGB triplet
is assigned to one address. Thus a write access needs the
LUT address and three data bytes following subaddress
FFH. For further write access auto-incrementing of the
LUT address is performed. The cursor bit map access is
similar to the LUT access but contains only a single byte
per address.
7.20 Programming the SAA7104H; SAA7105H
The SAA7104H; SAA7105H needs to provide a
continuous data stream at its analog outputs as well as
receive a continuous stream of data from its data source.
Because there is no frame memory isolating the data
streams, restrictions apply to the input frame timings.
Input and output processing of the SAA7104H; SAA7105H
are only coupled through the vertical frequencies. In
master mode, the encoder provides a vertical sync and an
odd/even pulse to the input processing. In slave mode, the
encoder receives them.
The I2C-bus slave address is defined as 88H.
7.19 Power-down modes
In order to reduce the power consumption, the SAA7104H;
SAA7105H supports 2 power-down modes, accessible via
the I2C-bus. The analog power-down mode (DOWNA = 1)
turns off the digital-to-analog converters and the pixel
clock synthesizer. The digital power-down mode turns off
all internal clocks and sets the digital outputs to LOW
except the I2C-bus interface. The IC keeps its
programming and can still be accessed in this mode,
however not all registers can be read or written to. Reading
or writing to the look-up tables, the cursor and the HD sync
generator require a valid pixel clock. The typical supply
current in full power-down is approximately 5 mA.
The parameters of the input field are mainly given by the
memory capacity of the SAA7104H; SAA7105H. The rule
is that the scaler and thus the input processing needs to
provide the video data in the same time frames as the
encoder reads them. Therefore, the vertical active video
times (and the vertical frequencies) need to be the same.
The second rule is that there has to be data in the buffer
FIFO when the encoder enters the active video area.
Therefore, the vertical offset in the input path needs to be
a bit shorter than the offset of the encoder.
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
The following Sections give the set of equations required
to program the IC for the most common application: A post
processor in master mode with non-interlaced video input
data.
The required pixel clock frequency can be determined in
the following way: Due to the limited internal FIFO size, the
input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to
process the first and last border lines for the anti-flicker
function. Thus:
Some variables are defined below:
• InPix: the number of active pixels per input line
• InPpl: the length of the entire input line in pixel clocks
• InLin: the number of active lines per input field/frame
• TPclk: the pixel clock period
262.5 × 1716 × TXclk
TPclk =
(60 Hz)
---------------------------------------------------------------------------------------
InLin + 2
InPpl × integer
× 262.5
----------------------
OutLin
312.5 × 1728 × TXclk
TPclk =
(50 Hz)
---------------------------------------------------------------------------------------
InLin + 2
OutLin
• RiePclk: the ratio of internal to external pixel clock
• OutPix: the number of active pixels per output line
• OutLin: the number of active lines per output field
• TXclk: the encoder clock period (37.037 ns).
InPpl × integer
× 312.5
----------------------
and for the pixel clock generator
TXclk
PCL =
× 220 + PCLE (all frequencies);
--------------
TPclk
see Tables 67, 69 and 70. The divider PCLE should be set
according to Table 69. PCLI may be set to a lower or the
same value. Setting a lower value means that the internal
pixel clock is higher and the data get sampled up. The
difference may be 1 at 640 × 480 pixels resolution and 2 at
resolutions with 320 pixels per line as a rule of thumb. This
allows horizontal upscaling by a maximum factor of 2
respectively 4 (this is the parameter RiePclk).
7.20.1 TV DISPLAY WINDOW
At 60 Hz, the first visible pixel has the index 256,
710 pixels can be encoded; at 50 Hz, the index is 284,
702 pixels can be visible.
The output lines should be centred on the screen. It should
be noted that the encoder has 2 clocks per pixel;
see Table 58.
logRiePclk
ADWHS = 256 + 710 − OutPix (60 Hz);
ADWHS = 284 + 702 − OutPix (50 Hz);
ADWHE = ADWHS + OutPix × 2 (all frequencies)
PCLI = PCLE –
(all frequencies)
----------------------------
log2
The equations ensure that the last line of the field has the
full number of clock cycles. Many graphic controllers
require this. Note that the bit PCLSY needs to be set to
ensure that there is not even a fraction of a clock left at the
end of the field.
For vertical, the procedure is the same. At 60 Hz, the first
line with video information is number 19, 240 lines can be
active. For 50 Hz, the numbers are 23 and 287;
see Table 64.
240 – OutLin
7.20.3 HORIZONTAL SCALER
FAL = 19 +
FAL = 23 +
(60 Hz);
(50 Hz);
---------------------------------
2
XOFS can be chosen arbitrarily, the condition being that
XOFS + XPIX ≤ HLEN is fulfilled. Values given by the
VESA display timings are preferred.
287 – OutLin
---------------------------------
2
LAL = FAL + OutLin (all frequencies)
HLEN = InPpl × RiePclk − 1
Most TV sets use overscan, and not all pixels respectively
lines are visible. There is no standard for the factor, it is
highly recommended to make the number of output pixels
and lines adjustable. A reasonable underscan factor is
10%, giving approximately 640 output pixels per line.
InPix
2
XPIX =
XINC =
× RiePclk
------------
OutPix
4096
×
----------------- -------------------
InPix RiePclk
XINC needs to be rounded up, it needs to be set to 0 for a
scaling factor of 1.
7.20.2 INPUT FRAME AND PIXEL CLOCK
The total number of pixel clocks per line and the input
horizontal offset need to be chosen next. The only
constraint is that the horizontal blanking has at least
10 clock pulses.
2004 Mar 04
19
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.20.4 VERTICAL SCALER
Or the upscaling factor needs to be limited to 1.5 and the
horizontal upscaling factor is also limited to less than
1.5. In this case a normal blanking length is sufficient.
The input vertical offset can be taken from the assumption
that the scaler should just have finished writing the first line
when the encoder starts reading it:
7.21 Input levels and formats
FAL × 1716 × TXclk
YOFS =
YOFS =
– 2.5 (60 Hz)
– 2.5 (50 Hz)
----------------------------------------------------
The SAA7104H; SAA7105H accepts digital Y, CB, CR or
RGB data with levels (digital codes) in accordance with
“ITU-R BT.601”. An optional gain adjustment also allows
to accept data with the full level swing of 0 to 255.
InPpl × TPclk
FAL × 1728 × TXclk
----------------------------------------------------
InPpl × TPclk
In most cases the vertical offsets will be the same for odd
and even fields. The results should be rounded down.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated for by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
YPIX = InLin
YSKIP defines the anti-flicker function. 0 means maximum
flicker reduction but minimum vertical bandwidth, 4095
gives no flicker reduction and maximum bandwidth. Note
that the maximum value for YINC is 4095. It might be
necessary to reduce the value of YSKIP to fulfil this
requirement.
The RGB, respectively CR-Y-CB path features an
individual gain setting for luminance (GY) and colour
difference signals (GCD). Reference levels are measured
with a colour bar, 100% white, 100% amplitude and
100% saturation.
OutLin
----------------------
InLin + 2
YSKIP
-----------------
4095
YINC =
× 1 +
× 4096
The SAA7104H; SAA7105H has special input cells for the
VGC port. They operate at a wider supply voltage range
and have a strict input threshold at 1/2VDDD. To achieve full
speed of these cells, the EIDIV bit needs to be set to
logic 1. Note that the impedance of these cells is
approximately 6 kΩ. This may cause trouble with the
bootstrapping pins of some graphic chips. So the
power-on reset forces the bit to logic 0, the input
impedance is regular in this mode.
YINC
2
YIWGTO =
YIWGTE =
+ 2048
-------------
YINC – YSKIP
-------------------------------------
2
When YINC = 0 it sets the scaler to scaling factor 1. The
initial weighting factors must not be set to 0 in this case.
YIWGTE may go negative. In this event, YINC should be
added and YOFSE incremented. This can be repeated as
often as necessary to make YIWGTE positive.
Table 6 “ITU-R BT.601” signal component levels
SIGNALS(1)
COLOUR
It should be noted that these equations assume that the
input is non-interlaced but the output is interlaced. If the
input is interlaced, the initial weighting factors need to be
adapted to obtain the proper phase offsets in the output
frame.
Y
CB
235 128 128 235 235 235
210 16 146 235 235 16
170 166 235 235
145 54
CR
R
G
B
White
Yellow
Cyan
16
34
16
16
If vertical upscaling beyond the upper capabilities is
required, the parameter YUPSC may be set to logic 1. This
extends the maximum vertical scaling factor by a factor
of 2. Only the parameter YINC is affected, it needs to be
divided by two to get the same effect.
Green
Magenta
Red
235
16
16
16
16
16
235
16
106 202 222 235
81
41
16
90
240 235
Blue
240 110
128 128
16
16
235
16
There are restrictions in this mode:
Black
• The vertical filter YFILT is not available in this mode; the
circuit will ignore this value
Note
1. Transformation:
a) R = Y + 1.3707 × (CR − 128)
• The horizontal blanking needs to be long enough to
transfer an output line between 2 memory locations.
This is 710 internal pixel clocks.
b) G = Y − 0.3365 × (CB − 128) − 0.6982 × (CR − 128)
c) B = Y + 1.7324 × (CB − 128).
2004 Mar 04
20
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 7 Usage of bits SLOTand EDGE
Table 9 Pin assignment for input format 1
5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
DATA SLOT CONTROL
(EXAMPLE FOR FORMAT 0)
FALLING
CLOCK EDGE
RISING
CLOCK EDGE
PIN
SLOT
EDGE
1ST DATA
2ND DATA
0
0
at rising edge
G3/Y3
at falling edge
R7/CR7
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
G2
G1
G0
B4
B3
B2
B1
B0
X
R4
R3
R2
R1
R0
G4
G3
0
1
1
1
0
1
at falling edge
G3/Y3
at rising edge
R7/CR7
at rising edge
R7/CR7
at falling edge
G3/Y3
at falling edge
R7/CR7
at rising edge
G3/Y3
Table 8 Pin assignment for input format 0
Table 10 Pin assignment for input format 2
8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED
RGB/CB-Y-CR
5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
FALLING
CLOCK EDGE
RISING
CLOCK EDGE
FALLING
CLOCK EDGE
RISING
CLOCK EDGE
PIN
PIN
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
G3/Y3
G2/Y2
R7/CR7
R6/CR6
R5/CR5
R4/CR4
R3/CR3
R2/CR2
R1/CR1
R0/CR0
G7/Y7
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
G2
G1
G0
B4
B3
B2
B1
B0
R4
R3
R2
R1
R0
G5
G4
G3
G1/Y1
G0/Y0
B7/CB7
B6/CB6
B5/CB5
B4/CB4
B3/CB3
B2/CB2
B1/CB1
B0/CB0
Table 11 Pin assignment for input format 3
8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR
FALLING RISING FALLING RISING
G6/Y6
G5/Y5
G4/Y4
CLOCK
EDGE
n
CLOCK
EDGE
n
CLOCK
EDGE
n + 1
CLOCK
EDGE
n + 1
PIN
PD7
CB7(0)
CB6(0)
CB5(0)
CB4(0)
CB3(0)
CB2(0)
CB1(0)
CB0(0)
Y7(0)
Y6(0)
Y5(0)
Y4(0)
Y3(0)
Y2(0)
Y1(0)
Y0(0)
CR7(0)
CR6(0)
CR5(0)
CR4(0)
CR3(0)
CR2(0)
CR1(0)
CR0(0)
Y7(1)
Y6(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Y0(1)
PD6
PD5
PD4
PD3
PD2
PD1
PD0
2004 Mar 04
21
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 12 Pin assignment for input format 4
Table 14 Pin assignment for input format 6
8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR
(ITU-R BT.656, 27 MHz CLOCK)
8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED
RGB/CB-Y-CR
RISING
CLOCK
EDGE
n
RISING
CLOCK
EDGE
n + 1
RISING
CLOCK
EDGE
n + 2
RISING
CLOCK
EDGE
n + 3
FALLING
CLOCK EDGE
RISING
CLOCK EDGE
PIN
PIN
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
G4/Y4
G3/Y3
R7/CR7
R6/CR6
R5/CR5
R4/CR4
R3/CR3
G7/Y7
PD7
CB7(0)
CB6(0)
CB5(0)
CB4(0)
CB3(0)
CB2(0)
CB1(0)
CB0(0)
Y7(0)
Y6(0)
Y5(0)
Y4(0)
Y3(0)
Y2(0)
Y1(0)
Y0(0)
CR7(0)
CR6(0)
CR5(0)
CR4(0)
CR3(0)
CR2(0)
CR1(0)
CR0(0)
Y7(1)
Y6(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Y0(1)
G2/Y2
PD6
PD5
PD4
PD3
PD2
PD1
PD0
B7/CB7
B6/CB6
B5/CB5
B4/CB4
B3/CB3
G0/Y0
G6/Y6
G5/Y5
R2/CR2
R1/CR1
R0/CR0
G1/Y1
B2/CB2
B1/CB1
B0/CB0
Table 13 Pin assignment for input format 5; note 1
8-BIT NON-INTERLACED INDEX COLOUR
FALLING
CLOCK EDGE
RISING
CLOCK EDGE
PIN
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INDEX7
INDEX6
INDEX5
INDEX4
INDEX3
INDEX2
INDEX1
INDEX0
Note
1. X = don’t care.
2004 Mar 04
22
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7.22 Bit allocation map
Table 15 Slave receiver (slave address 88H)
SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
(1)
(1)
Status byte (read only)
Null
00
01 to 15
16
VER2
(1)
VER1
(1)
VER0
(1)
CCRDO
CCRDE
FSEQ
(1)
O_E
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Common DAC adjust fine
R DAC adjust coarse
G DAC adjust coarse
B DAC adjust coarse
MSM threshold
DACF3
RDACC3
GDACC3
BDACC3
DACF2
RDACC2
GDACC2
BDACC2
MSMT2
RCOMP
CID2
DACF1
RDACC1
GDACC1
BDACC1
MSMT1
GCOMP
CID1
DACF0
RDACC0
GDACC0
BDACC0
MSMT0
BCOMP
CID0
17
RDACC4
GDACC4
BDACC4
18
19
1A
MSMT7
MSM
MSMT6
MSA
MSMT5
MSOE
CID5
MSMT4
MSMT3
(1)
(1)
Monitor sense mode
Chip ID (02B or 03B, read only)
Wide screen signal
Wide screen signal
Real-time control, burst start
Sync reset enable, burst end
Copy generation 0
Copy generation 1
CG enable, copy generation 2
Output port control
Null
1B
1C
26
CID7
CID6
CID4
WSS4
WSS12
BS4
CID3
WSS3
WSS11
BS3
WSS7
WSS6
(1)
WSS5
WSS13
BS5
WSS2
WSS10
BS2
WSS1
WSS9
BS1
WSS0
WSS8
BS0
27
WSSON
(1)
(1)
(1)
28
29
SRES
CG07
CG15
CGEN
BE5
BE4
BE3
BE2
BE1
BE0
2A
CG06
CG05
CG04
CG03
CG11
CG19
CG02
CG01
CG00
2B
CG14
(1)
CG13
(1)
CG12
(1)
CG10
CG09
CG08
2C
2D
2E to 36
37
CG18
CG17
CG16
(1)
VBSEN
CVBSEN1 CVBSEN0
CEN
(1)
ENCOFF
CLK2EN
CVBSEN2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Input path control
YUPSC
YFIL1
(1)
YFIL0
GY4
CZOOM
GY2
IGAIN
GY1
XINT
GY0
(1)
Gain luminance for RGB
Gain colour difference for RGB
Input port control 1
VPS enable, input control 2
VPS byte 5
38
GY3
(1)
(1)
(1)
(1)
39
GCD4
GCD3
GCD2
GCD1
GCD0
3A
CBENB
VPSEN
VPS57
SYNTV
GPVAL
VPS55
SYMP
DEMOFF
CSYNC
Y2C
UV2C
(1)
(1)
54
GPEN
EDGE
VPS51
VPS111
VPS121
VPS131
VPS141
CHPS1
SLOT
55
VPS56
VPS116
VPS126
VPS136
VPS146
CHPS6
VPS54
VPS114
VPS124
VPS134
VPS144
CHPS4
VPS53
VPS113
VPS123
VPS133
VPS143
CHPS3
VPS52
VPS112
VPS122
VPS132
VPS142
CHPS2
VPS50
VPS110
VPS120
VPS130
VPS140
CHPS0
VPS byte 11
56
VPS117
VPS127
VPS137
VPS147
CHPS7
VPS115
VPS125
VPS135
VPS145
CHPS5
VPS byte 12
57
VPS byte 13
58
VPS byte 14
59
Chrominance phase
5A
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SUB
REGISTER FUNCTION
Gain U
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
GAINU7
GAINV7
GAINU8
GAINV8
GAINU6
GAINU5
GAINV5
BLCKL5
BLNNL5
GAINU4
GAINV4
BLCKL4
BLNNL4
GAINU3
GAINV3
BLCKL3
BLNNL3
GAINU2
GAINV2
BLCKL2
BLNNL2
GAINU1
GAINV1
BLCKL1
BLNNL1
GAINU0
GAINV0
BLCKL0
BLNNL0
Gain V
GAINV6
(1)
Gain U MSB, black level
Gain V MSB, blanking level
CCR, blanking level VBI
Null
(1)
CCRS1
CCRS0
BLNVB5
BLNVB4
BLNVB3
BLNVB2
BLNVB1
BLNVB0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Standard control
Burst amplitude
Subcarrier 0
DOWND
RTCE
DOWNA
BSTA6
FSC06
FSC14
FSC22
FSC30
L21O06
L21O16
L21E06
INPI
YGS
SCBW
BSTA2
FSC02
FSC10
FSC18
FSC26
L21O02
L21O12
L21E02
PAL
FISE
BSTA5
FSC05
FSC13
FSC21
FSC29
L21O05
L21O15
L21E05
BSTA4
FSC04
FSC12
FSC20
FSC28
L21O04
L21O14
L21E04
BSTA3
FSC03
FSC11
FSC19
FSC27
L21O03
L21O13
L21E03
BSTA1
FSC01
FSC09
FSC17
FSC25
L21O01
L21O11
L21E01
BSTA0
FSC00
FSC08
FSC16
FSC24
L21O00
L21O10
L21E00
FSC07
FSC15
FSC23
FSC31
L21O07
L21O17
L21E07
Subcarrier 1
Subcarrier 2
Subcarrier 3
Line 21 odd 0
Line 21 odd 1
Line 21 even 0
Line 21 even 1
Null
L21E17
L21E16
L21E15
L21E14
L21E13
L21E12
L21E11
L21E10
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Trigger control
Trigger control
Multi control
HTRIG7
HTRIG10
NVTRIG
CCEN1
HTRIG6
HTRIG9
BLCKON
CCEN0
HTRIG5
HTRIG8
PHRES1
TTXEN
HTRIG4
VTRIG4
PHRES0
SCCLN4
HTRIG3
VTRIG3
LDEL1
HTRIG2
VTRIG2
LDEL0
HTRIG1
VTRIG1
FLC1
HTRIG0
VTRIG0
FLC0
Closed Caption, teletext enable
SCCLN3
ADWHS3
SCCLN2
ADWHS2
SCCLN1
SCCLN0
Active display window horizontal
start
ADWHS7
ADWHS6 ADWHS5 ADWHS4
ADWHE6 ADWHE5 ADWHE4
ADWHE10 ADWHE9 ADWHE8
ADWHS1 ADWHS0
Active display window horizontal
end
71
ADWHE7
ADWHE3
ADWHE2
ADWHE1 ADWHE0
(1)
(1)
MSBs ADWH
72
73
74
75
76
77
78
ADWHS10 ADWHS9 ADWHS8
TTX request horizontal start
TTX request horizontal delay
CSYNC advance
TTXHS7
TTXHS6
TTXHS5
TTXHS4
TTXHS3
TTXHD3
TTXHS2
TTXHS1
TTXHS0
(1)
(1)
(1)
(1)
TTXHD2
TTXHD1
TTXHD0
(1)
(1)
(1)
CSYNCA4 CSYNCA3 CSYNCA2 CSYNCA1 CSYNCA0
TTX odd request vertical start
TTX odd request vertical end
TTX even request vertical start
TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0
TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0
TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0
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SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
TTX even request vertical end
First active line
Last active line
TTX mode, MSB vertical
Null
79
7A
7B
7C
7D
7E
7F
TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0
FAL7
LAL7
FAL6
LAL6
FAL5
LAL5
FAL4
LAL4
FAL3
LAL3
FAL2
LAL2
FAL1
LAL1
FAL0
LAL0
TTX60
LAL8
TTXO
FAL8
TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Disable TTX line
Disable TTX line
FIFO status (read only)
Pixel clock 0
LINE12
LINE11
LINE10
LINE9
LINE8
LINE16
IFERR
PCL03
PCL11
PCL19
PCLE1
LINE7
LINE15
BFERR
PCL02
PCL10
PCL18
PCLE0
LINE6
LINE14
OVFL
LINE5
LINE13
UDFL
LINE20
LINE19
LINE18
LINE17
(1)
(1)
(1)
(1)
80
81
PCL07
PCL15
PCL23
DCLK
PCL06
PCL14
PCL22
PCL05
PCL13
PCL21
PCL04
PCL12
PCL20
PCL01
PCL09
PCL17
PCLI1
PCL00
PCL08
PCL16
PCLI0
Pixel clock 1
82
Pixel clock 2
83
Pixel clock control
FIFO control
84
PCLSY
IFRA
IFBP
(1)
(1)
(1)
85
EIDIV
FILI3
FILI2
FILI1
FILI0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Null
86 to 8F
90
Horizontal offset
Pixel number
XOFS7
XPIX7
YOFSO7
YOFSE7
YOFSE9
YPIX7
EFS
XOFS6
XPIX6
XOFS5
XPIX5
XOFS4
XPIX4
YOFSO4
YOFSE4
YOFSO8
YPIX4
ILC
XOFS3
XPIX3
YOFSO3
YOFSE3
XPIX9
YPIX3
YFIL
XOFS2
XPIX2
XOFS1
XPIX1
XOFS0
XPIX0
91
Vertical offset odd
Vertical offset even
MSBs
92
YOFSO6
YOFSE6
YOFSE8
YPIX6
YOFSO5
YOFSE5
YOFSO9
YPIX5
YOFSO2
YOFSE2
XPIX8
YOFSO1
YOFSE1
XOFS9
YPIX1
YOFSO0
YOFSE0
XOFS8
YPIX0
93
94
Line number
95
YPIX2
(1)
Scaler CTRL, MCB YPIX
Sync control
96
PCBN
SLAVE
OFS
YPIX9
YPIX8
97
HFS
VFS
PFS
OVS
PVS
OHS
PHS
Line length
98
HLEN7
IDEL3
HLEN6
IDEL2
HLEN5
IDEL1
HLEN4
IDEL0
XINC4
YINC4
YINC8
HLEN3
HLEN11
XINC3
YINC3
XINC11
HLEN2
HLEN10
XINC2
YINC2
XINC10
HLEN1
HLEN9
XINC1
YINC1
XINC9
HLEN0
HLEN8
XINC0
YINC0
XINC8
Input delay, MSB line length
Horizontal increment
Vertical increment
99
9A
9B
9C
XINC7
YINC7
YINC11
XINC6
YINC6
YINC10
XINC5
YINC5
YINC9
MSBs vertical and horizontal
increment
Weighting factor odd
Weighting factor even
Weighting factor MSB
Vertical line skip
9D
9E
9F
A0
YIWGTO7 YIWGTO6 YIWGTO5 YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTO0
YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE0
YIWGTE11 YIWGTE10 YIWGTE9 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YIWGTO8
YSKIP7
YSKIP6
YSKIP5
YSKIP4
YSKIP3
YSKIP2
YSKIP1
YSKIP0
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SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
(1)
(1)
(1)
Blank enable for NI-bypass,
vertical line skip MSB
A1
BLEN
YSKIP11
YSKIP10
YSKIP9
YSKIP8
Border colour Y
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
BCY7
BCU7
BCV7
BCY6
BCU6
BCV6
BCY5
BCU5
BCV5
BCY4
BCU4
BCV4
BCY3
BCU3
BCV3
BCY2
BCU2
BCV2
BCY1
BCU1
BCV1
BCY0
BCU0
BCV0
Border colour U
Border colour V
HD sync line count array
HD sync line type array
HD sync line pattern array
HD sync value array
HD sync trigger state 1
HD sync trigger state 2
HD sync trigger state 3
HD sync trigger state 4
HD sync trigger phase x
RAM address (see Table 88)
RAM address (see Table 90)
RAM address (see Table 92)
RAM address (see Table 94)
HLCT7
HLCT6
HLCPT2
HDCT6
HEPT2
HLCT5
HLCPT1
HDCT5
HEPT1
HLCT4
HLCPT0
HDCT4
HEPT0
HLCT3
HLCT2
HLCT1
HLCT9
HDCT1
HDCT9
HTX1
HLCT0
HLCT8
HDCT0
HDCT8
HTX0
HLCPT3
HLPPT1
HLPPT0
HDCT7
HDCT3
HDCT2
(1)
(1)
(1)
HTX7
(1)
HTX6
(1)
HTX5
(1)
HTX4
(1)
HTX3
HTX2
HTX11
HTX10
HTX9
HTX8
HD sync trigger phase y
HTY7
(1)
HTY6
(1)
HTY5
(1)
HTY4
(1)
HTY3
(1)
HTY2
(1)
HTY1
HTY0
HTY9
HTY8
(1)
(1)
(1)
(1)
HD output control
HDSYE
CC1R3
CC1G3
CC1B3
CC2R3
CC2G3
CC2B3
AUXR3
AUXG3
AUXB3
XCP3
HDTC
CC1R2
CC1G2
CC1B2
CC2R2
CC2G2
CC2B2
AUXR2
AUXG2
AUXB2
XCP2
HDGY
CC1R1
CC1G1
CC1B1
CC2R1
CC2G1
CC2B1
AUXR1
AUXG1
AUXB1
XCP1
HDIP
Cursor colour 1 R
CC1R7
CC1G7
CC1B7
CC2R7
CC2G7
CC2B7
AUXR7
AUXG7
AUXB7
XCP7
CC1R6
CC1G6
CC1B6
CC2R6
CC2G6
CC2B6
AUXR6
AUXG6
AUXB6
XCP6
CC1R5
CC1G5
CC1B5
CC2R5
CC2G5
CC2B5
AUXR5
AUXG5
AUXB5
XCP5
CC1R4
CC1G4
CC1B4
CC2R4
CC2G4
CC2B4
AUXR4
AUXG4
AUXB4
XCP4
CC1R0
CC1G0
CC1B0
CC2R0
CC2G0
CC2B0
AUXR0
AUXG0
AUXB0
XCP0
Cursor colour 1 G
Cursor colour 1 B
Cursor colour 2 R
Cursor colour 2 G
Cursor colour 2 B
Auxiliary cursor colour R
Auxiliary cursor colour G
Auxiliary cursor colour B
Horizontal cursor position
Horizontal hot spot, MSB XCP
Vertical cursor position
Vertical hot spot, MSB YCP
XHS4
XHS3
XHS2
XHS1
XHS0
XCP10
XCP9
XCP8
YCP7
YCP6
YCP5
YCP4
YCP3
YCP2
(1)
YCP1
YCP0
YHS4
YHS3
YHS2
YHS1
YHS0
YCP9
YCP8
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SUB
REGISTER FUNCTION
Input path control
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
FD
FE
FF
LUTOFF
CMODE
LUTL
IF2
IF1
IF0
MATOFF
DFOFF
Cursor bit map
RAM address (see Table 109)
RAM address (see Table 110)
Colour look-up table
Note
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.23 I2C-bus format
Table 16 I2C-bus write access to control registers; see Table 22
S
1 0 0 0 1 0 0 0
A
SUBADDRESS
A
DATA 0
A
--------
DATA n
A
P
Table 17 I2C-bus write access to the HD line count array (subaddress D0H); see Table 22
1 0 0 0 1 0 0 0 D0H RAM ADDRESS DATA 00 DATA 01
S
A
A
A
A
A
-------- DATA n
A
P
Table 18 I2C-bus write access to cursor bit map (subaddress FEH); see Table 22
1 0 0 0 1 0 0 0 FEH RAM ADDRESS DATA 0
S
A
A
A
A
--------
DATA n
A
P
P
P
Table 19 I2C-bus write access to colour look-up table (subaddress FFH); see Table 22
S
1 0 0 0 1 0 0 0
A
FFH
A
RAM ADDRESS
A
DATA 0R
A
A
DATA 0G
A
DATA 0B
A
--------
Table 20 I2C-bus read access to control registers; see Table 22
1 0 0 0 1 0 0 0 SUBADDRESS Sr 1 0 0 0 1 0 0 1
S
A
A
DATA 0 Am -------- DATA n Am
Table 21 I2C-bus read access to cursor bit map or colour LUT; see Table 22
S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
or
FFH
Table 22 Explanations of Tables 16 to 21
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
slave address
1 0 0 0 1 0 0 X; note 1
A
acknowledge generated by the slave
Am
acknowledge generated by the master
subaddress byte
SUBADDRESS; note 2
DATA
data byte
--------
continued data bytes and acknowledges
STOP condition
P
RAM ADDRESS
start address for RAM access
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
2004 Mar 04
28
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.24 Slave receiver
Table 23 Subaddress 16H
DATA BYTE
DESCRIPTION
DACF
output level adjustment fine in 1% steps for all DACs; default after reset is 00H; see Table 24
Table 24 Fine adjustment of DAC output voltage
BINARY
GAIN (%)
0111
0110
0101
0100
0011
0010
0001
0000
1000
1001
1010
1011
1100
1101
1110
1111
7
6
5
4
3
2
1
0
0
−1
−2
−3
−4
−5
−6
−7
Table 25 Subaddresses 17H to 19H
DATA BYTE
DESCRIPTION
RDACC
GDACC
BDACC
output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal
00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion
output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal
00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion
output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal
00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion
Table 26 Subaddress 1AH
DATA BYTE
DESCRIPTION
monitor sense mode threshold for DAC output voltage, should be set to 70
MSMT
2004 Mar 04
29
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 27 Subaddress 1BH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
MSM
MSA
0
1
0
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
monitor sense mode on
automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default
after reset
1
0
1
0
1
0
1
0
1
automatic monitor sense mode on if MSM = 0
MSOE
pin TVD is active
pin TVD is 3-state; default after reset
RCOMP
(read only)
check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded
check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded
check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded
check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded
check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded
check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
GCOMP
(read only)
BCOMP
(read only)
Table 28 Subaddresses 26H and 27H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
WSS
−
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
WSSON
0
1
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
Table 29 Subaddress 28H
LOGIC
DATA BYTE
DESCRIPTION
REMARKS
LEVEL
BS
−
starting point of burst in clock cycles
PAL: BS = 33 (21H); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin FSVGC tied to LOW
2004 Mar 04
30
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 30 Subaddress 29H
LOGIC
DATA BYTE
DESCRIPTION
REMARKS
LEVEL
SRES
BE
0
1
−
pin TTX_SRES accepts a teletext bit
stream (TTX)
default after reset
pin TTX_SRES accepts a sync reset input a HIGH impulse resets synchronization of the
(SRES)
encoder (first field, first line)
ending point of burst in clock cycles
PAL: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to LOW
Table 31 Subaddresses 2AH to 2CH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
CG
−
LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.
CGEN
0
1
copy generation data output is disabled; default after reset
copy generation data output is enabled
Table 32 Subaddress 2DH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
VBSEN
0
pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS
signal (CVBSEN1 = 1)
1
0
pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset
CVBSEN1
pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal;
default after reset
1
0
1
0
1
pin GREEN_VBS_CVBS provides a CVBS signal
CVBSEN0
CEN
pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (CB) signal
pin BLUE_CB_CVBS provides a CVBS signal; default after reset
pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (CR) signal
pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for
S-video; default after reset
ENCOFF
CLK2EN
0
1
0
1
encoder is active; default after reset
encoder bypass, DACs are provided with RGB signal after cursor insertion block
pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ)
pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default
after reset
CVBSEN2
0
1
pin RED_CR_C_CVBS provides a signal according to CEN; default after reset
pin RED_CR_C_CVBS provides a CVBS signal
2004 Mar 04
31
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 33 Subaddress 37H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
YUPSC
0
1
−
normal operation of the vertical scaler; default after reset
vertical upscaling is enabled
YFIL
controls the vertical interpolation filter, see Table 34; the filter is not available if
YUPSC = 1
CZOOM
0
1
0
1
0
1
normal operation of the cursor generator; default after reset
the cursor will be zoomed by a factor of 2 in both directions
expected input level swing is 16 to 235 (8-bit RGB); default after reset
expected input level swing is 0 to 255 (8-bit RGB)
IGAIN
XINT
no horizontal interpolation filter; default after reset
interpolation filter for horizontal upscaling is active
Table 34 Logic levels and function of YFIL
DATA BYTE
DESCRIPTION
YFIL1
YFIL0
0
0
1
1
0
1
0
1
no filter active; default after reset
filter is inserted before vertical scaling
filter is inserted after vertical scaling; YSKIP should be logic 0
reserved
Table 35 Subaddresses 38H and 39H
DATA BYTE
DESCRIPTION
GY4 to GY0
Gain luminance of RGB (CR, Yand CB) output, ranging from (1 − 16⁄32) to (1 + 15⁄32).
Suggested nominal value = 0, depending on external application.
GCD4 to GCD0
Gain colour difference of RGB (CR, Yand CB) output, ranging from
(1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = 0, depending on external
application.
2004 Mar 04
32
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 36 Subaddress 3AH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
CBENB
SYNTV
0
1
0
data from input ports is encoded
colour bar with fixed colours is encoded
in slave mode, the encoder is only synchronized at the beginning of an odd field; default
after reset
1
0
in slave mode, the encoder receives a vertical sync signal
SYMP
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
1
0
1
0
horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port
Y-CB-CR to RGB dematrix is active; default after reset
DEMOFF
CSYNC
Y-CB-CR to RGB dematrix is bypassed
pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output
(at PIXCLK)
1
pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL
clock)
Y2C
0
1
0
1
input luminance data is twos complement from PD input port
input luminance data is straight binary from PD input port; default after reset
input colour difference data is twos complement from PD input port
input colour difference data is straight binary from PD input port; default after reset
UV2C
Table 37 Subaddress 54H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
VPSEN
GPVAL
GPEN
EDGE
SLOT
0
1
0
1
0
1
0
1
0
1
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
pin VSM provides a LOW level if GPEN = 1
pin VSM provides a HIGH level if GPEN = 1
pin VSM provides a vertical sync for a monitor; default after reset
pin VSM provides a constant signal according to GPVAL
input data is sampled with inverse clock edges
input data is sampled with the clock edges specified in Tables 8 to 13; default after reset
normal assignment of the input data to the clock edge; default after reset
correct time misalignment due to inverted assignment of input data to the clock edge
Table 38 Subaddresses 55H to 59H
DATA BYTE
DESCRIPTION
REMARKS
VPS5
fifth byte of video programming system data
eleventh byte of video programming system data
twelfth byte of video programming system data
thirteenth byte of video programming system data
fourteenth byte of video programming system data
in line 16; LSB first; all other bytes are not
relevant for VPS
VPS11
VPS12
VPS13
VPS14
2004 Mar 04
33
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 39 Subaddress 5AH; note 1
DATA BYTE
DESCRIPTION
VALUE
6BH
RESULT
CHPS
phase of encoded colour subcarrier
(including burst) relative to horizontal
sync; can be adjusted in steps of
360/256 degrees
PAL B/G and data from input ports in master mode
PAL B/G and data from look-up table
16H
25H
NTSC M and data from input ports in master mode
NTSC M and data from look-up table
46H
Note
1. The default after reset is 00H.
Table 40 Subaddresses 5BH and 5DH
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINU
variable gain for
CB signal; input
representation in
accordance with
“ITU-R BT.601”
white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 118 (76H)
output subcarrier of U contribution = nominal
white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
Table 41 Subaddresses 5CH and 5EH
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINV
variable gain for
CR signal; input
representation in
accordance with
“ITU-R BT.601”
white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 165 (A5H)
output subcarrier of V contribution = nominal
white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
Table 42 Subaddress 5DH
DATA BYTE
DESCRIPTION
variable black level;
CONDITIONS
REMARKS
BLCKL
white-to-sync = 140 IRE; recommended value: BLCKL = 58 (3AH)
input representation note 1
in accordance with
BLCKL = 0; note 1
output black level = 29 IRE
“ITU-R BT.601”
BLCKL = 63 (3FH); note 1 output black level = 49 IRE
white-to-sync = 143 IRE; recommended value: BLCKL = 51 (33H)
note 2
BLCKL = 0; note 2
output black level = 27 IRE
BLCKL = 63 (3FH); note 2 output black level = 47 IRE
Notes
1. Output black level/IRE = BLCKL × 2/6.29 + 28.9.
2. Output black level/IRE = BLCKL × 2/6.18 + 26.5.
2004 Mar 04
34
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 43 Subaddress 5EH
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLNNL
variable blanking level
white-to-sync = 140 IRE;
note 1
recommended value: BLNNL = 46 (2EH)
BLNNL = 0; note 1
output blanking level = 25 IRE
BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE
white-to-sync = 143 IRE;
note 2
recommended value: BLNNL = 53 (35H)
BLNNL = 0; note 2
output blanking level = 26 IRE
BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE
Notes
1. Output black level/IRE = BLNNL × 2/6.29 + 25.4.
2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H.
Table 44 Subaddress 5FH
DATA BYTE
CCRS
DESCRIPTION
select cross-colour reduction filter in luminance; see Table 45
BLNVB
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 45 Logic levels and function of CCRS
CCRS1
CCRS0
DESCRIPTION
0
0
1
1
0
1
0
1
no cross-colour reduction; for overall transfer characteristic of luminance see Fig.6
cross-colour reduction #1 active; for overall transfer characteristic see Fig.6
cross-colour reduction #2 active; for overall transfer characteristic see Fig.6
cross-colour reduction #3 active; for overall transfer characteristic see Fig.6
2004 Mar 04
35
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 46 Subaddress 61H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
DOWND
DOWNA
INPI
0
1
0
1
0
1
0
1
0
digital core in normal operational mode; default after reset
digital core in sleep mode and is reactivated with an I2C-bus address
DACs in normal operational mode; default after reset
DACs in power-down mode
PAL switch phase is nominal; default after reset
PAL switch is inverted compared to nominal if RTCE = 1
luminance gain for white − black 100 IRE
YGS
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
SCBW
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 4 and 5)
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 4 and 5); default after reset
PAL
0
1
0
1
NTSC encoding (non-alternating V component)
PAL encoding (alternating V component)
864 total pixel clocks per line
FISE
858 total pixel clocks per line
Table 47 Subaddress 62H
LOGIC
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
LEVEL
RTCE
BSTA
0
1
no real-time control of generated subcarrier frequency; default after reset
real-time control of generated subcarrier frequency through a Philips video decoder; for a
specification of the RTC protocol see document “RTC Functional Description”, available on
request
−
amplitude of colour burst; input
white-to-black = 92.5 IRE;
recommended value:
representation in accordance with burst = 40 IRE; NTSC encoding BSTA = 63 (3FH)
“ITU-R BT.601”
BSTA = 0 to 2.02 × nominal
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
recommended value:
BSTA = 45 (2DH)
BSTA = 0 to 2.82 × nominal
white-to-black = 100 IRE;
recommended value:
burst = 43 IRE; NTSC encoding BSTA = 67 (43H)
BSTA = 0 to 1.90 × nominal
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
recommended value:
BSTA = 47 (2FH);
default after reset
BSTA = 0 to 3.02 × nominal
2004 Mar 04
36
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 48 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency (in multiples
of line frequency); fllc = clock frequency
(in multiples of line frequency)
FSC3 = most significant byte;
FSC0 = least significant byte
f
FSC = round fsc × 232
;
-------
fllc
note 1
Note
1. Examples:
a) NTSC M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
Table 49 Subaddresses 67H to 6AH
DATA BYTE
DESCRIPTION
REMARKS
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
LSBs of the respective bytes are encoded immediately
after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the
definition of line 21 encoding format.
Table 50 Subaddresses 6CH and 6DH
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to chip-internal horizontal input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; the default value is 0
Table 51 Subaddress 6DH
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
Table 52 Subaddress 6EH
LOGIC
DATA BYTE
DESCRIPTION
values of the VTRIG register are positive
LEVEL
NVTRIG
BLCKON
0
1
0
1
−
−
−
values of the VTRIG register are negative
encoder in normal operation mode; default after reset
output signal is forced to blanking level
PHRES
LDEL
FLC
selects the phase reset mode of the colour subcarrier generator; see Table 53
selects the delay on luminance path with reference to chrominance path; see Table 54
field length control; see Table 55
2004 Mar 04
37
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 53 Logic levels and function of PHRES
DATA BYTE
DESCRIPTION
DESCRIPTION
DESCRIPTION
PHRES1
PHRES0
0
0
1
1
0
1
0
1
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
Table 54 Logic levels and function of LDEL
DATA BYTE
LDEL1
LDEL0
0
0
1
1
0
1
0
1
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
Table 55 Logic levels and function of FLC
DATA BYTE
FLC1
FLC0
0
0
1
1
0
1
0
1
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 56 Subaddress 6FH
DATA
BYTE
LOGIC
LEVEL
DESCRIPTION
CCEN
−
0
1
−
enables individual line 21 encoding; see Table 57
disables teletext insertion; default after reset
enables teletext insertion
TTXEN
SCCLN
selects the actual line, where Closed Caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 57 Logic levels and function of CCEN
DATA BYTE
DESCRIPTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
line 21 encoding off; default after reset
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
2004 Mar 04
38
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 58 Subaddresses 70H to 72H
DATA BYTE
DESCRIPTION
ADWHS
active display window horizontal start; defines the start of the active TV display portion after the border
colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
ADWHE
active display window horizontal end; defines the end of the active TV display portion before the
border colour
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
Table 59 Subaddress 73H
DATA BYTE
DESCRIPTION
REMARKS
TTXHS
start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0);
see Fig.15
TTXHS = 42H; is default after
reset if strapped to PAL
TTXHS = 54H; is default after
reset if strapped to NTSC
Table 60 Subaddress 74H
DATA BYTE
DESCRIPTION
indicates the delay in clock cycles between rising edge of TTXRQ
REMARKS
TTXHD
minimum value: TTXHD = 2;
output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at is default after reset
pin TTX_SRES
Table 61 Subaddress 75H
DATA BYTE
DESCRIPTION
advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks
CSYNCA
Table 62 Subaddresses 76H, 77H and 7CH
DATA BYTE
DESCRIPTION
REMARKS
TTXOVS
TTXOVE
first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in odd field
TTXOVS = 05H; is default
after reset if strapped to PAL
TTXOVS = 06H; is default
after reset if strapped to
NTSC
line = (TTXOVS + 4) for M-systems
line = (TTXOVS + 1) for other systems
last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in odd field
TTXOVE = 16H; is default
after reset if strapped to PAL
TTXOVE = 10H; is default
after reset if strapped to
NTSC
line = (TTXOVE + 3) for M-systems
line = TTXOVE for other systems
2004 Mar 04
39
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 63 Subaddresses 78H, 79H and 7CH
DATA BYTE
DESCRIPTION
REMARKS
TTXEVS
TTXEVE
first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
TTXEVS = 04H; is default
after reset if strapped to PAL
TTXEVS = 05H; is default
after reset if strapped to
NTSC
line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems
last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
TTXEVE = 16H; is default
after reset if strapped to PAL
TTXEVE = 10H; is default
after reset if strapped to
NTSC
line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems
Table 64 Subaddresses 7AH to 7CH
DATA BYTE
DESCRIPTION
FAL
first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M-systems and LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
Table 65 Subaddress 7CH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
TTX60
TTXO
0
1
0
enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
enables world standard teletext 60 Hz (FISE = 1)
new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is
requested (see Fig.15); default after reset
1
old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the
length of the window depends on the chosen teletext standard (see Fig.15)
Table 66 Subaddresses 7EH and 7FH
DATA BYTE
DESCRIPTION
LINE
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
Table 67 Subaddresses 81H to 83H
DATA BYTE
DESCRIPTION
PCL
defines the frequency of the synthesized pixel clock PIXCLKO;
PCL
fPIXCLK
=
× f
× 8 ; fXTAL = 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH;
XTAL
-----------
224
640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
2004 Mar 04
40
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 68 Subaddress 84H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
DCLK
0
pixel clock input is differential, pin PIXCLKI receives the inverted clock; default after
reset
1
0
1
0
1
0
1
−
−
pixel clock input is single ended, pin PIXCLKI has no function
pixel clock generator runs free; default after reset
pixel clock generator gets synchronized with the vertical sync
input FIFO gets reset explicitly at falling edge
PCLSY
IFRA
input FIFO gets reset every field; default after reset
input FIFO is active
IFBP
input FIFO is bypassed; default after reset
PCLE
PCLI
controls the divider for the external pixel clock; see Table 69
controls the divider for the internal pixel clock; see Table 70
Table 69 Logic levels and function of PCLE
DATA BYTE
DESCRIPTION
PCLE1
PCLE0
0
0
1
1
0
1
0
1
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2; default after reset
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
Table 70 Logic levels and function of PCLI
DATA BYTE
DESCRIPTION
divider ratio for internal PIXCLK is 1
PCLI1
PCLI0
0
0
1
1
0
1
0
1
divider ratio for internal PIXCLK is 2; default after reset
divider ratio for internal PIXCLK is 4
not allowed
Table 71 Subaddress 85H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
EIDIV
FILI
0
1
−
set to logic 0 if DVO compliant signals are applied; default after reset
set to logic 1 if non-DVO compliant signals are applied
threshold for FIFO internal transfers; nominal value is 8; default after reset
Table 72 Subaddresses 90H and 94H
DATA BYTE
DESCRIPTION
XOFS
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
2004 Mar 04
41
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 73 Subaddresses 91H and 94H
DATA BYTE
DESCRIPTION
XPIX
pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
Table 74 Subaddresses 92H and 94H
DATA BYTE
DESCRIPTION
YOFSO
vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 75 Subaddresses 93H and 94H
DATA BYTE
DESCRIPTION
YOFSE
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 76 Subaddresses 95H and 96H
DATA BYTE
DESCRIPTION
YPIX
defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE − YOFSO
Table 77 Subaddress 96H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
EFS
0
1
0
1
0
1
0
1
0
1
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7104H; SAA7105H is timing master to the graphics controller
the SAA7104H; SAA7105H is timing slave to the graphics controller
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
PCBN
SLAVE
ILC
YFIL
luminance sharpness booster enabled
2004 Mar 04
42
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 78 Subaddress 97H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
HFS
0
1
horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
VFS
0
1
vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
OFS
PFS
0
1
0
pin FSVGC is switched to input
pin FSVGC is switched to active output
polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1
polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
OVS
PVS
0
1
0
pin VSVGC is switched to input
pin VSVGC is switched to active output
polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1
polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
OHS
PHS
0
1
0
pin HSVGC is switched to input
pin HSVGC is switched to active output
polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1
polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
Table 79 Subaddresses 98H and 99H
DATA BYTE
DESCRIPTION
number of PIXCLKs
HLEN
horizontal length; HLEN =
– 1
----------------------------------------------------
line
Table 80 Subaddress 99H
DATA BYTE
DESCRIPTION
IDEL
input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received
valid pixel
2004 Mar 04
43
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 81 Subaddresses 9AH and 9CH
DATA BYTE
DESCRIPTION
XINC
number of output pixels
--------------------------------------------------------------
line
incremental fraction of the horizontal scaling engine; XINC =
× 4096
--------------------------------------------------------------
number of input pixels
----------------------------------------------------------
line
Table 82 Subaddresses 9BH and 9CH
DATA BYTE
DESCRIPTION
YINC
number of active output lines
----------------------------------------------------------------------------
number of active input lines
incremental fraction of the vertical scaling engine; YINC =
× 4096
Table 83 Subaddresses 9DH and 9FH
DATA BYTE
DESCRIPTION
weighting factor for the first line of the odd field; YIWGTO =
YIWGTO
YINC
2
+ 2048
-------------
Table 84 Subaddresses 9EH and 9FH
DATA BYTE
DESCRIPTION
YIWGTE
YINC – YSKIP
-------------------------------------
2
weighting factor for the first line of the even field; YIWGTE =
Table 85 Subaddresses A0H and A1H
DATA BYTE
DESCRIPTION
YSKIP
vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective;
YSKIP = 4095: anti-flicker filter switched off
Table 86 Subaddress A1H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
BLEN
0
1
no internal blanking for non-interlaced graphics in bypass mode; default after reset
forced internal blanking for non-interlaced graphics in bypass mode
Table 87 Subaddresses A2H to A4H
DATA BYTE
DESCRIPTION
luminance and colour difference portion of border colour in underscan area
BCY, BCU
and BCV
2004 Mar 04
44
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 88 Subaddress D0H
DATA BYTE
DESCRIPTION
HLCA
RAM start address for the HD sync line count array; the byte following subaddress D0 points to the
first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line count array entry consists of 2 bytes; see Table 89. The array has
15 entries.
HLC
HLT
HD line counter. The system will repeat the pattern described in ‘HLT’ HLC times and then start with
the next entry in line count array.
HD line type pointer. If not 0, the value points into the line type array, index HLT − 1 with the
description of the current line. 0 means the entry is not used.
Table 89 Layout of the data bytes in the line count array
BYTE
DESCRIPTION
HLC4 HLC3
HLT0
0
1
HLC7
HLT3
HLC6
HLT2
HLC5
HLT1
HLC2
0
HLC1
HLC9
HLC0
HLC8
0
Table 90 Subaddress D1H
DATA BYTE
DESCRIPTION
HLTA
RAM start address for the HD sync line type array; the byte following subaddress D1 points to the first
cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line type array entry consists of 4 bytes; see Table 91. The array has
15 entries.
HLP
HD line type; if not 0, the value points into the line pattern array. The index used is HLP − 1. It consists
of value-duration pairs. Each entry consists of 8 pointers, used from index 0 to 7. The value 0 means
that the entry is not used.
Table 91 Layout of the data bytes in the line type array
BYTE
DESCRIPTION
0
1
2
3
0
0
0
0
HLP12
HLP32
HLP52
HLP72
HLP11
HLP31
HLP51
HLP71
HLP10
0
0
0
0
HLP02
HLP22
HLP42
HLP62
HLP01
HLP21
HLP41
HLP61
HLP00
HLP20
HLP40
HLP60
HLP30
HLP50
HLP70
Table 92 Subaddress D2H
DATA BYTE
DESCRIPTION
HLPA
RAM start address for the HD sync line pattern array; the byte following subaddress D2 points to the
first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes;
see Table 93. The array has 7 entries.
HPD
HPV
HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the corresponding value
HPV is added to the HD output signal. If 0, this entry will be skipped.
HD pattern value pointer. This gives the index in the HD value array containing the level to be inserted
into the HD output path. If the MSB of HPV is logic 1, the value will only be inserted into the Y/GREEN
channel of the HD data path, the other channels remain unchanged.
2004 Mar 04
45
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 93 Layout of the data bytes in the line pattern array
BYTE
DESCRIPTION
HPD04 HPD03
0
1
2
3
4
5
6
7
HPD07
HPV03
HPD17
HPV13
HPD27
HPV23
HPD37
HPV33
HPD06
HPV02
HPD16
HPV12
HPD26
HPV22
HPD36
HPV32
HPD05
HPV01
HPD14
HPV11
HPD25
HPV21
HPD35
HPV31
HPD02
HPD01
HPD09
HPD11
HPD19
HPD21
HPD29
HPD31
HPD39
HPD00
HPD08
HPD10
HPD18
HPD20
HPD28
HPD30
HPD38
HPV00
HPD14
HPV10
HPD24
HPV20
HPD34
HPV30
0
0
HPD13
HPD12
0
HPD23
0
0
HPD22
0
HPD33
0
HPD32
0
Table 94 Subaddress D3H
DATA BYTE
DESCRIPTION
HPVA
RAM start address for the HD sync value array; the byte following subaddress D3 points to the first
cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line pattern array entry consists of 2 bytes. The array has 8 entries.
HPVE
HHS
HVS
HD pattern value entry. The HD path will insert a level of (HPV + 52) × 0.66 IRE into the data path.
The value is signed 8-bits wide; see Table 95.
HD horizontal sync. If the HD engine is active, this value will be provided at pin HSM_CSYNC;
see Table 95.
HD vertical sync. If the HD engine is active, this value will be provided at pin VSM; see Table 95.
Table 95 Layout of the data bytes in the value array
BYTE
DESCRIPTION
HPVE4 HPVE3
0
1
HPVE7
0
HPVE6
0
HPVE5
0
HPVE2
0
HPVE1
HVS
HPVE0
HHS
0
0
Table 96 Subaddresses D4H and D5H
DATA BYTE
DESCRIPTION
HLCT
state of the HD line counter after trigger, note that it counts backwards
state of the HD line type pointer after trigger
HLCPT
HLPPT
state of the HD pattern pointer after trigger
Table 97 Subaddresses D6H and D7H
DATA BYTE
DESCRIPTION
HDCT
HEPT
state of the HD duration counter after trigger, note that it counts backwards
state of the HD event type pointer in the line type array after trigger
Table 98 Subaddresses D8H and D9H
DATA BYTE
DESCRIPTION
horizontal trigger phase for the HD sync engine in pixel clocks
HTX
2004 Mar 04
46
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 99 Subaddresses DAH and DBH
DATA BYTE
DESCRIPTION
vertical trigger phase for the HD sync engine in input lines
HTY
Table 100 Subaddress DCH
LOGIC
DATA BYTE
DESCRIPTION
the HD sync engine is off; default after reset
LEVEL
HDSYE
HDTC
HDGY
0
1
0
1
0
the HD sync engine is active
HD output path processes RGB; default after reset
HD output path processes YUV
gain in the HD output path is reduced, insertion of sync pulses is possible; default after
reset
1
0
1
full level swing at the input causes full level swing at the DACs in HD mode
interpolator for the colour difference signal in the HD output path is active; default after reset
interpolator for the colour difference signals in the HD output path is off
HDIP
Table 101 Subaddresses F0H to F2H
DATA BYTE
DESCRIPTION
CC1R, CC1G RED, GREEN and BLUE portion of first cursor colour
and CC1B
Table 102 Subaddresses F3H to F5H
DATA BYTE
DESCRIPTION
CC2R, CC2G RED, GREEN and BLUE portion of second cursor colour
and CC2B
Table 103 Subaddresses F6H to F8H
DATA BYTE
DESCRIPTION
AUXR, AUXG RED, GREEN and BLUE portion of auxiliary cursor colour
and AUXB
Table 104 Subaddresses F9H and FAH
DATA BYTE
DESCRIPTION
DESCRIPTION
XCP
horizontal cursor position
Table 105 Subaddress FAH
DATA BYTE
XHS
horizontal hot spot of cursor
2004 Mar 04
47
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Table 106 Subaddresses FBH and FCH
DATA BYTE
DESCRIPTION
DESCRIPTION
YCP
vertical cursor position
Table 107 Subaddress FCH
DATA BYTE
YHS
vertical hot spot of cursor
Table 108 Subaddress FDH
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
LUTOFF
CMODE
LUTL
0
1
0
1
0
1
0
1
2
3
4
colour look-up table is active
colour look-up table is bypassed
cursor mode; input colour will be inverted
auxiliary cursor colour will be inserted
LUT loading via input data stream is inactive
colour and cursor LUTs are loaded via input data stream
input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR
input format is 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB
input format is 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB
input format is 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR
IF
input format is 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock)
(in subaddresses 91H and 94H set XPIX = number of active pixels/line)
5
6
0
1
0
1
input format is 8-bit non-interlaced index colour
input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering)
RGB to CR-Y-CB matrix is active
MATOFF
DFOFF
RGB to CR-Y-CB matrix is bypassed
down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active
down formatter is bypassed
Table 109 Subaddress FEH
DATA BYTE
DESCRIPTION
CURSA
RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be
loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop
condition
Table 110 Subaddress FFH
DATA BYTE
DESCRIPTION
COLSA
RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be
loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop
condition
In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up.
2004 Mar 04 48
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
7.25 Slave transmitter
Table 111 Slave transmitter (slave address 89H)
DATA BYTE
D4 D3
VER0 CCRDO CCRDE
REGISTER
FUNCTION
SUBADDRESS
D7
D6
D5
D2
D1
D0
Status byte
Chip ID
00H
1CH
80H
VER2
CID7
0
VER1
CID6
0
0
CID2
0
FSEQ
CID1
O_E
CID0
UDFL
CID5
0
CID4
0
CID3
0
FIFO status
OVFL
Table 112 Subaddress 00H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
VER
−
version identification of the device: it will be changed with all versions of the IC that have
different programming models; current version is 101 binary
CCRDO
1
0
Closed Caption bytes of the odd field have been encoded
the bit is reset after information has been written to the subaddresses 67H and 68H; it is
set immediately after the data has been encoded
CCRDE
1
0
Closed Caption bytes of the even field have been encoded
the bit is reset after information has been written to the subaddresses 69H and 6AH; it is
set immediately after the data has been encoded
FSEQ
O_E
1
0
1
0
during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields)
not first field of a sequence
during even field
during odd field
Table 113 Subaddress 1CH
DATA BYTE
DESCRIPTION
CID
chip ID of SAA7104H = 04H; chip ID of SAA7105H = 05H
Table 114 Subaddress 80H
LOGIC
DATA BYTE
DESCRIPTION
LEVEL
IFERR
BFERR
OVFL
0
1
0
1
0
1
0
1
normal FIFO state
input FIFO overflow/underflow has occurred
normal FIFO state
buffer FIFO overflow, only if YUPSC = 1
no FIFO overflow
FIFO overflow has occurred; this bit is reset after this subaddress has been read
no FIFO underflow
UDFL
FIFO underflow has occurred; this bit is reset after this subaddress has been read
2004 Mar 04
49
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
MBE737
6
G
v
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 1.
MBE735
handbook, halfpage
2
G
v
(dB)
0
(1)
(2)
−2
−4
−6
0
0.4
0.8
1.2
1.6
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 2.
50
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
MGD672
6
G
v
(dB)
(4)
0
(2)
(3)
−6
−12
−18
(1)
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) CCRS1 = 0; CCRS) = 1.
(2) CCRS1 = 1; CCRS) = 0.
(3) CCRS1 = 1; CCRS) = 1.
(4) CCRS1 = 0; CCRS) = 0.
Fig.6 Luminance transfer characteristic 1 (excluding scaler).
MBE736
handbook, halfpage
1
G
v
(dB)
(1)
0
−1
−2
−3
−4
−5
0
2
4
6
f (MHz)
(1) CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 2(excluding scaler).
51
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
MGB708
6
G
v
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
Fig.8 Luminance transfer characteristic in RGB (excluding scaler).
MGB706
6
G
v
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
Fig.9 Colour difference transfer characteristic in RGB (excluding scaler).
52
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
8
BOUNDARY SCAN TEST
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all
supported; see Table 115. Details about the
JTAG BST-TEST can be found in the specification “IEEE
Std. 1149.1”. A file containing the detailed Boundary Scan
Description Language (BSDL) of the SAA7104H;
SAA7105H is available on request.
The SAA7104H; SAA7105H has built-in logic and
5 dedicated pins to support boundary scan testing which
allows board testing without special hardware (nails). The
SAA7104H; SAA7105H follows the “IEEE Std. 1149.1 -
Standard Test Access Port and Boundary-Scan
Architecture” set by the Joint Test Action Group (JTAG)
chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
Table 115 BST instructions supported by the SAA7104H; SAA7105H
INSTRUCTION
DESCRIPTION
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.
EXTEST
SAMPLE
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the
boundary scan register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary scan register is in external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer, part number and
version number.
INTEST
USER1
This optional instruction allows testing of the internal logic (no support for customer available).
This private instruction allows testing by the manufacturer (no support for customer available).
8.1
Initialization of boundary scan circuit
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between TDI and TDO of the IC.
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller, this code can subsequently be shifted
out. At board level this code can be used to verify
component manufacturer, type and version number. The
device identification register contains 32 bits, numbered
31 to 0, where bit 31 is the most significant bit (nearest to
TDI) and bit 0 is the least significant bit (nearest to TDO);
see Fig.10.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.
8.2
Device identification codes
A device identification register is specified in “IEEE Std.
1149.1b-1994”. It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and to determine the version number of the ICs
during field service.
2004 Mar 04
53
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
MSB
31
LSB
28 27
12 11
1
0
TDI
TDO
0101
1
0111000100000100
16-bit part number
00000010101
4-bit
version
code
11-bit manufacturer
identification
MHC568
a. SAA7104H.
MSB
LSB
31
28 27
12 11
1
0
TDI
TDO
0101
1
0111000100000101
00000010101
4-bit
version
code
16-bit part number
11-bit manufacturer
identification
MHC569
b. SAA7105H.
Fig.10 32 bits of identification code.
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and
grounded (0 V); all supply pins connected together.
SYMBOL
VDDD
VDDA
Vi(A)
PARAMETER
digital supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+4.6
UNIT
V
V
V
V
V
V
analog supply voltage
−0.5
−0.5
−0.5
−0.5
−0.5
+4.6
input voltage at analog inputs
+4.6
Vi(n)
input voltage at pins XTALI, SDA and SCL
input voltage at digital inputs or I/O pins
VDDD + 0.5
+4.6
Vi(D)
outputs in 3-state
outputs in 3-state;
note 1
+5.5
∆VSS
Tstg
voltage difference between VSSA(n) and VSSD(n)
storage temperature
−
100
mV
°C
°C
V
−65
0
+150
70
Tamb
Vesd
ambient temperature
electrostatic discharge voltage
human body model;
note 2
−
±2000
machine model;
note 3
−
±200
V
Notes
1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V.
2. Class 2 according to EIA/JESD22-114-B.
3. Class B according to EIA/JESD22-115-A.
2004 Mar 04
54
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
10 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
44(1)
K/W
Note
1. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and
ground pins must be connected to the power and ground layers directly. An ample copper area direct under the
SAA7104H; SAA7105H with a number of through-hole plating, which connect to the ground layer (four-layer board:
second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In
addition the usage of soldering glue with a high thermal conductance after curing is recommended.
11 CHARACTERISTICS
Tamb = 0 to 70 °C (typical values excluded); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
digital supply voltage
3.15
3.3
3.45
V
VDDD2
VDDD3
VDDD4
,
,
3.15
3.3
3.45
V
VDDD1
digital supply voltage (DVO)
1.045
1.425
1.71
2.375
3.135
1
1.1
1.5
1.8
2.5
3.3
110
175
1.155
1.575
1.89
V
V
V
2.625
3.465
115
V
V
IDDA
IDDD
analog supply current
digital supply current
note 1
note 2
mA
mA
1
200
Inputs
VIL
LOW-level input voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V −0.1
−
+0.2
V
or 2.5 V; note 3
VDDD1 = 3.3 V; note 3
−0.5
−0.5
−
−
+0.8
+0.8
V
V
pins RESET, TMS, TCK,
TRST and TDI
VIH
HIGH-level input voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
VDDD1 − 0.2 −
VDDD1 + 0.1 V
VDDD1 = 3.3 V; note 3
2
2
−
−
VDDD1 + 0.3 V
VDDD2 + 0.3 V
pins RESET, TMS, TCK,
TRST and TDI
ILI
Ci
input leakage current
input capacitance
−
−
−
−
−
−
−
−
10
10
10
10
µA
clocks
pF
pF
pF
data
I/Os at high-impedance
2004 Mar 04
55
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Outputs
VOL
LOW-level output voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
0
−
0.1
V
VDDD1 = 3.3 V; note 3
0
0
−
−
0.4
0.4
V
V
pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
VOH
HIGH-level output voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
VDDD1 − 0.1 −
VDDD1
V
VDDD1 = 3.3 V; note 3
2.4
2.4
−
−
VDDD1
VDDD2
V
V
pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
I2C-bus; pins SDA and SCL
VIL
VIH
Ii
LOW-level input voltage
−0.5
0.7VDDD2
−10
−
−
−
−
0.3VDDD2
V
HIGH-level input voltage
input current
VDDD2 + 0.3 V
Vi = LOW or HIGH
IOL = 3 mA
+10
0.4
µA
VOL
LOW-level output voltage
(pin SDA)
−
V
Io
output current
during acknowledge
3
−
−
mA
Clock timing; pins PIXCLKI and PIXCLKO
TPIXCLK
td(CLKD)
cycle time
note 4
note 5
12
−
−
−
−
ns
ns
delay from PIXCLKO to
PIXCLKI
−
δ
duty factor tHIGH/TPIXCLK
duty factor tHIGH/TCLKO2
rise time
note 4
output
note 4
note 4
40
40
−
50
50
−
60
%
%
ns
ns
60
tr
tf
1.5
1.5
fall time
−
−
Input timing
tSU;DAT
input data set-up time
input data hold time
input data set-up time
input data hold time
pins PD11 to PD0, RTCI
and TTX_SRES
2
−
−
−
−
−
−
−
−
ns
ns
ns
ns
tHD;DAT
tSU;DAT
tHD;DAT
pins PD11 to PD0, RTCI
and TTX_SRES
1.5
2
pins HSVGC, VSVGC
and FSVGC; note 6
pins HSVGC, VSVGC
and FSVGC; note 6
1.5
Crystal oscillator
fnom
nominal frequency
−
27
−
MHz
10−6
∆f/fnom
permissible deviation of
nominal frequency
note 7
−50
−
+50
2004 Mar 04
56
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CRYSTAL SPECIFICATION
Tamb
CL
ambient temperature
0
−
70
−
°C
pF
Ω
load capacitance
8
−
RS
C1
series resistance
−
−
80
1.8
4.2
motional capacitance (typical)
parallel capacitance (typical)
1.2
2.8
1.5
3.5
fF
C0
pF
Data and reference signal output timing
Co(L)
output load capacitance
8
−
−
40
pF
ns
to(h)(gfx)
output hold time to graphics
controller
pins HSVGC, VSVGC,
FSVGC and CBO
1.5
−
to(d)(gfx)
to(h)
output delay time to graphics
controller
pins HSVGC, VSVGC,
FSVGC and CBO
−
−
−
10
ns
ns
output hold time
pins TDO,
3
−
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
to(d)
output delay time
pins TDO,
−
−
25
ns
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
CVBS and RGB outputs
Vo(CVBS)(p-p) output voltage CVBS
(peak-to-peak value)
see Table 116
−
−
−
−
−
1.23
1
−
−
−
−
−
V
V
V
V
%
Vo(VBS)(p-p) output voltage VBS (S-video) see Table 116
(peak-to-peak value)
Vo(C)(p-p)
output voltage C (S-video)
(peak-to-peak value)
see Table 116
0.89
0.7
2
Vo(RGB)(p-p) output voltage R, G, B
(peak-to-peak value)
see Table 116
∆Vo
inequality of output signal
voltages
Ro(L)
BDAC
output load resistance
−
−
37.5
170
−
−
Ω
output signal bandwidth of
DACs
−3 dB; note 8
MHz
ILElf(DAC)
low frequency integral linearity
error of DACs
−
−
−
−
±3
±1
LSB
LSB
DLElf(DAC)
low frequency differential
linearity error of DACs
2004 Mar 04
57
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
Notes
1. Minimum value for I2C-bus bit DOWNA = 1.
2. Minimum value for I2C-bus bit DOWND = 1.
3. Levels refer to pins PD11 to PD0, PIXCLKI, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being
inputs or outputs directly connected to a graphics controller.
Input sensitivity is 1/2VDDD2 + 100 mV for HIGH and 1/2VDDD2 − 100 mV for LOW.
The reference voltage 1/2VDDD2 is generated on chip.
4. The data is for both input and output direction.
5. This parameter is arbitrary, if PIXCLKI is looped through the VGC.
6. Tested with programming IFBP = 1.
7. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
1
8. B–3 dB
=
with RL = 37.5 Ω and Cext = 20 pF (typical).
------------------------------------------------
2πRL(Cext + 5 pF)
2004 Mar 04
58
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
T
PIXCLK
t
HIGH
V
OH
PIXCLKO
0.5V
DDD1
V
OL
t
t
r
t
f
d(CLKD)
V
IH
PIXCLKI
0.5V
DDD1
V
IL
t
t
HD;DAT
HD;DAT
t
t
SU;DAT
SU;DAT
V
V
IH
IL
PDn
t
o(d)
t
o(h)
V
V
OH
OL
any output
MHC567
Fig.11 Input/output timing specification 1.
V
IH
LLC
0.5V
DDD1
V
IL
t
HD;DAT
t
SU;DAT
V
IH
RTCI,
TTX_SRES
V
IL
t
o(d)
t
o(h)
V
OH
OL
TTXRQ_XCLKO2
V
MHC685
Fig.12 Input/output timing specification 2.
59
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
HSVGC
CBO
PD
XOFS
IDEL
XPIX
HLEN
MHB905
Fig.13 Horizontal input timing.
HSVGC
VSVGC
CBO
YOFS
YPIX
MHB906
Fig.14 Vertical input timing.
60
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
11.1 Teletext timing
Time ti(TTXW) is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL),
296 teletext bits at a text data rate of 5.7272 Mbits/s (world
standard TTX) or 288 teletext bits at a text data rate of
5.7272 Mbits/s (NABTS). The insertion window is not
opened if the control bit TTXEN is zero.
Time tFD is the time needed to interpolate input data TTX
and insert it into the CVBS and VBS output signal, such
that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs
(NTSC) after the leading edge of the horizontal
synchronization pulse.
Time tPD is the pipeline delay time introduced by the
source that is gated by TTXRQ_XCLKO2 in order to
deliver TTX data. This delay is programmable by register
TTXHD. For every active HIGH state at output pin
TTXRQ_XCLKO2, a new teletext bit must be provided by
the source.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
It is essential to note that the two pins used for teletext
insertion must be configured for this purpose by the
correct I2C-bus register settings.
Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of the outgoing
horizontal synchronization pulse.
CVBS/Y
t
t
TTX
i(TTXW)
text bit #:
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TTX_SRES
t
t
FD
PD
TTXRQ_XCLKO2
MHB891
Fig.15 Teletext timing.
2004 Mar 04
61
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
12 APPLICATION INFORMATION
DVO
supply
+3.3 V digital
supply
+3.3 V analog
AGND
supply
0.1 µF
0.1 µF
1 nF
0.1 µF
DGND
DGND
AGND
10 pF
10 pF
use one capacitor
use one capacitor
0.1 µH
27 MHz
for each V
for each V
DDD
DDA
V
V
to V
V
to V
DDA1 DDA3
DDD1
DDD2
DDD4
XTALI
XTALO
6
12, 25, 53
51
50
43, 44, 52
39, 40
VSM, HSM_CSYNC
GREEN_VBS_CVBS
42
FLTR0
U
U
U
75 Ω
75 Ω
Y
AGND
AGND
AGND
RED_CR_C_CVBS
SAA7104H
SAA7105H
41
digital
inputs
and
FLTR1
75 Ω
75 Ω
C
outputs
AGND
AGND
AGND
BLUE_CB_CVBS
45
FLTR2
75 Ω
75 Ω
CVBS
7, 13, 26, 57
48
46
47
AGND
AGND
AGND
V
to V
V
RSET
DUMP
SSD1
SSD4
SSA
1 kΩ
12 Ω
AGND
MHC686
DGND
AGND
AGND
Fig.16 Application circuit.
62
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
C16
handbook, halfpage
120 pF
L2
L3
2.7 µH
2.7 µH
C10
C13
390 pF
560 pF
AGND
JP11
JP12
FIN
FOUT
FILTER 1
= byp.
ll act.
MHB912
Fig.17 FLTR0, FLTR1 and FLTR2 of Fig.16.
2004 Mar 04
63
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
SAA7104H
SAA7105H
SAA7104H
SAA7105H
51
50
XTALO
51
50
XTALO
XTALI
XTALI
27.00 MHz
27.00 MHz
4.7 µH
1 nF
18
pF
18
pF
39
pF
39
pF
MHC687
(1a) With 3rd-harmonic quartz.
Crystal load = 8 pF.
(1b) With fundamental quartz.
Crystal load = 20 pF.
SAA7104H
SAA7105H
SAA7104H
SAA7105H
51
50
XTALO
51
50
XTALO
XTALI
XTALI
R
s
27.00 MHz
n.c.
clock
MHC688
(2a) With direct clock.
(2b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator
is too high, a resistance Rs can be placed in series with the oscillator output XTALO.
Note: The decreased crystal amplitude results in a lower drive level but on the other hand
the jitter performance will decrease.
Fig.18 Oscillator application.
2004 Mar 04
64
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
12.1 Reconstruction filter
Tables 40 to 47 for example a standard PAL or NTSC
signal) conditions occupy different conversion ranges, as
Figure 17 shows a possible reconstruction filter for the
digital-to-analog converters. Due to its cut-off frequency of
6 MHz, it is not suitable for HDTV applications.
indicated in Table 116 for a 100
⁄100 colour bar signal.
By setting the reference currents of the DACs as shown in
Table 116, standard compliant amplitudes can be
12.2 Analog output voltages
achieved for all signal combinations; it is assumed that in
subaddress 16H, parameter DACF = 0000b, that means
the fine adjustment for all DACs in common is set to 0%.
The analog output voltages are dependent on the total
load (typical value 37.5 Ω), the digital gain parameters and
the I2C-bus settings of the DAC reference currents (analog
settings).
If S-video output is desired, the adjustment for the C
(chrominance subcarrier) output should be identical to the
one for VBS (luminance plus sync) output.
The digital output signals in front of the DACs under
nominal (nominal here stands for the settings given in
Table 116 Digital output signals conversion range
SET/OUT
CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE
RGB, BLACK-TO-WHITE
Digital settings
Digital output
Analog settings
Analog output
see Tables 40 to 47
1014
see Tables 40 to 47
see Table 35
881
876
e.g. B DAC = 1FH
1.23 V (p-p)
e.g. G DAC = 1BH
1.00 V (p-p)
e.g. R DAC = G DAC = B DAC = 0BH
0.70 V (p-p)
12.3 Suggestions for a board layout
Place the analog coupling (clamp) capacitors close to the
analog input pins. Place the analog termination resistors
close to the coupling capacitors.
Use separate ground planes for analog and digital ground.
Connect these planes only at one point directly under the
device, by using a 0 Ω resistor directly at the supply stage.
Use separate supply lines for analog and digital supply.
Place the supply decoupling capacitors close to the supply
pins.
Be careful of hidden layout capacitors around the crystal
application.
Use serial resistors in clock, sync and data lines, to avoid
clock or data reflection effects and to soften data energy.
Use Lbead (ferrite coil) in each digital supply line close to
the decoupling capacitors to minimize radiation energy
(EMC).
2004 Mar 04
65
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
13 PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
y
X
A
48
33
32
49
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w
p
M
pin 1 index
L
p
b
L
17
64
detail X
16
1
w
M
v
M
A
b
p
Z
e
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.75
0.10 2.55
0.45 0.23 14.1 14.1
0.30 0.13 13.9 13.9
17.45 17.45
16.95 16.95
1.03
0.73
1.2
0.8
1.2
0.8
mm
3
0.25
0.8
1.6
0.16 0.16 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-20
SOT393-1
134E07
MS-022
2004 Mar 04
66
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
14 SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
14.1 Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
14.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Mar 04
67
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
WAVE
REFLOW(2)
not suitable suitable
PACKAGE(1)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not recommended(7)
suitable
not suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Mar 04
68
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
15 DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16 DEFINITIONS
17 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 04
69
Philips Semiconductors
Product specification
Digital video encoder
SAA7104H; SAA7105H
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2004 Mar 04
70
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R21/01/pp71
Date of release: 2004 Mar 04
Document order number: 9397 750 11437
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