SAA7740 [NXP]
Digital Audio Processing IC DAPIC; 数字音频处理IC DAPIC
| 型号： | SAA7740 |
| 厂家： | 
NXP |
| 描述： | Digital Audio Processing IC DAPIC |
| 文件： | 总28页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7740H
Digital Audio Processing IC
(DAPIC)
1997 May 30
Product specification
Supersedes data of 1996 Mar 11
File under Integrated Circuits, IC01
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
FEATURES
Hardware
• Two digital inputs and two digital outputs in the I2S-bus
format (i.e. 4 audio channels)
• Independent input/output interfaces
• Slave input/output interfaces
• Slave processing
• External delay line processing for delays up to 1 second
• Reverberation with selectable reverberation time (up to
5 seconds) and energy
• I2C-bus microcontroller interface
• DC filtering at the inputs
• Three different surround sound programs to obtain a
spatial effect on 4 loudspeakers
• One programmable 2nd-order digital filter unit
• Passive DOLBY surround processing with the addition
of an external dynamic noise reduction IC
• Two multiply accumulate processor units
(24 × 16-bit/MAC)
• Karaoke processing
• DRAM interface and address computation unit for
external delay lines
• Dual 16th-order correction filtering
• Quad 8th-order correction filtering
• Digital volume and balance control
• On-chip coefficient and external delay line address
storage
• Hardware controlled soft mute via the MUTE pin
• Hardware controlled soft demute via the RST pin
• Operating ambient temperature; −40 to +85 °C.
• Soft controlled soft mute/demute via the microcontroller
interface
• Input switching matrix
• Output rear and front switching matrix.
Software
• 5-band parametric equalizer with selectable centre
frequency, slope setting and boost/cut gain settings
from −12 to +12 dB
APPLICATIONS
• Digital amplifiers
• Stereo width control from mono to stereo to spatial
stereo
• Audio combination sets
• Car audio systems
• TV audio channels.
• Stereo Hall-effects for field acoustics, such as concert
halls, with 8 coefficients and 8 delayed taps per channel
QUICK REFERENCE DATA
SYMBOL
VDD(tot)
IDD(tot)
fxtal
PARAMETER
total DC supply voltage
total DC supply current
input crystal frequency
total power dissipation
operating ambient temperature
CONDITIONS
all VDD pins
MIN.
4.5
TYP.
5.0
60
16.9344 23.0
MAX.
UNIT
5.5
V
fxtal = 16.9344 MHz
−
−
mA
MHz
W
12.288
−
Ptot
fxtal = 16.9344 MHz
0.3
−
Tamb
−40
−
+85
°C
ORDERING INFORMATION
TYPE
PACKAGE
DESCRIPTION
NUMBER
NAME
VERSION
SAA7740H
QFP64
plastic quad flat package; 64 leads (lead length 1.95 mm); body
SOT319-2
14 × 20 × 2.8 mm
1997 May 30
2
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
BLOCK DIAGRAM
V
V
SSX
CLKO
63
TSTCLK
45
TST1
47
TST2
48
TST3
DDX
60
XTAL
61
49
56
59
9, 13, 25, 40,
46, 50, 55
CLK1/XTAL1
XTAL2
OSCILLATOR
CLOCK
V
SS
COUNTER
7
7, 8, 26, 32,
38, 53, 54
62
SCCLK
V
DD
7
43
41
42
44
36
34
DIGITAL SIGNAL
PROCESSING CORE
2nd-ORDER FILTER
MAC
OFFSET FILTER
REGISTERS
DIWS
DI1D
DOWS
DO1D
DO2D
2
2
INPUT
BUFFER
OUTPUT
BUFFER
I S-BUS
I S-BUS
OUTPUT
35
37
DI2D
INPUT
DIBCK
DOBCK
MUTE
RAS
4
19
1
RST
ALL
10
17
18
14
CAS
64
CAS2
WE
16
16
7
OE
PROGRAM
COUNTER
PROGRAMMABLE
ROM
COEFFICIENT
31 to 27/24 to 21
RAM
A0 to A8
ADDRESS
CONTROL
UNIT
11, 12, 15, 16
D0 to D3
20
33
2
16
A8B
MUX
SCL
SDA
SAA7740H
2
I C-BUS
INTERFACE
3
51
52
MLC173
AS1
AS2
Fig.1 Block diagram.
1997 May 30
3
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
DO1D
DO2D
DOWS
DOBCK
VDD
34 digital audio output 1 (I2S-bus)
35 digital audio output 2 (I2S-bus)
36 digital audio input word select
37 digital audio input serial bit clock
38 supply voltage
RST
SCL
SDA
MUTE
n.c.
1
2
3
4
5
6
7
8
9
reset input (active LOW)
serial clock input (I2C-bus)
serial data input/output (I2C-bus)
mute input (active HIGH)
not connected
n.c.
39 not connected
n.c.
not connected
VSS
40 ground supply
VDD
supply voltage
DI1D
41 digital audio input 1 (I2S-bus)
42 digital audio input 2 (I2S-bus)
43 digital audio input word select
44 digital audio input serial bit clock
VDD
supply voltage
DI2D
VSS
ground supply
DIWS
DIBCK
TSTCLK
CAS
10 column address strobe (DRAM)
(active LOW)
D0
11 input/output data bus line 0 (DRAM)
12 input/output data bus line 1 (DRAM)
13 ground supply
45 clock input for test mode
(should be tied LOW)
D1
VSS
46 ground supply
VSS
OE
TST1
47 test pin input 1
(should be tied LOW)
14 output buffer enable (DRAM)
(active LOW)
TST2
TST3
48 test pin input 2
(should be tied LOW)
D2
15 input/output data bus line 2 (DRAM)
16 input/output data bus line 3 (DRAM)
D3
49 test pin input 3
(should be tied LOW)
CAS2
17 second column address strobe
(active LOW)
VSS
AS1
AS2
VDD
VDD
VSS
50 ground supply
WE
18 write enable (DRAM; active LOW)
51 address select input 1 (I2C-bus)
52 address select input 2 (I2C-bus)
53 supply voltage
RAS
19 row address strobe (DRAM;
active LOW)
A8B
20 inverse MSB address line output
(DRAM)
54 supply voltage
A8
21 address line output 8 (DRAM)
22 address line output 7 (DRAM)
23 address line output 6 (DRAM)
24 address line output 5 (DRAM)
25 ground supply
55 ground supply
A7
CLK1/
XTAL1
56 clock or crystal input
A6
n.c.
57 not connected
A5
n.c.
58 not connected
VSS
VDD
A4
XTAL2
VDDX
VSSX
SCCLK
59 crystal output 2
60 crystal supply voltage
61 crystal ground supply
26 supply voltage
27 address line output 4 (DRAM)
28 address line output 3 (DRAM)
29 address line output 2 (DRAM)
30 address line output 1 (DRAM)
31 address line output 0 (DRAM)
32 supply voltage
A3
62 scan test clock input
(should be tied LOW)
A2
A1
CLKO
ALL
63 clock signal output
A0
64 mode select input
(should be tied HIGH)
VDD
MUX
33 address latch strobe output (SRAM)
1997 May 30
4
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
RST
SCL
1
2
3
4
5
6
7
8
9
51 AS1
V
50
49
SS
SDA
MUTE
n.c.
TST3
48 TST2
47 TST1
V
n.c.
46
SS
V
45 TSTCLK
DD
V
DIBCK
DIWS
44
43
DD
V
SS
CAS 10
D0 11
D1 12
42 DI2D
41 DI1D
SAA7740H
V
40
SS
V
13
39 n.c.
SS
V
38
OE 14
D2 15
DD
37 DOBCK
36 DOWS
35 DO2D
34 DO1D
33 MUX
MLC156
D3 16
CAS2 17
WE 18
RAS 19
Fig.2 Pin configuration.
5
1997 May 30
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
GENERAL DESCRIPTION
GENERAL DAPIC MODE
The SAA7740H is a function-specific digital signal
processor. The device is capable of performing processing
for listening-environments such as equalization,
hall-effects, reverberation, surround-sound and digital
volume/balance control. The SAA7740H can also be
reconfigured (in a dual and quad filter mode) so that it can
be used as a digital filter with programmable
characteristics.
In the general DAPIC mode two variants are available
(see Figs 3 and 4). In this mode the DAPIC accepts
2 stereo input signals. DC filtering is performed on the
inputs before further processing. On one of the stereo
inputs a 5-band graphic equalization can be performed.
The stereo image of this signal can be controlled from
mono to stereo.
In the first variant (see Fig.3) a stereo hall-effect can be
added to the signal by means of direct reflections. In the
second variant (see Fig.4) a reverberation effect can be
added to the signal by means of exponential decaying
reflections. Surround-sound can then be created for the
rear loudspeakers. The surround-sound module is also
able to provide karaoke.
For reasons of silicon efficiency, the SAA7740H realises
most functions directly in hardware. The flexibility exists in
the possibility to download function parameters, correction
coefficients and various configurations from a host
microcontroller (see Fig.1). The parameters can be
passed in real time and all functions can be switched on
simultaneously.
The surround-sound module accepts the second stereo
input, a microphone signal can be added via the 5-band
equalizer. At the output, each of the 4 channels can be
individually delayed via the external DRAM.
The interfacing and addressing of the DRAM is performed
by the DAPIC.
The communication with a host microcontroller conforms
with the standard I2C-bus format. The SAA7740H accepts
2 digital stereo signals in the I2S-bus format at audio
sampling frequency (fas) and provides 2 digital stereo
outputs.
The applications for the general mode are digital
amplifiers, audio combination sets and TV audio channels.
Mode description
The SAA7740H can be set in four basic modes of
operation.
1997 May 30
6
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
LM5C1
a n d b l p a g e w i d t h
1997 May 30
7
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
LM1C52
a n d b p a g e w i d t h
1997 May 30
8
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
16 poles and 16 zeros can be selected arbitrarily from the
Z-domain. At the output, one of the channels can be
delayed internally by the DAPIC. The two corrected
outputs can be added to either one of the two stereo
outputs.
DUAL-FILTER MODE
In the dual-filter mode one mono signal is accepted
(see Fig.5) The input can be selected from either one of
the 2 stereo inputs (from the left or right input channel).
DC filtering is performed at the input before further
processing. Two separate corrections, in parallel, can be
performed by means of an 8-band graphic equalizer.
The application for this mode is in loudspeaker correction.
16 POLE/ZERO
CORRECTION
FIXED
DELAY
FILTER
11 SAMPLES
DC
FILTERS
16 POLE/ZERO
CORRECTION
FILTER
SWITCHES
SWITCHES
MLC153
Fig.5 Dual filter mode.
1997 May 30
9
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
QUAD-FILTER MODE
STEREO EXPANSION MODE
In the quad-filter mode two stereo signals are accepted
(see Fig.6). DC filtering is performed at the inputs before
further processing. A correction can be performed on the
input signals using a 4-band graphic equalizer, i.e. 8 poles
and 8 zeros can be placed arbitrarily in the Z-domain.
At the output, different delays can be applied to the
4 channels via the external DRAM. The interfacing and
addressing of the DRAM is performed by the DAPIC.
In the stereo expansion mode one stereo signal is
accepted (see Fig.7). DC filtering is performed at the
inputs before further processing. A 4-band graphic
equalization is first performed after which a complex
stereo expansion is applied. A room effect can be added
by the addition of early reflections.
The applications for this mode are in the headphone
out-of-head and incredible stereo applications.
The application for this mode is in 4-channel correction
applications such as car and home audio systems.
8 POLE/ZERO
CORRECTION
FILTER
8 POLE/ZERO
CORRECTION
FILTER
(1)
DC
FILTERS
SWITCHES
DELAY
SWITCHES
8 POLE/ZERO
CORRECTION
FILTER
8 POLE/ZERO
CORRECTION
FILTER
MLC154
(1) External DRAM.
Fig.6 Quad filter mode.
1997 May 30
10
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
LM1C5
a n d b l l p a g e w i d t h
1997 May 30
11
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
The transfer byte organization is as follows:
FUNCTIONAL DESCRIPTION
START condition
The SAA7740H is used as a slave device. The internal
operation is automatically synchronized with the word
select clock of the incoming data (I2S-bus format). Within
an input frame of data, at fas, 384 clock cycles are needed
to compute a stereo output sample. The external clock
therefore, should be minimum 384fas. External clocks
which generate more than 384 clocks cycles will cause the
processor to return to a wait state.
First byte (8 bits)
Acknowledge (1-bit)
Second byte (8 bits)
Acknowledge (1-bit)
Third to tenth byte (8 bits)
Acknowledge (1-bit)
STOP condition.
The external clock can be either a crystal connected
directly to the DAPIC, or any clock generated in the system
which contains DAPIC.
The first byte is the address of the I2C-bus device being
addressed. If the device detects its address it answers with
an acknowledge by pulling down the data line (SDA) for
one clock period (SCL line). The second byte contains the
address of the internal RAM to which the first new
coefficient should have written. The data will then be
transmitted. Each new word (coefficient) is 2 bytes wide.
Up to four words of data can be written within one transfer.
Should the mode of the feature register be addressed then
only one data word will be transferred.
The I2S-bus
Two I2S-bus inputs and outputs are available on the
DAPIC. The serial clock (DIBCK and DOBCK) and the
word select (DIWS and DOWS) are applied from an
external source. The two inputs and outputs are fully
synchronized. However, the inputs do not have to be
synchronized with the outputs. The clock and word select
signals can be separated at the input and output.
Because the I2C-bus (on the DAPIC) is a slave receiver
bus, the clock has to be generated by the host
microcontroller.
The input and output buses support word lengths in
accordance with the I2S-bus standard. Up to 20 significant
bits can be read by the DAPIC. Zeros will be added at the
LSB position should less than 20 bits be applied. If more
than 20 bits are applied the extra LSBs will be ignored.
The stereo word rate (fas) can be either 32, 44.1 or 48 kHz.
The minimum time interval between two I2C-bus transfers
(bus free between a STOP and START condition) should
coeff + 1
be: tinv
>
ms
-----------------------
fas
Because the DAPIC is a slave device it can only be
connected to a master I2S-bus transmitter or receiver
(see Chapter “Timing characteristics” and Fig.9).
Where:
Number of coefficients = coeff
Frequency fas should be in kHz.
I2C-bus control (SCL and SDA)
The I2C-bus interface is used to control the operation of
the DAPIC for the audio signal processing and write the
coefficients and the external delay line addresses of the
different signal processing algorithms. New coefficients
are updated in real time to the internal RAM.
Table 1 I2C-bus slave address.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
1
1
0
AS2(1)
AS1(1)
0
Note
1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will
respond with an acknowledge pulse on the SDA line.
1997 May 30
12
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
Improper acknowledge generated by the DAPIC
If an I2C-bus device, other than DAPIC, is addressed by the master then the DAPIC will generate a short acknowledge
pulse. The DAPIC starts pulling down the SDA line at the trailing edge of the SCL clock pulse. and releases the SDA line
approximately 390 ns after the leading edge of the following SCL LOW-to-HIGH transition (see Fig.8).
This improper acknowledge pulse can cause the I2C-bus master to detect an incorrect acknowledgement, depending on
the capturing moment of the SDA line by the I2C-bus master. Any possible non-acknowledgements of involved I2C-bus
devices, including the SAA7740H, will be masked thus making the system unreliable.
To avoid these problems the I2C-bus master should only capture the SDA line at such a moment that the improper
acknowledge pulse will not be detected.
non-DAPIC device address
data output
from transmitter
improper acknowledge
generated by DAPIC
data output
from DAPIC
SCL from
master
1
2
7
8
9
S
MGK425
START condition
390 ns (typ)
Fig.8 Improper acknowledge generated by the DAPIC.
1997 May 30
13
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
For fast DRAMs, the maximum value for RAS to CAS
delay time (tdRAS;CAS) is important.
DRAM interface
The DRAM interface contains a nibble wide data bus, a
9-bit wide address bus and all necessary control signals to
enable the different DRAM configurations.
Different DRAM combinations can be connected to the
DAPIC. The smallest DRAM is a 64 × 4-bit (256 kbits)
RAM. For this configuration, 16K data words can be
stored. When this RAM is connected to the DAPIC, the
MSB address signal (A8) can be felt floating.
Timing of the control signals RAS, CAS, CAS2, A8B, OE
and WE is related to the applied clock frequency of the
DAPIC. The important timing parameters are the page
mode cycle time (tcy;CAS), the access time (tacc;RAS), the
refreshing rate and the maximum value for RAS to CAS
delay time (tdRAS;CAS) (see Chapter “Timing
characteristics” and Fig.10). A read/write operation will
always be executed in the page mode (one row address
and four column addresses) because every data transfer
consists of 4 nibbles.
The DAPIC can address up to 1 Mbit DRAMs. However,
RAMs greater than 1 Mbit can also be connected. This,
therefore, implies that the redundant address lines of the
RAM must be fixed to VDD or VSS or must be joined with
one of the other address pins.
The choice of a 256 kbit or a 1 Mbit DRAM device must be
indicated by a flag bit residing in the start address control
word of the different delay lines.
The refresh time of the DRAM (trfsh) must be greater than;
2addr
trfsh
>
ms
-------------
3fas
where ‘addr’ is the number of physical address lines and
fas is measured in kHz.
1997 May 30
14
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
V
(each supply pin)
∆VDD
voltage difference between VDD
and VDDX
−
550
mV
IIK
DC input clamp diode current
VI < −0.5 V or VI > VDD + 0.5 V
−
−
±10
±20
mA
mA
IOK
DC output clamp diode current VO < −0.5 V or
(output type 4 mA)
VO > VDD + 0.5 V
IO
DC output sink or source
current (output type 4 mA)
−0.5 < VO < VDD + 0.5 V
−
±20
mA
IDD
DC supply current per pin
DC supply current per pin
latch-up protection
−
50
mA
mA
mA
mW
W
ISS
−
50
LTCH
PO
CIC specification/test method
100
−
−
power dissipation per output
total power dissipation
storage temperature
100
1
Ptot
Tstg
Tamb
Ves
−
−65
−40
−3000
−300
+150
+85
+3000
+300
°C
°C
V
operating ambient temperature
electrostatic discharge
note 1
note 2
V
Notes
1. Human body model: C = 100 pF; R = 1.5 kΩ.
2. Machine model: C = 200 pF; L = 2.5 µH; R = 0 Ω.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
47
UNIT
K/W
1997 May 30
15
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
DC CHARACTERISTICS
VDD = 4.5 to 5.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
4.5
TYP.
5.0
MAX.
UNIT
VDDn
DC supply voltage (pins 7, 8,
26, 32, 38, 53, 54 and 60)
5.5
V
IDD(tot)
total of all DC supply current
pins
fxtal = 16.9344 MHz
fxtal = 16.9344 MHz
−
60
−
mA
Ptot
VIH
total power dissipation
−
300
−
−
mW
V
HIGH level input voltage
(pins 1, 3, 4, 11, 12, 15, 16,
36, 37, 41 to 45, 47 to 49, 51,
52, 62 and 64)
0.7VDD
−
VIL
LOW level input voltage
(pins 1, 3, 4, 11, 12, 15, 16,
36, 37, 41 to 45, 47 to 49, 51,
52, 62 and 64)
−
−
0.3VDD
V
Vth(pos)
Vth(neg)
Schmitt trigger positive-going
threshold (pin 2)
−
−
−
0.8VDD
V
V
Schmitt trigger negative-going
threshold (pin 2)
0.2VDD
−
Vhys
VOH
hysteresis voltage (pin 2)
−
0.33VDD
−
−
V
V
HIGH level output voltage
(pins 10 to 12, 14 to 24, 27 to
31, 33 to 35 and 63)
VDD = 4.5 V; IO = 4 mA
4.0
−
VOL
LOW level output voltage
(pins 3, 10 to 12, 14 to 24, 27
to 31, 33 to 35 and 63)
VDD = 4.5 V; IO = 4 mA
VDD = 0 or 5.5 V
−
−
−
−
0.5
V
ILI
input leakage current
±1
µA
(pins 1, 2, 4, 36, 37, 41 to 45,
47 to 49, 51, 52 and 62)
IZO
output leakage current; 3-state VDD = 0 or 5.5 V
(pins 3, 11, 12, 15 and 16)
−
−
−
±5
µA
kΩ
Rpd
internal pull-down resistance
to VSS (pin 64)
VI = VDD
17
134
tr(i)
tf(i)
tr(o)
input rise time
input fall time
VDD = 5.5 V
VDD = 5.5 V
−
−
−
6
6
−
200
200
ns
ns
output rise time for
VDD = 4.5 V; Tamb = 85 °C;
9.5 + 0.4CL ns
LOW-to-HIGH transition
CL = pF; pins 11, 12, 15 and 16
VDD = 4.5 V; Tamb = 85 °C;
−
−
8.5 + 0.4CL ns
CL = pF; pins 10, 14, 17 to 24,
27 to 31, 33 to 35 and 63
tf(o)
output fall time for
HIGH-to-LOW transition
VDD = 4.5 V; Tamb = 85 °C;
CL = pF; pins 11, 12, 15 and 16
−
−
−
−
11 + 0.5CL ns
9.0 + 0.5CL ns
VDD = 4.5 V; Tamb = 85 °C;
CL = pF; pins 10, 14, 17 to 24,
27 to 31, 33 to 35 and 63
1997 May 30
16
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
AC CHARACTERISTICS
VDDX = 5 V; Tamb = +25 °C; unless otherwise specified.
SYMBOL
fxtal
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
MHz
crystal input frequency
≥384f
12.288
20
16.9344 23.0
as
αf
I59
g
spurious frequency
attenuation
−
−
1
−
dB
crystal current output
(pin 59)
slave mode only
−
−
−
mA
mS
transconductance at
maximum current
0.4
Vxtal
CL
1⁄2Tclk
voltage across crystal
load capacitance
−
500
−
−
mV
pF
ns
−
15
−
half clock period of
external clock
21
−
TIMING CHARACTERISTICS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
ns
tHC
tLC
tr
pulse width HIGH, DIBCK and DOBCK
pulse width LOW, DIBCK and DOBCK
DIBCK and DOBCK rise time
DIBCK and DOBCK fall time
DIWS and DOWS hold time
DIWS and DOWS set-up time
DI1D and DI2D hold time
110
110
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
20
20
−
tf
−
th1
tsu1
th2
tsu2
tacc
10
20
10
20
−
−
−
DI1D and DI2D set-up time
−
DO1D and DO2D access time
25 + 0.5CL
(CL in pF)
DRAM timing
1⁄2Tclk
half clock period
21
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tp;RAS
RAS precharge time
4 × 1⁄2Tclk − 12
16 × 1⁄2Tclk − 12
1⁄2Tclk − 8
−
tW;RAS
tsu;RA
RAS pulse width
−
row address set-up time
row address hold time
−
th;RA
1⁄2Tclk − 12
−
tdRAS;CAS
th;CAS
RAS to CAS delay time
CAS hold time
2 × 1⁄2Tclk − 11
4 × 1⁄2Tclk − 12
2 × 1⁄2Tclk − 12
−
5 × 1⁄2Tclk − 11
1⁄2Tclk − 12
3 × 1⁄2Tclk − 8
4 × 1⁄2Tclk − 14
1⁄2Tclk − 8
2 × 1⁄2Tclk + 14
−
th;RAS
RAS hold time
−
tRAS;CA
thCA;RAS
thCA;RASp
tlCA;RAS
tpCAS;RAS
tsu;CA
RAS to column address
column address hold time from RAS
column address hold time from RAS precharge
column address to RAS lead time
CAS to RAS precharge time
column address set-up time
1⁄2Tclk + 8
−
−
−
−
−
1997 May 30
17
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
SYMBOL
th1CA;CAS
PARAMETER
MIN.
MAX.
UNIT
ns
column address hold time to CAS
column address hold time to CAS precharge
CAS pulse width
3 × 1⁄2Tclk − 14
1⁄2Tclk − 15
2 × 1⁄2Tclk − 14
2 × 1⁄2Tclk − 11
4 × 1⁄2Tclk
−
−
−
−
−
−
th2CA;CAS
tW;CAS
tp;CAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS precharge time
tcy;CAS
tacc;CA
tacc;CAS
tacc;RAS
thDAT;CAS
trcy;def
CAS page mode cycle time
access time from column address
access time from CAS
3 × 1⁄2Tclk − 20
2 × 1⁄2Tclk − 24
4 × 1⁄2Tclk − 22
−
access time from RAS
−
data hold time from CAS
read cycle definition time
data input set-up time
2
−
4 × 1⁄2Tclk − 10
1⁄2Tclk − 8
3 × 1⁄2Tclk − 16
5 × 1⁄2Tclk − 15
2 × 1⁄2Tclk − 12
−
−
tsu;DAT
th;DAT
−
data input hold time
−
thDAT;RAS
twcy;def
toff
data input hold time from RAS
write cycle definition time
output data disable time
−
−
1⁄2Tclk + 8
VH
VL
CL
t
t
HC
LC
t
t
su1
h1
WS
t
t
su2
h2
DATA IN
t
acc
DATA OUT
MLC157
Fig.9 I2S-bus timing diagram.
1997 May 30
18
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
t
f
h
t
t
t
r
p;RAS
W;RAS
t
hCA;RAS
V
V
H
RAS
CAS
L
t
t
t
t
h;CAS
dRAS;CAS
cy;CAS
t
p;CAS
t
t
h;RAS
t
t
W;CAS
pCAS;RAS
t
t
RAS;CA
t
su;CA
t
t
lCA;RAS
t
h1CA;CAS
h;RA
t
t
t
su;RA
r
h2CA;CAS
COLUMN ADD
hCA;RASp
ROW
ADD
A0 to A8
COLUMN ADD
COLUMN
WE
t
acc;CA
t
t
t
t
rcy;def
rcy;def
rcy;def
rcy;def
t
acc;CAS
READ
OE
t
t
hDAT;CAS
acc;RAS
D0 to D3
DATA OUT
DATA OUT
wcy;def
t
wcy;def
t
WE
WRITE
OE
t
wcy;def
t
wcy;def
t
off
t
t
su;DAT
h;DAT
D0 to D3
DATA IN
DATA
IN
t
hDAT;RAS
t
t
p;RAS
W;RAS
RAS
t
t
t
p;RAS RAS;CA
pCAS;RAS
REFRESH
CAS
MLC158
A0 to A8
ROW
Fig.10 Timing diagram DRAM interface.
19
1997 May 30
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
I2S-BUS PROTOCOL
Two data line have been implemented as input from an
external processor for the four audio channels. Because of
this configuration the DAPIC operates in the following
manner.
The I2S-bus digital interface is used for communication to
external digital sources. It is a 3-line serial bus with one
line each for data, clock and word select. Figure 11
illustrates an excerpt from the Philips I2S-bus specification
interface report with respect to general timing and format
of the bus. Word select (WS) at logic 0 signifies the left
channel and logic 1 the right channel.
The I2S-bus input block reads 4 samples (left and right
samples of the front and rear channel) and stores the
information into the register file. The operators read from
the register file, process the data and store the
intermediate results back into the register file. If a delay
line is required, the external RAM will need to be
accessed. The output samples are read from the register
file and are passed via the fade unit to the I2S-bus output
block. The same operation is repeated for each incoming
audio sample.
The serial data is transmitted in two’s complement with
MSB first. One clock period after the negative edge of the
WS line, the MSB of the left channel is transmitted. Data is
synchronized on the negative edge of the clock and
latched on the positive edge.
T
t
t
LC
HC
V
IH
SCK
V
IL
t
t
sr
hr
V
IH
SD WS
V
IL
SCK
WS
MSB
LEFT
MSB
RIGHT
SD
MLC159
Fig.11 I2S-bus timing format.
1997 May 30
20
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
I2C-BUS PROTOCOL
Data transfer
The I2C-bus is intended for 2-way, 2-line communication
between different ICs or modules. The two lines are the
serial data line (SDA) and the serial clock line (SCL). Both
lines must be connected to the supply rail via a pull-up
resistor when connected to the output stages of a
microcontroller. Data transfer can only be initiated when
the bus is not busy. Full details of the I2C-bus are given in
the document “The I2C-bus and how to use it”. This
document may be ordered using the code
A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the device are the ‘slaves’ (see Fig.14).
Acknowledge
The number of data bytes that are transferred between the
START and STOP conditions, from transmitter to receiver,
is unlimited. Each byte is followed by an acknowledge bit.
The acknowledge bit is a HIGH level bit placed on the bus
by the transmitter, whereas the master generates an extra
acknowledge bit which is related to the clock pulse. A slave
receiver which is addressed must generate an
acknowledge bit after the reception of each byte.
The master must also generate an acknowledge bit after
the reception of each byte that has been clocked out of the
slave transmitter.
9398 393 40011.
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulses as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.12).
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Set-up and hold times
must also be taken into account. A master receiver must
signal an end-of-data to the transmitter. This is achieved
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this condition the
transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.15).
START and STOP condition
In the START and STOP condition the data and clock lines
remain HIGH when the bus is not busy. A HIGH-to-LOW
transition on the data line, while the clock is HIGH, is
defined as the START condition (S). A LOW-to-HIGH
transition on the data line, while the clock is HIGH, is
defined as the STOP condition (P); (see Fig.13).
SDA
SCL
MLC160
data line
stable
change
of data
data valid
allowed
Fig.12 Bit transfer on the I2C bus.
1997 May 30
21
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
SDA
SCL
S
P
START condition
STOP condition
MLC161
Fig.13 START and STOP conditions.
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete
interrupt within receiver
clock line held LOW while
interrupts are serviced
SCL
1
2
7
8
9
1
2
3 to 8
9
ACK
S
START condition
P
STOP condition
MLC162
Fig.14 Data transfer on the I2C-bus.
data output
from transmitter
not acknowledge
data output
from receiver
acknowledge
SCL from
master
1
2
7
8
9
MLC163
S
clock pulse for
START condition
acknowledgement
Fig.15 Acknowledge on the I2C-bus.
22
1997 May 30
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
APPLICATION INFORMATION
Clock circuit and oscillator
The clock generation of the SAA7740H is designed to
accommodate two main modes, the master and the slave.
handbook, halfpage
C1
10 pF
C2
CLK1/XTAL1
56
R1
100
kΩ
In the master mode, the DAPIC is the master in the
system. The clock is generated by connecting a crystal to
the oscillator pins CLK1/XTAL1 and XTAL2 (see Fig.16).
59
XTAL2
10 pF
In the slave mode, the DAPIC is supplied as a slave.
The external clock should be connected to the oscillator at
pin CLK1/XTAL1 (see Fig.17).
MLC164
Crystal oscillator supply
The power supply for the oscillator is separate from the
other supply line. This is to minimize feedback from the
ground bounce of the IC to the oscillator. Pin VSSX is the
ground supply and VDDX is the positive supply.
Fig.16 Master mode.
Power supply connection and EMC
The SAA7740H has in total 8 positive supply lines (VDD
)
including VDDX, and 8 ground supply lines (VSS) including
VSSX. For correct current distribution all positive supply
lines should be connected together on the printed
circuit-board. The ground supply lines should also be
connected together on the printed circuit-board.
handbook, halfpage
external
C1
CLK1/XTAL1
R1
56 max 1 V (p-p)
clock
10 pF
30 pF
100
C2
kΩ
To minimize radiation the IC should be placed on a
double-layer printed circuit-board with a large ground
plane on one side. The ground supply lines should have a
short connection to the ground plane. An LC network in the
positive supply lines can be used as a high frequency filter.
59
XTAL2
C3
10
nF
MLC165
Test mode connections
Pins SCCLK, TSTCLK, TST1, TST2 and TST3 are used to
put the IC in the test mode and to test the internal
connections. In the application these pins must be
connected to ground.
Fig.17 Slave mode.
1997 May 30
23
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.4
1.2
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT319-2
1997 May 30
24
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
SOLDERING
Introduction
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
Reflow soldering techniques are suitable for all QFP
packages.
QFP100 (SOT382-1) or QFP160 (SOT322-1).
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 May 30
25
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 May 30
26
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
NOTES
1997 May 30
27
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/04/pp28
Date of release: 1997 May 30
Document order number: 9397 750 02262
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