TDA9840TD-T_技术文档

INTEGRATED CIRCUITS

DATA SHEET

TDA9840

TV and VTR stereo/dual sound

processor with digital identification

and I²C-bus control

1998 Jul 03

Product speciﬁcation

Supersedes data of 1995 Mar 21

File under Integrated Circuits, IC02

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

FEATURES

• Supply voltage 5 to 8 V

• De-emphasis

• Source selector

• Level and stereo matrix adjustment possible via the

I²C-bus

GENERAL DESCRIPTION

• I²C-bus transceiver

The TDA9840 is a stereo/dual sound processor for TV and

VTR sets. Its identification ensures safe operation by using

internal digital PLL technique with extremely small

bandwidth, synchronous detection and digital integration

(switching time maximum 2.3 s; identification concerning

the main functions).

• AF inputs for NICAM or AM sound (standard L)

• AF outputs for Main and SCART

• AF input and output signals selectable via the I²C-bus

• Information for identified transmission mode is readable

via I²C-bus

• Software is compatible with the TDA8415/16/17

• Quartz oscillator and clock generator

• Three digital PLL, alignment-free

• Two digital integrators, alignment-free

• Stabilizer circuit for ripple rejection and constant output

signals

• ESD protection of all pins.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

TDA9840

DIP20

SO20

plastic dual in-line package; 20 leads (300 mil)

SOT146-1

SOT163-1

TDA9840T

plastic small outline package; 20 leads; body width 7.5 mm

1998 Jul 03

2

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

QUICK REFERENCE DATA

SYMBOL

PARAMETER

supply voltage (pin 18)

CONDITIONS

MIN.

4.5

TYP.

MAX. UNIT

V_P

5

8.8

20.5

−

V

I_P

supply current (pin 18)

15.5

16.5

250

mA

mV

V_i(rms)

nominal input signal voltage (V_{i 1}, V_{i 2}, V_{i 3})

(RMS value)

54% modulation

−

V_o(rms)

nominal output signal voltage (RMS value)

THD ≤ 0.3%

54% modulation

−

500

−

mV

clipping level of the output signal voltages

(RMS value)

THD ≤ 1.5%

V_P= 5 V

1.4

2.4

+2.4

−2.3

+2.4

−1.9

5

1.6

2.65

+2.5

−2.4

+2.5

−2.0

−

V

V_P= 8 V

−

V

∆G_v

stereo control range for V_{i 1}(0.1 dB steps)

level control range for V_{i 2}(0.5 dB steps)

+2.6

−2.5

+2.6

−2.1

100

−

dB

mV

dB

%

V_{i pil}

input voltage sensitivity of pilot frequency

weighted signal-to-noise ratio

total harmonic distortion

unmodulated

“CCIR468-3”

S/N(W)

THD

T_amb

f_ident

66

75

−

0.2

−

0.3

+70

operating ambient temperature range

identiﬁcation window width

0

°C

normal mode

STEREO

DUAL

2.0

2.3

−

2.0

2.3

Hz

fast mode

STEREO

DUAL

3.8

5.8

−

3.8

5.8

Hz

t_ident(on)

total identiﬁcation time ON

normal mode

STEREO

DUAL

0.35

−

2.3

2.0

s

fast mode

STEREO

DUAL

0.175

−

1.1

1.0

−

s

−

s

V_{i tuner}

identiﬁcation voltage sensitivity

28

dBµV

∆f_pil

pull-in frequency range of pilot PLL

f_ω= 10.008 MHz

lower side

−296

−

−296

Hz

upper side

302

1998 Jul 03

3

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

PINNING

SYMBOL PIN

DESCRIPTION

I²C-bus data input/output

SDA

C_AGC

C_LP

C_DCL

V_{i pil}

C_ref

1

2

3

4

5

6

7

8

9

AGC capacitor of pilot frequency ampliﬁer

identiﬁcation low-pass capacitor

fpage

SDA

1

2

20 SCL

DC loop capacitor

C

19 XTAL

AGC

pilot frequency input voltage

C

V

capacitor of reference voltage (¹⁄₂V_P)

AF input signal V_{i 1}(from 1st sound carrier)

AF input signal V_{i 2}(from 2nd sound carrier)

AF input signal V_{i 3}(NICAM or AM sound (standard L))

3

18

17

LP

P

C

V_{i 1}

4

DCL

D2

V_{i 2}

V

5

16 GND

i pil

TDA9840

V_{i 3}

C

V

6

15

14

13

12

11

ref

D1

V_{i 4}

10 AF input signal V_{i 4}(NICAM)

11 AF output signal V_{o 4}(SCART)

12 AF output signal V_{o 3}(SCART)

13 AF output signal V_{o 2}(main)

14 AF output signal V_{o 1}(main)

15 50 µs de-emphasis capacitor of AF Channel 1

16 ground (0 V)

V

7

i 1

i 2

i 3

i 4

o 1

V_{o 4}

V_{o 3}

V_{o 2}

V_{o 1}

C_D1

GND

C_D2

V_P

V

o 2

8

V

9

o 3

V

10

o 4

MBE459

17 50 µs de-emphasis capacitor of AF Channel 2

18 supply voltage (+5 to +8 V)

19 10 MHz crystal input

XTAL

SCL

Fig.3 Pin configuration.

20 I²C-bus clock input

1998 Jul 03

6

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

are fed to the AM-synchronous demodulator. The

FUNCTIONAL DESCRIPTION

demodulator detects the identification signal, which is fed

through a low-pass filter with external capacitor C_LP(pin 3)

to a Schmitt-trigger for pulse shaping and suppression of

low level spurious signal components. This is a measure

against mis-identification.

The TDA9840 (see Fig.1) receives the signals from the

FM-demodulators in a TV two sound-carrier system. The

circuit is realized by the H00485 bipolar process.

The IC is intended for use in economic TV and VTR

receivers. Therefore optimum relationship between

integration of functions and use of external components

has been striven for. Additionally a new type of

identification circuit has been developed.

The identification signal is amplified and fed through an

AGC low-pass filter with external capacitor C_AGC(pin 2) to

obtain the AGC voltage for controlling the gain of the pilot

signal amplifier.

The identification stages consist of two digital PLL circuits

with digital synchronous demodulation and digital

integrators to generate the stereo or dual sound

identification bits which can be read out via the I²C-bus.

AF signal handling

The input AF signals, derived from the two sound carriers,

are processed in analog form using operational

amplifiers.The circuit incorporates level- and

A 10 MHz quartz crystal oscillator provides the reference

clock frequency. The corresponding detection bandwidth

is larger than ±50 Hz for the pilot carrier signal, so that

f_p-variations from the transmitter can be tracked in case of

missing synchronisation with the horizontal frequency f_H.

However the detection bandwidth for the identification

signal is made small (approximately ±1 Hz) to reduce

mis-identification.

stereo-adjustment to correct the spreading in the FM

detector output levels. Dematrixing uses the technique of

two amplifiers processing the AF signals. Finally, a source

selector provides the facility to route the mono signal

through to the outputs (‘forced mono’).

De-emphasis is performed by two RC low-pass filter

networks with internal resistors and external capacitors.

This provides a frequency response with the tolerances

given in Fig.4.

Figure 2 shows an example of the alignment-free f_p

band-pass filter. To achieve the required Q_Lof

A source selector, controlled via the I²C-bus, allows

selection of the different modes of operation in accordance

with the transmitted signal. The device was designed for a

nominal input signal (FM: 54% modulation is equivalent to

∆f = ±27 kHz / AM: m = 0.54) of 250 mV RMS (V_{i 1}, V_{i 2}),

respectively 500 mV RMS (V_{i 3},V_{i 4}). A nominal gain of

6 dB for V_{i 1}and V_{i 2}signals and 0 dB for V_{i 3}and V_{i 4}

signals is built-in. By using rail-to-rail operational

approximately 12, the Q₀at f_pof the coil was chosen to be

approximately 25 (effective Q₀including PCB influence).

Using coils with other Q₀, the RC-network (R_FP, C_FP) has

to be adapted accordingly. It is assumed that the loss

factor tanδ of the resonance capacitor is ≤0.01 at f_p.

Copper areas under the coil might influence the loaded Q

and have to be taken into account. Care has also to be

taken in environments with strong magnetic fields when

using coils without magnetic shielding.

amplifiers, the clipping level (THD ≤1.5%) is 1.6 V RMS for

V_P= 5 V and 2.65 V RMS for V_P= 8 V at outputs V_{o 1}

,

V

_{o 2},V_{o 3}and V_{o 4}. Care has been taken to minimize

I²C-bus transceiver

switching plops. Also total harmonic distortion and random

noise are considerably reduced.

The complete IC is controlled by a microcomputer via the

I²C-bus. The built-in I²C-bus transceiver transmits the

identification result to the I²C-bus and receives the control

data for the source selector and level control. The I²C-bus

protocol is given in Tables 2 to 12 respectively.

Identiﬁcation

The pilot signal is fed via an external RC high-pass filter

and single tuned LC band-pass filter to the input of a gain

controlled amplifier. The external LC band-pass filter in

combination with the external RC high-pass filter should

have a loaded Q-factor of about 40 to 50 to ensure the

highest identification sensitivity. By using a fixed coil (±5%)

to save the alignment (see Fig.2), a Q-factor of about 12 is

proposed. This may cause a loss in sensitivity of about

2 to 3 dB. A digital PLL circuit generates a reference

carrier, which is synchronized with the pilot carrier.

This reference carrier and the gain controlled pilot signal

The data transmission between the microcontroller and

the other I²C-bus controlled ICs is not disturbed, when the

supply voltage of the TDA9840 is not connected or when

powering up or down. Finally, a Schmitt-trigger is built-in

the SDA/SCL interface to suppress spikes from the

I²C-bus.

1998 Jul 03

7

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Power supply

Fast mode / test mode

The different supply voltages and currents required for the

analog and digital circuits are derived from an internal

band-gap reference circuit. The AF reference voltage is

¹⁄₂V_P. For a fast setting to ¹⁄₂V_Pan internal start-up circuit

is added. A good ripple rejection is achieved with the

external capacitor C_ref= 100 µF/16 V in conjunction with

the high ohmic input of the ¹⁄₂V_Ppin (pin 6). Additional

DC-load on this pin is prohibited.

The TDA9840 has a fast mode (test mode) to reduce the

integration time of the 117/274 Hz integrator from

approximately 1 to 0.5 s.

ESD protection

All pins are ESD protected. The protection circuits

represent the latest state of the art.

Internal circuit

Power-on reset

The internal pin loading diagram is given in Fig.7.

When a power-on reset is activated by switching on the

supply voltage or because of a supply voltage breakdown,

the 117/274 Hz DPLL, the 117/274 Hz integrator and the

registers will be reset. Both AF channels

(Main and SCART) are muted.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

supply voltage (pin 18)

CONDITIONS

MIN.

−0.3

MAX.

10

UNIT

V_P

V_i

V

voltage at pins 1 and 20

−0.3

−25

0

5.5

V

V_i

voltage at pins 2 to 15, 17 and 19

storage temperature

V_P

V

T_stg

+150

+70

±300

°C

V

T_amb

V_esd

operating ambient temperature

electrostatic handling for all pins

note 1

−

Note

1. Charge device model class B: discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL

R_{th j-a}

PARAMETER

VALUE

UNIT

thermal resistance from junction to ambient in free air

DIP20

SO20

73

90

K/W

1998 Jul 03

8

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

CHARACTERISTICS

V_P= 5 V; T_amb= +25 °C; nominal input signal V_{i 1, 2}= 0.25 V RMS value (FM: 54% modulation is equivalent to

∆f = ±27 kHz); nominal input signal V_{i 3, 4}= 0.5 V RMS value (AM: m = 0.54); nominal output signal V_{o 1, 2, 3, 4}= 0.5 V

RMS value; f_AF= 1 kHz; V_{i pil}= 16 mV RMS value; f_pil= 54.6875 kHz (identiﬁcation frequencies: stereo = 117.48 Hz,

dual = 274.12 Hz), 50 µs pre-emphasis; noise measurement in accordance with “CCIR468-3”, working oscillator

frequency f_ω= 10.008 MHz; currents into the IC positive; measured in test circuit according to Fig.5; unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

V_P

supply voltage (pin 18)

supply current (pin 18)

total power dissipation

4.5

5

8.8

V

I_P

15.5

16.5

82.5

20.5

mA

mW

V

P_tot

69.75

¹⁄₂V_P− 0.1 ¹⁄₂V_P

180.4

¹⁄₂V_P+ 0.1

V_n(DC)

DC voltage

(pins 7 to 15 and 17)

V_ref(DC)

l_L(DC)

DC reference voltage (pin 6)

DC leakage current (pin 6)

¹⁄₂V_P− 0.1 ¹⁄₂V_P

¹⁄₂V_P+ 0.1

±1

V

−

µA

AF Inputs; V_{i 1}and V_{i 2}(pins 7 and 8)

V_i(rms)

nominal input signal voltage

(RMS value)

54% modulation

0.25

−

V

V_i(rms)

clipping voltage level

(RMS value)

THD ≤ 1.5%; note 1

V_P= 5 V

0.625

1.050

0.715

1.200

−

V

V_P= 8 V

THD ≤ 1.5%; note 2

V_P= 5 V

0.780

1.300

5

0.900

1.500

6

−

V

V_P= 8 V

−

V

G_v

AF signal voltage gain

G = V_o/V_i; note 3

only at pin 7

7

dB

kΩ

∆G_v(V_o1) stereo control range

+2.4

−2.3

−

+2.5

−2.4

0.1

+2.6

−2.5

−

nominal step

maximum 49 steps

only at pin 8

∆G_v(V_o2) level control range

+2.4

−1.9

−

+2.5

−2.0

0.5

+2.6

−2.1

−

nominal step

maximum 9 steps

see Fig.4

R_i

input resistance

40

50

60

R_deem

internal de-emphasis resistor

(pins 15 and 17)

4.25

5.0

5.75

Additional AF input pin (pins 9 and 10)

V_i(rms)

nominal input signal voltage

(RMS value)

54% modulation

−

0.5

−

V

V_i(rms)

clipping voltage level

(RMS value)

THD ≤ 1.5%

V_P= 5 V

1.25

2.10

1.40

2.35

−

V

V_P= 8 V

G_v

R_i

AF signal voltage gain

input resistance

−1

0

1

dB

G = V_o/V_i; note 3

40

50

60

kΩ

1998 Jul 03

9

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

SYMBOL

AF outputs (pins 11 to 14)

V_o(rms)nominal output signal voltage THD ≤ 0.3%;

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

−

0.5

−

V

(RMS value)

54% modulation

THD ≤ 1.5%

V_P= 5 V

V_o(rms)

clipping voltage level

(RMS value)

1.4

2.4

1.6

−

V

V_P= 8 V

2.65

250

−

V

R_o

C_L

R_L

output resistance

150

−

350

1.5

−

Ω

load capacitor on output

nF

kΩ

load resistor on output

(AC-coupled)

10

−

B

frequency response

(bandwidth)

f_i= 40 to 20000 Hz;

note 4

−0.5

−

+0.5

dB

B_{−3 dB}

THD

frequency response

−3 dB; note 4

300

−

350

0.2

75

400

0.3

−

kHz

%

total harmonic distortion

note 3

S/N(W)

weighted signal-to-noise ratio “CCIR468-3”

(quasi-peak)

66

dB

α_cr

crosstalk attenuation for

DUAL

notes 3 and 5

Z_s≤ 1 kΩ

70

40

76

−

75

45

80

−

dB

mV

STEREO

Z_s≤ 1 kΩ

−

α_mute

mute attenuation

Z_s≤ 1 kΩ; note 3

after switching

−

∆V_DC

change of DC level output

voltage between any two

modes of operation

±10

PSRR

I_O(DC)

α_I2C

power supply ripple rejection

f_r= 70 Hz; see Fig.6

note 6

50

−

65

−

dB

µA

dB

DC output current

noise from I²C-bus

±20

80

−

90

10 MHz crystal oscillator (pin 19)

f_r

series resonant frequency of

crystal (fundamental mode)

C_L= 20 pF

9.995

9.988

10.008

10.021

10.028

MHz

f_ω

working oscillator frequency

over operating

(running in parallel resonance temperature range

mode)

including ageing and

inﬂuence of drive

circuit

R_r

equivalent crystal series

resistance

even at extremely low

drive level (<1 pW)

over operating

−

60

200

Ω

temperature range

with C₀= 6 pF

R_n

crystal series resistance of

unwanted mode

2 × R_r

−

Ω

C₀

C₁

crystal parallel capacitance

crystal motional capacitance

with R_r≤ 100 Ω

−

6

10

50

pF

fF

25

1998 Jul 03

10

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

µW

P_XTAL

level of drive in operation

−

5

V_OSC(p-p)oscillator operating voltage

(peak-to-peak value)

500

550

600

mV

Pilot processing

V_{i pil(rms)}

pilot input voltage level at pin 5 unmodulated

5

−

100

mV

(RMS value)

R_{i pil}

m

pilot input resistance

modulation depth

500

25

1000

50

−

kΩ

AM

75

%

∆f_pil

pilot PLL pull-in frequency

range (referred to

f_pil= 54.6875 kHz)

f_ω= 9.988 MHz

lower side

−405

−

−405

Hz

upper side

192

f_ω= 10.008 MHz

lower side

−296

−

−296

Hz

upper side

302

f_ω= 10.028 MHz

lower side

−188

411

0

−

−188

411

1.7

Hz

ms

Hz

kΩ

mV

upper side

−

t_pil

pilot PLL pull-in time

−

f_LP

low-pass frequency response −3 dB

450

18.75

−

600

25

−

750

31.25

70

R₃

low-pass output resistance

V_4(rms)

identiﬁcation threshold voltage

(RMS value)

Q_L

loaded quality factor of

resonance circuit

high sensitivity

40

−

50

loaded quality factor of

resonance circuit with ﬁxed

coil

sensitivity loss

2 to 3 dB; see Fig.2

−

12

−

t_{acqui AGC}AGC acquisition time

V_{i pil(rms)}switched from

0 to 100 mV RMS

value

−

0.1

s

Identiﬁcation (internal functions)

V_{i tuner}

C/N

H

identiﬁcation voltage sensitivity note 7

(pin 5)

−

28

33

−

2

dBµV

dB/Hz

dB

pilot carrier-to-noise ratio for

start of identiﬁcation

note 8

note 7

hysteresis

1998 Jul 03

11

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

SYMBOL

PARAMETER

CONDITIONS

normal mode

MIN.

TYP.

MAX.

UNIT

f_det

pull-in frequency range of

identiﬁcation PLL (referred to

lower side

STEREO

DUAL

f_{det STEREO}= 117.48 Hz and

−0.38

−

−0.38

Hz

f_{det DUAL}= 274.12 Hz)

−0.69

Hz

normal mode

upper side

STEREO

DUAL

0.69

−

0.69

Hz

fast mode lower side

STEREO

−0.89

−2.05

−

−0.89

−2.05

Hz

DUAL

fast mode upper side

STEREO

1.15

2.05

−

1.15

2.05

Hz

DUAL

t_det

pull-in time of identiﬁcation

PLL (referred to

f_{det STEREO}= 117.48 Hz and

f_{det DUAL}= 274.12 Hz)

normal mode

STEREO

0

−

1.35

0.72

s

DUAL

fast mode

STEREO

0

−

0.57

0.25

s

DUAL

f_ident

identiﬁcation window

normal mode; note 9

STEREO

frequency width (referred to

f_{det STEREO}= 117.48 Hz and

f_{det DUAL}= 274.12 Hz)

2.0

2.3

−

2.0

2.3

Hz

DUAL

fast mode; note 9

STEREO

3.8

−

3.8

Hz

s

DUAL

5.8

t_integr

integrator time constant

total identiﬁcation time on

normal mode

fast mode

0.94

0.47

0.94

0.47

s

t_ident(on)

normal mode; note 10

STEREO

0.35

−

2.3

2.0

s

DUAL

fast mode; note 10

STEREO

0.175

−

1.1

1.0

s

DUAL

t_ident(off)

total identiﬁcation time off

normal mode; note 11

STEREO

0.6

−

1.6

s

DUAL

fast mode; note 11

STEREO

0.3

−

0.8

s

DUAL

1998 Jul 03

12

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

SYMBOL

I²C-bus transceiver (pins 1 and 20)

f_CIclock frequency

I²C-bus: SCL (pin 20)

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

0

−

100

kHz

V_IL

V_IH

t_low

t_high

t_r

LOW level input voltage

−0.3

3.0

4.7

4.0

−

1.5

5.5

−

V

HIGH level input voltage

timing LOW period

timing HIGH period

rise time

V

µs

µA

−

1

t_f

fall time

−

0.3

−10

10

I_IL

LOW level input current

HIGH level input current

−

I_IH

−

I²C-bus: SDA (pin 1)

V_IL

V_IH

t_r

LOW level input voltage

−0.3

3.0

−

1.5

5.5

1

V

HIGH level input voltage

rise time

V

µs

µA

mA

µA

t_f

fall time

−

0.3

−

t_su

I_IL

data set-up time

0.25

−

LOW level input current

LOW level output current

HIGH level input current

−10

−

I_OL

I_IH

−3

−

10

Notes

1. Input control amplifiers with ∆G_v= 0 dB.

2. Input control amplifiers with ∆G_v= −2 dB.

3. V_o= 0.5 V RMS value; f = 1 kHz; input control amplifiers with ∆G_v= 0 dB.

4. Without de-emphasis capacitors with respect to nominal gain.

5. In dual mode: A (B)-signal into B (A) channel.

In stereo mode: R-signal into left channel; L-signal = 0.

6. Test procedure tbf (same as TDA9855).

7. Tuner input signal, measured with PCALH reference front end (¹⁄₂EMF, 75 Ω, 2T/20T/white bar, 100% video) and

PC/SC₁= 13 dB; PC/SC₂= 20 dB. The pilot band-pass has to be aligned.

8. Bandwidth of the pilot BP-filter B_{−3 dB}= 1.2 kHz. V_{i 2}input driven with identification-modulated pilot carrier and white

noise.

9. Identification window is defined as total pull-in frequency range (lower plus upper side) of identification PLL (steady

detection) plus window increase due to integrator (fluctuating detection).

10. The maximum total system identification time ON is equal to t_ident(on)plus t_{acqui AGC}plus t_{I2C read-out}

11. The maximum total system identification time OFF is equal to t_ident(off)plus t_{I2C read-out}

.

1998 Jul 03

13

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

I²C-BUS PROTOCOL FOR THE TV AND VTR

STEREO/DUAL SOUND PROCESSOR TDA9840

HIGH. After a successful reading of the status register, the

bit D7 will be reset to LOW.

The TDA9840 has an I²C-bus interface with five registers:

status, test, switch, level and stereo adjustment register

controlled by a microcontroller via I²C-bus. The status

register can be read and the other registers are write

registers. The status byte represents the transmitter status

detected by the identification circuit and the power-on

reset status. The switch register controls the source

selectors of the AF signal part, and the level and stereo

adjustment register set the input level and stereo

adjustment stage. Additionally, a test register is built-in to

reduce the detection time of the identification circuit (test

mode, fast mode respectively).

The bits D5 and D6 represent the transmitter status

detected by the identification circuit (stereo, dual or mono

transmission). The other bits are set to 0 (default).

Data format for the receiver

Table 1 Registers for receiver mode (see Table 6)

REGISTER

Switch register

VALUE

(00)_HEX

Port register

(01)_HEX(without function)

(02)_HEX

Level adjustment register

Stereo adjustment register (03)_HEX

Test register (04)_HEX

I²C-bus transceiver and data-handling

(bus speciﬁcation)

The TDA9840 is controlled by a microcomputer via the

bidirectional 2-line I²C-bus. The two lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data

transfer may be initiated only when the bus is not busy.

The port register is without function, because this IC has

no control ports as TDA8415/6/7. A data byte for the

subaddress (01)_HEXwill not be stored in any register. An

acknowledge will be sent to the microcontroller.

The first byte of the data transmission is the slave address

and the second byte is the subaddress indicating the data

register in which the data shall be stored. Starting from

subaddress (00)_HEXthe n-th data byte will automatically be

stored under subaddress n − 1.

When the bus is free, both lines are HIGH. The data on the

SDA line must be stable during the HIGH period of the

clock. The HIGH or LOW state of the data line can only

change, when the clock signal on the SCL line is LOW.

The set-up and hold times are specified in the

Chapter “Characteristics”.

All 8 bits of the subaddress are decoded by the device.

The subaddresses from (04)_HEXto (FF)_HEXare forbidden

for the user. If the I²C-bus transceiver receives

subaddresses from (05)_HEXto (FF)_HEX, no acknowledge

will be sent back to the microcontroller.

A HIGH-to-LOW transition of the SDA line, while SCL is

HIGH, is defined as the start condition. A LOW-to-HIGH

transition of the SDA line, while SCL is HIGH, is defined as

the stop condition. The bus transceiver will be reset on the

reception of a start condition. The bus is considered to be

busy after the start condition. The bus is considered to be

free again after a stop condition.

Switch register

The source selector is controlled by the switch register.

Table 7 shows the modes of operation. Note, that in the

event of the external operation mode, no further selection

is possible.

Data format transmitter mode

For the data transmission no subaddress is to be

transmitted, because there is only one read register

implemented. So the total number of bytes reduces from

three to two. The second byte represents the status of

the IC.

Status register (see Table 4)

The bit D7 (PONRES) represents the status of the IC and

indicates whether the power-on reset was activated by

switching-on the supply voltage or a supply voltage

breakdown. If so, the I²C-bus transceiver, the digital PLLs

and integrators are initialized and the PONRES bit is set to

1998 Jul 03

14

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Level adjustment register

Level and stereo adjustment

The information about the level adjustment of the AF

channel V_{i 2}(pin 8) is stored in the level adjustment

register (see Table 10). There are 10 steps (positions) of

the AF level adjustment stage. The level range is from

2.5 dB up to −2.0 dB in 0.5 dB steps.

For the level and stereo adjustment of both AF channels

V_{i 1}and V_{i 2}, the following procedure will be recommended.

Level adjustment of the AF channel V

• Feeds AF signal at the input V_{i 2}

After a power-on reset, the data byte of the level

adjustment register will be set to (00)_HEX: 0 dB gain at the

AF input V_{i 2}.

• Sets the data byte of the switch register (dual mode)

to (1A)_HEX

• Measures the signal at the outputs V_{o 2}or V_{o 4}

• Adjusts the output level with the level adjustment

Stereo adjustment register

register.

The information about the stereo adjustment of the

AF channel V_{i 1}(pin 7) is stored in the stereo adjustment

register (see Table 11). There are 50 steps (positions) of

the AF stereo adjustment stage. The stereo range is from

2.5 dB up to −2.4 dB in 0.1 dB steps.

Stereo adjustment of the AF channel V_{i 1}

• Feeds AF stereo signals at the inputs V_{i 1}((L+R)/2) and

V_{i 2}(R)

• Sets the data byte of the switch register (stereo mode)

to (2A)_HEX

After a power-on reset, the data byte of the stereo

adjustment register will be set to (00)_HEX: 0 dB gain at the

AF input V_{i 1}.

• Measures the crosstalk attenuation between V_{o 1}and

V_{o 2}or V_{o 3}and V_{o 4}

Test register (also used for fast mode)

• Adjusts the crosstalk attenuation with the stereo

adjustment register.

Table 12 shows the meaning of the test register. The

integration time of the integrator is approximately 1 s

(normal mode, default). If the data byte of this register is

set to HIGH, the integration time is reduced from

approximately 1 to approximately 0.5 s (fast mode, test

mode). The pull-in ranges of the identification PLLs are

changed to:

During the stereo adjustment the data byte of the level

adjustment register does not change.

After the level and stereo adjustment, the bytes of the level

and stereo adjustment register must be stored by the

microcontroller in a memory. (To avoid mis-adjustment it

would be wise to compare the stored bytes with the proper

adjustment bytes). If the PONRES bit of the status register

will be set to HIGH (see status register) the data bytes for

these both registers must be sent out of the memory to the

TDA9840 via I²C-bus. Also the data byte of the switch

register (see Table 7) must be changed, because the

AF outputs are muted.

Stereo: −0.89/+1.15 Hz

Dual: ±2.05 Hz.

If the integration time of the integrator is switched from one

mode to the other (i.e. from fast mode/test mode to normal

mode), the status register bits D5 and D6 might set to zero

internally (MONO). Therefore, the previous status register

information has to be stored by the microcontroller until the

transmitter status is detected again by the identification

circuit (now in the new mode) the first time.

The data byte of the test register can be reset in two

different ways to (00)_HEX: integration time approximately

1 s, normal mode:

• after a power-on reset, for instance by switching the

power supply V_poff and on again

• data transmission via I²C-bus for the test register

(see Table 12).

1998 Jul 03

15

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

I²C-BUS FORMAT

X is the read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave

transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed.

Table 2 I²C-bus; SLAVE ADDRESS/SUBADDRESS/DATA format

S

SLAVE ADDRESS

A

SUBADDRESS

A

DATA

P

Table 3 Explanation of Table 2

BIT

FUNCTION

S

start condition

SLAVE ADDRESS

1000 010X

A

acknowledge, generated by the slave

dual sound A/B

SUBADDRESS

DATA

P

data byte; see Table 6

stop condition

Table 4 I²C-bus; SLAVE ADDRESS/DATA to read the status byte (X = 1 in the address byte)

DATA

SLAVE

FUNCTION

ADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

Status byte

1000 0101

PONRES

ST

DS

0

Table 5 Explanation of Table 4

BIT

FUNCTION

PONRES = 0

PONRES = 1

ST = 0; DS = 0

ST = 0; DS = 1

ST = 1; DS = 0

ST = 1; DS = 1

after a successful reading of the status register

after power-on reset or after supply breakdown

MONO sound identified

DUAL sound identified

STEREO sound identified

incorrect identification

1998 Jul 03

16

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Table 6 I²C-bus; SUBADDRESS/DATA for writing (X = 0 in the address byte)

DATA

FUNCTION

Switching

SUBADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

0000 0000

0000 0001

0

SW6

0

SW5

0

SW4

0

SW3

0

SW2

0

SW1

0

SW0

0

Without function

(note 1)

Level adjustment

Stereo adjustment

0000 0010

0000 0011

0

LV3

ST3

LV2

ST2

LV1

ST1

LV0

ST0

ST5

ST4

Note

1. This byte is acknowledged by the TDA9840.

Function of the bits:

• SW6 to SW0 input and output AF selection; see Table 7

• LV3 to LV0 level adjustment; see Table 10

• ST5 to ST0 stereo adjustment; see Table 11.

Table 7 Data byte to select AF inputs and AF outputs [subaddress (00)_HEX

INPUT SIGNAL OUTPUT SIGNAL

ST/DS/M EXT MAIN SCART

V_{i 1}V_{i 2}V_{i 3}V_{i 4}V_{o 1}V_{o 2}V_{o 3}V_{o 4}

]

DATA

TRANSMISSION

MODE

PIN PIN PIN PIN PIN PIN PIN PIN D7 D6 D5 D4 D3 D2 D1 D0 HEX

7

8

9

10 14 13 12 11

Sound mute

MONO

−

M

S

A

−

C

−

D

no signal

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

10

2A

12

1A

16

1E

7A

M

ST

M

S

L

M

S

R

B

D

M

S

L

M

S

R

A

B

A

B

D

STEREO

R

B

−

DUAL

DS

A

C

A

B

C

External

−

Table 8 Explanation of Table 7

SIGNAL DESCRIPTION

SIGNAL

DESCRIPTION

R

L

right

left

C

NICAM or AM sound (standard L)

NICAM

D

S

M

mono sound

(L + R)

--------------------

2

DS

ST

dual sound

stereo sound

A and B

dual sound A/B

1998 Jul 03

17

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Table 9 AF switch conﬁguration

INPUT

OUTPUT

TRANSMITTER STATUS

MONO

SIGNAL

MAIN

SCART

M

STEREO

DUAL

L

R

A

B

C

D

L or M

R or M

A or B

C

R or M

A

B

C

D

External

D

Table 10 Data byte to select level adjustment [subaddress (02)_HEX

]

DATA

D3

∆G_V(dB)

+2.5

D7

D6

D5

D4

D2

D1

D0

HEX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0D

0C

0B

0A

09

00

01

02

03

04

+2.0

+1.5

+1.0

+0.5

0

−0.5

−1.0

−1.5

−2.0

1998 Jul 03

18

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Table 11 Data byte to select stereo adjustment

[subaddress (03)_HEX

]

DATA

D7 D6 D5 D4 D3 D2 D1 D0 HEX

∆G_V

(dB)

∆G_V

(dB)

D7 D6 D5 D4 D3 D2 D1 D0 HEX

+2.5

+2.4

+2.3

+2.2

+2.1

+2.0

+1.9

+1.8

+1.7

+1.6

+1.5

+1.4

+1.3

+1.2

+1.1

+1.0

+0.9

+0.8

+0.7

+0.6

+0.5

+0.4

+0.3

+0.2

+0.1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

39

38

37

36

35

34

33

32

31

30

2F

2E

2D

2C

2B

2A

29

28

27

26

25

24

23

22

21

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

−0.1

−0.2

−0.3

−0.4

−0.5

−0.6

−0.7

−0.8

−0.9

−1.0

−1.1

−1.2

−1.3

−1.4

−1.5

−1.6

−1.7

−1.8

−1.9

−2.0

−2.1

−2.2

−2.3

−2.4

Table 12 Data byte to select integration time [subaddress (04)_HEX

]

DATA

FUNCTION

Test byte

SUBADDRESS

D7

D6

D5

D4

D3

D2

D1

D0

0000 0100

X

INTFU INT1SN

Function of the bits:

• INTFU = 0 integrator function enabled

• INTFU = 1 integrator function disabled

• INT1SN = 0 integration time approximately 1 s (default)

• INT1SN = 1integration time approximately 0.5 s.

1998 Jul 03

19

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

MED647

+2

V

R: −15%;

C: −5%

oAF

(dB)

+1

0

−1

−2

R: +15%;

C: +5%

2

3

4

5

10

f

(Hz)

oAF

Fig.4 Tolerance scheme of AF frequency response; de-emphasis with C_D1, C_D2= 10 nF (±5%),

R_internal= 5 kΩ (±15%).

1998 Jul 03

20

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

handbook, full pagewidth

SDA

SCL

1

2

3

20

19

18

10 MHz

10 µF

10 nF

C

XTAL

AGC

LP

100 µF/16 V

V

P

C

VP

C

ref

10 µF

100 nF

DCL

5%

C

50 µs

de-emphasis

1/2 V

4

17

16

15

14

13

12

P

D2 10 nF

5

2.5

mH

3.3

nF

TDA9840

47 pF

5%

50 µs

de-emphasis

6

C

D1 10 nF

30 kΩ

2.2 µF

V

AF from 5.5 MHz

AF from 5.742 MHz

7

V

i 1

i 2

i 3

i 4

o 1

main

scart

2.2 µF

V

8

o 2

from external sound source C

from external sound source D

9

V

o 3

o 4

10

11

MBE460

Fig.5 Test circuit of the stereo decoder TDA9840.

V

handbook, full pagewidth

o 1

14

13

V

o 2

V

measurements

on outputs

V

B

P

V

18

o 3

TDA9840

12

11

V

o 4

10 k

Ω

8

6

7

9

10

16

100 µF

5 V modulated

with 200 mV (p-p)

100 µF /

100 µF

16 V

70 Hz

MBE462

Fig.6 Test circuit for measurement of ripple rejection.

21

1998 Jul 03

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

INTERNAL CIRCUITRY

handbook, full pagewidth

+

2 kΩ

20

19

1

SCL

SDA

+

XTAL

–

+

3 pF

13 kΩ

+5 V

18

17

5 kΩ

V

P

+

–

68 µA

25 kΩ

5 kΩ

C

2

3

+

D2

C

AGC

+

–

+

C

GND

LP

16

15

25 kΩ

40 µA

+

1/2 V

4

P

60 µA

+

–

5 kΩ

C

D1

DCL

+

25 kΩ

–

+

40 µA

5 kΩ

5

6

+

V

i pil

C

ref

14

V

o 1

22.5 kΩ

I

B

5 kΩ

+

200 µA

10 kΩ

25 kΩ

TDA9840

–2 dB

7

8

9

V

i 1

13

40 kΩ

V

I

o 2

B

AF outputs

1/2 V

P

–2 dB

200 µA

V

i 2

+

40 kΩ

AF inputs

12

+

1/2 V

V

P

o 3

–6 dB

V

i 3

25 kΩ

200 µA

1/2 V

P

11

25 kΩ

V

–6 dB

10

o 4

V

i 4

25 kΩ

1/2 V

I

B

200 µA

P

MBE461

V

P

ESD protection diode

for pins 2 to 15, 17 and 19

zener diode protection

for pins 1, 18 and 20

Fig.7 Internal circuits.

1998 Jul 03

22

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

PACKAGE OUTLINES

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

M

H

20

11

pin 1 index

E

1

10

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

(1)

Z

1

2

UNIT

mm

b

c

D

E

e

1

L

M

H

w

1

E

max.

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

26.92

26.54

6.40

6.22

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.10

7.62

0.30

0.254

0.01

2.0

0.068

0.051

0.021

0.015

0.014

0.009

1.060

1.045

0.25

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.020

0.13

0.078

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

92-11-17

95-05-24

SOT146-1

SC603

1998 Jul 03

23

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

mm

2.65

0.25

0.01

1.27

0.050

1.4

0.25 0.25

0.01

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches 0.10

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-01-24

97-05-22

SOT163-1

075E04

MS-013AC

1998 Jul 03

24

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

WAVE SOLDERING

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering

technique should be used.

DIP

• The longitudinal axis of the package footprint must be

parallel to the solder flow.

SOLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

• The package footprint must incorporate solder thieves at

the downstream end.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_{stg max}). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

6 seconds. Typical dwell time is 4 seconds at 250 °C.

REPAIRING SOLDERED JOINTS

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not

more than 2 mm above it. If the temperature of the

soldering iron bit is less than 300 °C it may remain in

contact for up to 10 seconds. If the bit temperature is

between 300 and 400 °C, contact may be up to 5 seconds.

REPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

SO

REFLOW SOLDERING

Reflow soldering techniques are suitable for all SO

packages.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

1998 Jul 03

25

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1998 Jul 03

26

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I²C-bus control

TDA9840

NOTES

1998 Jul 03

27

Philips Semiconductors – a worldwide company

Argentina: see South America

Middle East: see Italy

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Fax. +43 160 101 1210

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

Norway: Box 1, Manglerud 0612, OSLO,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belgium: see The Netherlands

Brazil: see South America

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Portugal: see Spain

Romania: see Italy

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Colombia: see South America

Czech Republic: see Austria

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. +65 350 2538, Fax. +65 251 6500

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

Slovakia: see Austria

Slovenia: see Italy

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Spain: Balmes 22, 08007 BARCELONA,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545104/00/03/pp28

Date of release: 1998 Jul 03

Document order number: 9397 750 03999


型号：	TDA9840TD-T
厂家：	NXP
描述：	暂无描述消费电路商用集成电路录像机电视光电二极管
文件：	总28页 (文件大小：204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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