PLL520-19 [PLL]
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal); 低相位噪声压控与乘数（为65-130MHz基金XTAL）
| 型号： | PLL520-19 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) |
| 文件： | 总7页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
PIN CONFIGURATION
•
•
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS.
Integrated variable capacitors.
VDD
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
•
•
•
•
•
XOUT
SEL3^
SEL2^
OE
CLKC
VDD
Supports 3.3V-Power Supply.
Available in 16 pin (TSSOP or SOIC)
CLKT
GND
VCON
GND
GND
DESCRIPTION
^: Internal pull-up
The PLL520-17/-18/-19 family of VCXO IC’s is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default) Output enabled
PLL520-18
1
0
Tri-state
Tri-state
PLL520-17
PLL520-19
1 (Default) Output enabled
BLOCK DIAGRAM
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
SEL
OE
Q
PLL
Oscillator
Amplifier
w/
(Phase
Locked
Loop)
VCON
Q
XIN
integrated
varicaps
XOUT
PLL by-pass
PLL520-17/-18/-19
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
PIN DESCRIPTIONS
Name
Number
Type
Description
XIN
XOUT
OE
2
I
I
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Output enable. See Output Enable Logic Levels on page 1.
Voltage control input.
3
6
I
VCON
GND
7
I
8,9, 10, 14
P
Ground.
True output PECL (PLL520-18) or LVDS (PLL520-19).
No Connect for CMOS (PLL520-17).
Complementary output PECL (PLL520-18) or LVDS (PLL520-19).
CMOS output for (PLL520-17).
CLKT
CLKC
11
13
O
O
Multiplier selector pins. These pins have an internal pull-up that will
default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
SEL
4,5,15,16
1, 12
I
VDD
P
FREQUENCY SELECTION TABLE
Pin #4
SEL3
Pin #5
SEL2
Pin #15
SEL1
Pin #16
SEL0
Selected Multiplier
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
Fin x 8
Fin x 4
Fin x 2
No multiplication
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
Output Voltage, dc
Storage Temperature
-0.5
-0.5
-65
V
VO
TS
TA
TJ
V
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
CX+
CX-
C0
2
2
Built-in Capacitance
65MHz to 130MHz
(VDD=3.3V)
pF
Inter-electrode capacitance
C0/C1 ratio (gamma)
2
300
200
-
γ
Oscillation Frequency
OF
Fund.
120
MHz
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
From power valid
10
ms
FXIN = 100 – 200MHz;
XTAL C0/C1 < 250
0V ≤ VCON ≤ 3.3V
VCXO Tuning Range
200*
ppm
CLK output pullability
On-chip Varicaps control range
Linearity
ppm
pF
VCON=1.65V, ±1.65V
±100*
VCON = 0 to 3.3V
4 – 18*
10*
%
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
65
60
ppm/V
kΩ
25
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
Operating Voltage
IDD
PECL/LVDS/CMOS
100/80/40
3.63
mA
V
VDD
2.97
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock Duty Cycle
Short Circuit Current
%
mA
±50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
5. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
77.76MHz
155.52MHz
622.08MHz
77.76MHz
155.52MHz
622.08MHz
2.5
4
Period jitter RMS
ps
5
24
29
32
0.5
1.5
1.5
Period jitter peak-to-peak
Integrated jitter RMS
ps
ps
Integrated 12 kHz to 20 MHz at 77.76MHz
Integrated 12 kHz to 20 MHz at 155.52MHz
Integrated 12 kHz to 20 MHz at 622.08MHz
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
77.76MHz
155.52MHz
622.08MHz
-75
-75
-75
-95
-95
-95
-125
-120
-115
-145
-125
-118
-155
-123
-115
Phase Noise relative
to carrier
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Output Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
IOL
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
30
30
10
10
mA
mA
mA
mA
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
8. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
9. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
tf
0.2
0.7
1.0
ns
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Fall Time
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
10. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
VDD – 1.025
Output High Voltage
Output Low Voltage
VOH
VOL
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
11. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
2.0V
OUT
50
50
Ω
Ω
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC
TSSOP
E
H
Symbol
Min.
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
Max.
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
Min.
-
Max.
1.20
0.15
0.30
0.20
5.10
4.50
A
A1
B
C
D
E
H
L
e
0.05
0.19
0.09
4.90
4.30
D
6.40 BSC
0.75
0.65 BSC
A
0.45
A
1
C
1.27 BSC
L
B
e
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-1x O C
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PART NUMBER
PACKAGE TYPE
O=TSSOP S=SOIC
Order Number
Marking
Package Option
PLL520-17OC
PLL520-17OC-R
PLL520-17SC
PLL520-17SC-R
P520-17OC
P520-17OC
P520-17SC
P520-17SC
TSSOP – Tube
TSSOP – Tape & Reel
SOIC – Tube
SOIC – Tape & Reel
PLL520-18OC
PLL520-18OC-R
PLL520-18SC
PLL520-18SC-R
P520-18OC
P520-18OC
P520-18SC
P520-18SC
TSSOP – Tube
TSSOP – Tape & Reel
SOIC – Tube
SOIC – Tape & Reel
PLL520-19OC
PLL520-19OC-R
PLL520-19SC
PLL520-19SC-R
P520-19OC
P520-19OC
P520-19SC
P520-19SC
TSSOP – Tube
TSSOP – Tape & Reel
SOIC – Tube
SOIC – Tape & Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7
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