HYS64D32000EDL-5-D [QIMONDA]
DDR DRAM Module, 32MX64, 0.7ns, CMOS, GREEN, SODIMM-200;
| 型号： | HYS64D32000EDL-5-D |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 32MX64, 0.7ns, CMOS, GREEN, SODIMM-200 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总29页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2009
HYS64D[32/64]0x0EDL–5–D
HYS64D[32/64]0x0EDL–6–D
200-Pin Small-Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
HYS64D[32/64]0x0EDL–5–D, HYS64D[32/64]0x0EDL–6–D
Revision History: 2009-01, Rev. 1.00
Page
Subjects (major changes since last revision)
All
Metadata change and document adapted to internet edition.
Previous Revision: Rev. 0.60, 2008-05
All
Added product type HYS64D32000EDL-[5/6]-D
Previous Revision: Rev. 0.50, 2007-09
All
New Document.
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05282008-IARQ-5WHU
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
1
Overview
This chapter contains features and the description.
1.1
Features
•
•
•
•
•
Non-parity 200-Pin Small-Outline Dual-In-Line Memory
Modules
One rank 32M × 64, two ranks 64M × 64 module
organization and 32M × 64 chip organization
Industry standard Double-Data-Rate Synchronous
DRAMs (DDR SDRAM)
Single +2.5 V (± 0.2 V) power supply and +2.6 V (± 0.1 V)
for DDR400
Built with 512-Mbit DDR SDRAMs organised as ×16 in
packages P–TSOPII–66
•
Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
Industry standard form factor:
67.60 mm × 31.75 mm × 3.80 mm
Industry standard reference layout Raw Cards ’A’
DDR400 speed grade supported
•
•
•
•
•
•
•
Gold plated contacts
TABLE 1
Performance for –5 and –6
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
Module
@CL3
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
—
max. Clock
Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1.2
Description
The
HYS64D[32/64]0x0EDL–5–D
and
a serial E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
HYS64D[32/64]0x0EDL–6–D are industry standard 200-Pin
Small-Outline Dual-In-Line Memory Modules (SO-DIMMs)
organized as 32M ×64 and 64M ×64. The memory array is
designed with Double-Data-Rate Synchronous DRAMs (DDR
SDRAM). A variety of decoupling capacitors are mounted on
the PCB. The DIMMs feature serial presence detect based on
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
TABLE 2
Odering Information for Lead-Free (RoHS Compliant Products)
Product Type
Compliance Code
Description
SDRAM Technology Note1)
PC3200 (CL=3.0)
HYS64D32000EDL-5-D
HYS64D64020EDL-5-D
PC2700 (CL=2.5)
PC3200S–3033–1–C1 one rank 256MB SO-DIMM 512 MBit (×16)
PC3200S–3033–1–A1 two ranks 512MB SO-DIMM 512 MBit (×16)
HYS64D32000EDL-6-D
HYS64D64020EDL-6-D
PC2700S–2533-1–C1 one rank 256MB SO-DIMM 512 MBit (×16)
PC2700S–2533-1–A1 two ranks 512MB SO-DIMM 512 MBit (×16)
1) RoHS: Restriction of the use of certain hazardous substances in electrical and electronic equipment as defined in the directive 2002/95/EC
issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent
chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Note: All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D64020EDL–5–D, indicating Rev.B die are used for SDRAM components.The Compliance Code is
printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example “30330”
means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks),
JEDEC SPD code definition version 1, and the Raw Card used for this module.
TABLE 3
Address Format
Density Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
512MB
256MB
64M ×64
32M ×64
2
1
32M ×16
32M ×16
8
4
13/2/10
13/2/10
8K
8K
64 ms
64 ms
7.8 μs
7.8 μs
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR
SDRAM DIMM is listed by function in Table 4 (200 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 5 and Table 6 respectively. The pin
numbering is depicted in Figure 1.
TABLE 4
Pin Configuration of SO-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
35
CK0
CK1
CK2
I
I
I
SSTL
SSTL
SSTL
Clock Signal
160
89
Clock Signal
Clock Signal
Note: ECC type module
Note: non-ECC type module
Complement Clock
Complement Clock
Complement Clock
Note: ECC type module
Note: non-ECC type module
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
NC
NC
–
37
CK0
CK1
CK2
I
I
I
SSTL
SSTL
SSTL
158
91
NC
NC
–
96
95
CKE0
CKE1
I
I
SSTL
SSTL
NC
NC
–
Control Signals
121
122
S0
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
S1
NC
NC
–
118
120
119
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Address Signals
117
116
112
111
110
109
108
107
106
105
102
101
115
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 11:0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
100
99
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: 128 Mbit based module
Address Signal 13
NC
NC
I
–
123
A13
SSTL
Note: 1 Gbit based module
NC
NC
–
Note: Module based on 512 Mbit or smaller dies
Data Signals
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
7
13
17
6
8
14
18
19
23
29
31
20
24
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
30
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
172
176
177
181
187
189
178
182
188
190
71
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Check Bit 0
Note: ECC type module
Note: Non-ECC module
Check Bit 1
NC
NC
I/O
–
73
79
83
72
74
80
84
CB1
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 2
NC
NC
I/O
–
CB2
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 3
NC
NC
I/O
–
CB3
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 4
NC
NC
I/O
–
CB4
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 5
NC
NC
I/O
–
CB5
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 6
NC
NC
I/O
–
CB6
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 7
NC
NC
I/O
–
CB7
SSTL
Note: ECC type module
Note: Non-ECC module
NC
NC
–
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
11
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes 7:0
Note: See block diagram for corresponding DQ
signals
25
47
61
133
147
169
183
77
Data Strobe 8
Note: ECC type module
Note: Non-ECC module
Data Mask 7:0
NC
NC
–
12
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
26
48
62
134
148
170
184
78
Data Mask 8
Note: ECC type module
Note: Non-ECC module
NC
NC
–
EEPROM
195
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
193
I/O
Serial Bus Data
194
I
I
I
CMOS
CMOS
CMOS
Slave Address Select Bus 2:0
196
198
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Power Supplies
1,2
VREF
VDDSPD
VDD
AI
–
–
–
I/O Reference Voltage
EEPROM Power Supply
Power Supply
197
PWR
PWR
9,10,21,
22,
33,
34,
36,
45,
46,
57,
58,
69,
70,
81,
82,
92,
93,
94,
113,
114,
131,
132,
143,
144,
155,
156,
157,
167,
168,
179,
180,
191,
192
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
3,4,
VSS
GND
–
Ground Plane
15,
16,
27,
28,
38, 39, 40,
51,
52,
63,
64,
75,
76,
87,
88, 90, 103,
104,
125,
126,
137,
138,
149,
150,
159,
161,
162,
173,
174,
185,
186
Other Pins
199
VDDID
O
OD
–
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets
connected on PCB
85,
NC
NC
Not connected
86, 97, 98,
124,
Note: Pins not connected on Infineon SO DIMMs
200
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.00, 2009-01
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05282008-IARQ-5WHU
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Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
FIGURE 1
Pin Configuration Diagram 200-Pin SO-DIMM
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Rev. 1.00, 2009-01
05282008-IARQ-5WHU
13
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test
Condition
min.
typ. max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
–
V
DDQ + 0.5
V
–
–
–
–
–
–
–
–
–
+3.6
+3.6
+3.6
+70
+150
–
V
VDD
–
V
VDDQ
TA
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note/Test Condition1)
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fCK ≤ 166 MHz
f
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
VDD
VDDQ
VDDQ
VDDSPD
fCK > 166 MHz 2)3)
—
—
Supply Voltage, I/O Supply VSS, VSSQ
Voltage
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
REF – 0.04 REF + 0.04
V
V
I/O Termination Voltage
(System)
V
V
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition1)
Min.
Max.
6)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
V
V
V
DDQ + 0.3
V
6)
–0.3
–0.3
REF – 0.15
DDQ + 0.3
V
6)
Input Voltage Level, CK and VIN(DC)
V
CK Inputs
6)7)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
0.71
–2
V
DDQ + 0.6
V
8)
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
Input Leakage Current
Output Leakage Current
II
μA
μA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V9)
IOZ
–5
5
DQs are disabled; 0 V ≤ VOUT
VDDQ
≤
9)
Output High Current, Normal IOH
Strength Driver
–16.2
16.2
—
—
mA VOUT
=
1.95 V
Output Low Current, Normal IOL
mA VOUT = 0.35 V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V;
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ
5) TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
6) Inputs are not recognized as valid until VREF stabilizes.
7) ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
.
V
.
V
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
3.2
Current Specification and Conditions
This chapter describes the Specifications and Conditions.
TABLE 9
DD Conditions
I
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
TABLE 10
DD Specification for HYS64D64020EDL–[5/6]–D
I
Unit
Note 1)2)
512MB
×64
512MB
×64
2 Ranks
–5
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
3)
IDD0
228
260
8
294
330
37
196
224
8
258
290
37
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
176
120
64
240
176
112
296
370
358
602
32
160
112
64
216
160
112
272
326
314
522
32
5)
5)
5)
232
296
284
496
12
208
256
248
444
12
3)4)
3)
5)
5)
IDD6
3)4)
IDD7
712
870
600
686
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD2P[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
TABLE 11
DD Specification for HYS64D32000EDL–[5/6]–D
I
Unit
Note 1)2)
256MB
×64
256MB
×64
1 Rank
–5
1 Rank
–6
Symbol
Typ.
Max.
Typ.
Max.
3)
IDD0
224
256
4
276
312
18
192
220
4
240
272
18
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
88
120
88
80
108
80
5)
60
56
5)
32
56
32
56
5)
116
292
280
492
6
148
352
340
584
16
104
252
244
440
6
136
308
296
504
16
3)4)
3)
5)
5)
IDD6
3)4)
IDD7
708
852
596
668
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD2P[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
TABLE 12
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.55
12
0.45
6
0.55
12
tCK
5
ns
ns
ns
tCK
tCK
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
6
12
7
12
7.5
0.45
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery + tDAL
(tWR/tCK) + (tRP/tCK)
precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
tCK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
latching transition
tDQSQ
tDQSS
tDS
+0.40
1.25
+0.45
1.25
TSOPII 2)3)4)5)
2)3)4)5)
0.72
0.75
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
tCK
CK (write cycle)
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
Min. (tCL, tCH
)
—
Min. (tCL, tCH
)
—
ns
ns
2)3)4)5)7)
Data-out high-impedance time
from CK/CK
+0.7
–0.7
+0.7
Address and control input hold
time
tIH
0.6
0.7
2.2
—
—
—
0.75
0.8
—
—
—
ns
ns
ns
Fast slew rate
3)4)5)6)10)
Slow slew rate
3)4)5)6)10)
2)3)4)5)8)
Control and Addr. input pulse
width (each input)
tIPW
2.2
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition1)
DDR333
Min.
Max.
Min.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
ns
tCK
Fast slew rate
3)4)5)6)9)
0.7
–0.7
2
—
0.8
–0.7
2
—
Slow slew rate
3)4)5)6)10)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time
from CK/CK
tLZ
+0.7
—
+0.7
—
Mode register set command
cycle time
tMRD
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP – tQHS
—
t
HP – tQHS
—
ns
ns
ns
tQHS
tRAP
tRAS
tRC
—
+0.50
—
—
+0.55
—
TSOPII 2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRCD
40
tRCD
2)3)4)5)
2)3)4)5)
70E+3 42
70E+3 ns
Active to Active/Auto-refresh
command period
55
—
60
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
—
18
—
—
ns
2)3)4)5)10)
Average Periodic Refresh
Interval
7.8
7.8
μs
2)3)4)5)
Auto-refresh to Active/Auto-
refresh command period
tRFC
70
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
0.60
—
0.40
15
0.60
—
tCK
ns
Write recovery time
2)3)4)5)
Internal write to read command tWTR
2
—
1
—
tCK
delay
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
tXSRD
75
—
—
75
—
—
ns
Exit self-refresh to read
command
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
.
t
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VOH(ac) and VOL(ac)
.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
Table 13 “HYS64D[32/64]3x0EDL-[5/6]-D” on Page 22
TABLE 13
HYS64D[32/64]3x0EDL-[5/6]-D
Product Type
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 2 Ranks
(×16)
2 Ranks
(×16)
Label Code
PC3200S–
30331
PC2700S–
25331
PC3200S–
30331
PC2700S–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
80
08
07
0D
0A
01
40
00
04
50
70
00
82
10
80
08
07
0D
0A
01
40
00
04
60
70
00
82
10
80
08
07
0D
0A
02
40
00
04
50
70
00
82
10
80
08
07
0D
0A
02
40
00
04
60
70
00
82
10
1
2
3
4
5
6
7
Data Width (MSB)
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
9
10
11
12
13
Primary SDRAM Width
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Product Type
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 2 Ranks
(×16)
2 Ranks
(×16)
Label Code
PC3200S–
30331
PC2700S–
25331
PC3200S–
30331
PC2700S–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Error Checking SDRAM Width
00
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
40
60
60
40
40
00
37
41
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
00
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
40
60
60
40
40
00
37
41
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
30
48
2A
40
75
75
45
45
00
3C
48
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
t
t
RPmin [ns]
RRDmin [ns]
tRCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
t
AH, tCH [ns]
DS [ns]
tDH [ns]
36 - 40 Not used
41
42
t
RCmin [ns]
tRFCmin [ns]
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HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Product Type
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 2 Ranks
(×16)
2 Ranks
(×16)
Label Code
PC3200S–
30331
PC2700S–
25331
PC3200S–
30331
PC2700S–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
43
44
45
46
47
tCKmax [ns]
28
28
50
00
01
00
10
76
7F
7F
7F
7F
7F
51
00
00
xx
30
2D
55
00
01
00
10
1A
7F
7F
7F
7F
7F
51
00
00
xx
28
28
50
00
01
00
10
77
7F
7F
7F
7F
7F
51
00
00
xx
30
2D
55
00
01
00
10
1B
7F
7F
7F
7F
7F
51
00
00
xx
t
t
DQSQmax [ns]
QHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
33
32
30
30
30
36
34
44
33
32
30
30
30
36
34
44
36
34
30
32
30
36
34
44
36
34
30
32
30
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Rev. 1.00, 2009-01
24
05282008-IARQ-5WHU
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Product Type
Organization
256MB
256MB
512MB
512MB
×64
×64
×64
×64
1 Rank (×16) 1 Rank (×16) 2 Ranks
(×16)
2 Ranks
(×16)
Label Code
PC3200S–
30331
PC2700S–
25331
PC3200S–
30331
PC2700S–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 9
45
44
4C
35
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
45
44
4C
36
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
45
44
4C
35
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
45
44
4C
36
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.00, 2009-01
25
05282008-IARQ-5WHU
ꢇꢍ
ꢆ
ꢀ0
$;ꢀꢀ
ꢁꢍꢅꢀꢀ
ꢀꢀ
ꢄꢇꢍ
ꢄ
ꢅꢀꢀ
ꢅꢋꢋꢀꢀ
ꢎꢃꢍ
ꢅꢊꢏꢀꢀ
ꢎꢃꢍꢂꢊꢏꢀꢀ
ꢁ
ꢍꢅ
ꢀꢀ
ꢁꢍꢅꢀꢀ
ꢆꢍꢂꢊꢀꢀ
ꢅꢀꢀ
ꢅ
ꢁ
ꢍ
ꢅꢀꢀ
ꢅꢍꢆ
ꢎꢃ
ꢀꢀ
ꢍ
ꢂꢏꢀꢀ
ꢁꢂꢃꢀꢀ
ꢀꢀ
ꢃ
ꢃꢂꢄ
ꢁꢍꢅꢀꢀ
ꢀꢀ
ꢂꢉꢍ
ꢂ
ꢎꢃꢍꢉꢏꢀꢀ
ꢎꢃꢍꢅꢊꢏꢀꢀ
ꢎꢃꢍ
ꢂꢊꢏꢀꢀ
ꢁꢍꢅꢀꢀ
ꢀꢀ
ꢅꢍ
ꢊ
ꢁ
ꢍ
ꢅꢀꢀ
ꢃꢀꢀ
ꢃꢁꢁꢀꢀ
ꢃꢀ0,1ꢍꢀꢀ
'HWD
LO
ꢀRI
ꢀFR
Q
W
D
FWV
ꢀꢀ
ꢁꢍ
ꢂꢊꢀꢀ
ꢁꢇꢀꢀ
ꢁꢍ
ꢁꢍꢅ
ꢁꢍꢄꢀꢀ
ꢀꢀ
%XUQLVKHGꢐꢀ
QR
ꢀEXUU
ꢀ
DOORZHG
ꢀꢀ
*
/'ꢁ
ꢋꢊ
ꢄꢆꢀꢀ
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 2
Package Outline SO-DIMM Raw Card A (L-DIM-200-6)
ꢄꢉꢍꢄꢀꢀ
ꢅꢀꢀ
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/-0.15
Rev. 1.00, 2009-01
26
05282008-IARQ-5WHU
ꢃꢍꢂꢀ
0$;ꢍꢀ
ꢄꢇꢍꢄꢀ
ꢅꢀ
ꢅꢋꢋꢀ
ꢎꢃꢍꢅꢊꢏꢀ
ꢎ
ꢃꢍꢂꢊꢏꢀ
ꢅꢀ
ꢁꢍ
ꢅꢀ
ꢁꢍꢅꢀ
ꢅꢆꢍꢂꢊꢀ
ꢀ
ꢁꢍꢅꢀ
ꢅꢍꢆ
ꢎ
ꢃꢍꢂꢏꢀ
ꢁꢍꢅꢀ
ꢅꢍꢂꢀ
ꢅ
ꢁꢍꢅꢀ
ꢂꢉꢍꢂꢀ
ꢎ
ꢃꢍꢉꢏꢀ
ꢎ
ꢅꢊꢏꢀ
ꢃꢍ
ꢎ
ꢃꢍꢂꢊꢏꢀ
ꢁꢍꢅꢀ
ꢊꢀ
ꢅꢍ
ꢅꢀ
ꢁꢍꢅꢀ
ꢃꢀ
ꢃꢁꢁꢀ
ꢃꢀ0
,1
ꢍꢀ
I
'
H
WD
L
OꢀR
ꢀF
WD
FWVꢀ
RQ
ꢁꢍꢂꢊꢀ
ꢁꢍꢁꢇꢀ
ꢁꢍꢅꢀ
ꢁꢍꢄꢀ
%XU
L
KHGꢐꢀQRꢀ
EXU
ꢀDOORZHG
ꢀ
*/
'ꢁꢋ
ꢊꢉ
Q V
U
ꢁꢀ
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
FIGURE 3
Package Outline SO-DIMM Raw Card C (L-DIM-200-11)
ꢄꢉꢍꢄꢀ
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.00, 2009-01
27
05282008-IARQ-5WHU
Internet Data Sheet
HYS64D[32/64]0x0EDL–[5/6]–D
Small-Outline DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
4
5
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Rev. 1.00, 2009-01
28
05282008-IARQ-5WHU
Internet Data Sheet
Edition 2009-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2009.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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