ISL6420AIR_技术文档

Advanced Single Synchronous Buck Pulse-Width

Modulation (PWM) Controller

ISL6420A

Features

• Operates From:

- 4.5V to 5.5V Input

- 5.5V to 28V Input

The ISL6420A simplifies the implementation of a

complete control and protection scheme for a

high-performance DC/DC buck converter. It is designed

to drive N-Channel MOSFETs in a synchronous rectified

buck topology. The ISL6420A integrates control, output

adjustment, monitoring and protection functions into a

single package. Additionally, the IC features an

external reference voltage tracking mode for externally

referenced buck converter applications and DDR

termination supplies, as well as a voltage margining

mode for system testing in networking DC/DC

converter applications.

• 0.6V Internal Reference Voltage

- ±1.0% Reference Accuracy

• Resistor-Selectable Switching Frequency

- 100kHz to 1.4MHz

• Voltage Margining and External Reference Tracking

Modes

• Output can Sink or Source Current

The ISL6420A provides simple, single feedback loop,

voltage mode control with fast transient response. The

output voltage of the converter can be precisely

regulated to as low as 0.6V.

• Lossless, Programmable Overcurrent Protection

- Uses Upper MOSFET’s r

DS(ON)

• Programmable Soft-Start

• Drives N-Channel MOSFETs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

The operating frequency is fully adjustable from

100kHz to 1.4MHz. High frequency operation offers

cost and space savings.

The error amplifier features a 15MHz gain-bandwidth

product and 6V/µs slew rate that enables high

converter bandwidth for fast transient response. The

PWM duty cycle ranges from 0% to 100% in transient

conditions. Selecting the capacitor value from the

ENSS pin to ground sets a fully adjustable PWM

soft-start. Pulling the ENSS pin LOW disables the

controller.

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Extensive Circuit Protection Functions

- PGOOD, Overvoltage, Overcurrent, Shutdown

• Diode Emulation during Startup for Pre-Biased

Load Applications

The ISL6420A monitors the output voltage and

generates a PGOOD (power good) signal when

soft-start sequence is complete and the output is

within regulation. A built-in overvoltage protection

circuit prevents the output voltage from going above

typically 115% of the set point. Protection from

overcurrent conditions is provided by monitoring the

• Offered in 20 Ld QFN and QSOP Packages

• QFN (4x4) Package

- QFN compliant to JEDEC PUB95 MO-220

QFN -Quad Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint;

Improves PCB Efficiency, Thinner in Profile

r

of the upper MOSFET to inhibit the PWM

DS(ON)

• Pb-Free (RoHS Compliant)

operation appropriately. This approach simplifies the

implementation and improves efficiency by eliminating

the need for a current sensing resistor.

Applications

• Power Supplies for Microprocessors/ASICs

- Embedded Controllers

- DSP and Core Processors

- DDR SDRAM Bus Termination

• Ethernet Routers and Switchers

• High-Power DC/DC Regulators

• Distributed DC/DC Power Architecture

• Personal Computer Peripherals

• Externally Referenced Buck Converters

December 4, 2009

FN9169.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6420A

Ordering Information

PART NUMBER

(Notes 2, 3)

PART

MARKING

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6420AIAZ

6420 AIAZ

-40 to +85

20 Ld QSOP

M20.15

ISL6420AIAZ-TK (Note 1)

ISL6420AIRZ

6420 AIAZ

64 20AIRZ

20 Ld QSOP (Tape and Reel)

20 Ld 4x4 QFN

M20.15

L20.4x4

ISL6420AIRZ-TK (Note 1)

20 Ld 4x4 QFN (Tape and Reel) L20.4x4

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6240A For more information on MSL please

see techbrief TB363.

Pin Configurations

ISL6420A

(20 LD QFN)

TOP VIEW

ISL6420A

(20 LD QSOP)

TOP VIEW

1

PGOOD

ENSS

CDEL

PGND

20

19

2

3

4

5

6

7

8

9

20 19 18 17 16

LGATE

18 COMP

17 FB

PVCC

GPIO2

GPIO1/REFIN

OCSET

1

2

3

4

5

15 PGND

14 CDEL

13 PGOOD

12 ENSS

11 COMP

PHASE

16 RT

UGATE

SGND

VIN

15

14

BOOT

GPIO2

13 VCC5

12

REFOUT

GPIO1/REFIN

VMSET/MODE

OCSET 10

11 REFOUT

6

7

8

9

10

FN9169.4

December 4, 2009

2

ISL6420A

Typical 5V Input DC/DC Application Schematic

5V ±10%

C

6

C

1

C

3

5

2

C

4

VCC5

VIN

PVCC

D

1

9

R

1

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q

1

C

UGATE

PHASE

PGOOD

CDEL

OSC

C

7

R

2

L

1

0.1µF

REF

V

OUT

C

8

SGND

FB

Q

LGATE

PGND

-

2

-

C

10

+

-

R

3

COMP

GPIO1/REFIN

GPIO2

C

11

R

6

C

R

12

5

C

13

VOLTAGE MARGINING ENABLED WITH INTERNAL V

SEE PAGE 12 FOR MORE DETAILS

R

REF

4

Typical 5.5V to 28V Input DC/DC Application Schematic

5.5V to 28V

C

6

C

1

C

5

3

2

C

4

VIN VCC5

PVCC

D

1

R

1

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q

1

UGATE

PHASE

C

9

PGOOD

CDEL

OSC

C

7

R

2

L

1

0.1µF

REF

V

OUT

C

8

SGND

FB

Q

LGATE

PGND

C

-

2

-

10

+

-

R

3

COMP

GPIO1/REFIN

GPIO2

C

R

11

R

6

C

12

5

C

13

R

4

VOLTAGE MARGINING ENABLED WITH INTERNAL V

SEE PAGE 12 FOR MORE DETAILS

REF

FN9169.4

December 4, 2009

4

ISL6420A

Typical 5V Input DC/DC Application Schematic

5V ±10%

C6

C

1

C

3

C

5

2

C

4

D

PVCC

VIN

VCC5

1

R

1

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q

1

C

8

CDEL

UGATE

PHASE

OSC

R

C

2

7

L

PGOOD

1

REF

2.5V/1.25V

SGND

FB

LGATE

PGND

Q

2

-

+

C

9

+

-

COMP

R

3

C

10

GPIO1/REFIN <-- V

REF

= VDDQ/2

1.25V V

REF

TO REFIN OF VTT SUPPLY

C

11

R

5

C

12

R

4

VCC5

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

Typical 5.5V to 28V Input DC/DC Application Schematic

5.5V to 28V

C

6

C

1

C

3

C

5

2

C

4

D

VIN

VCC5

PVCC

1

R

1

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q

1

C

UGATE

PHASE

8

CDEL

OSC

R

C7

2

L

PGOOD

1

REF

2.5V/1.25V

SGND

FB

Q

LGATE

PGND

2

-

+

C

9

+

-

R

3

COMP

C

10

GPIO1/REFIN <-- V

= VDDQ/2

REF

1.25V V

REF

TO REFIN OF VTT SUPPLY

11

R

5

R

4

VCC5

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

FN9169.4

December 4, 2009

5

ISL6420A

Typical 5V Input DC/DC Application Schematic

5V ±10%

C

6

C

1

C

5

3

2

C

4

VCC5

VIN

PVCC

D

1

R

1

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

PGOOD

CDEL

Q

1

C

9

UGATE

PHASE

OSC

C7

0.1µF

R

2

L

1

REF

V

OUT

C

8

SGND

FB

Q

LGATE

PGND

C

10

-

2

-

+

-

R

3

COMP

C

11

C

12

R

5

USE INTERNAL V

VOLTAGE MARGINING

SEE PAGE 12 FOR MORE DETAILS

WITH NO

REF

C13

R

4

Typical 5.5V to 28V Input DC/DC Application Schematic

5.5V to 28V

C

6

C

1

C

5

3

2

C

4

VCC5

VIN

PVCC

D

1

R

OCSET

BOOT

1

MONITOR AND

PROTECTION

ENSS

RT

Q

1

C

9

UGATE

PHASE

PGOOD

CDEL

OSC

C7

0.1µF

R

2

L

1

REF

V

OUT

C

8

SGND

Q

LGATE

PGND

-

2

C

10

-

+

F

B

+

-

COMP

R

3

C

11

C

12

R

5

USE INTERNAL V

VOLTAGE MARGINING

WITH NO

REF

SEE PAGE 12 FOR MORE DETAILS

C

13

R

4

FN9169.4

December 4, 2009

6

ISL6420A

Absolute Maximum Ratings (Note 4)

Thermal Information

Bias Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V

BOOT and U Pins . . . . . . . . . . . . . . . . . . . . . . . . . +36V

Thermal Resistance (Typical)

θ

(°C/W) θ (°C/W)

JC

JA

GATE

QFN Package (Notes 5, 6) . . . . . . .

QSOP Package (Note 5) . . . . . . . .

47

90

8.5

NA

Maximum Junction Temperature (Plastic Package) . . +150°C

Maximum Storage Temperature Range . . . -65°C to +150°C

Ambient Temperature Range . -40°C to +85°C (for “I” suffix)

Junction Temperature Range . . . . . . . . . . -40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

4. All voltages are with respect to GND.

5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

JA

features. See Tech Brief TB379.

6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications

Operating Conditions: VIN = 12V, PVCC shorted with VCC5, T = +25°C. Boldface limits

apply over the operating temperature range, -40°C to +85°C.

A

MIN

MAX

PARAMETER

VIN SUPPLY

SYMBOL

TEST CONDITIONS

(Note 12) TYP (Note 12) UNITS

Input Voltage Range

5.6

12

28

V

VIN SUPPLY CURRENT

Shutdown Current (Note 7)

Operating Current (Notes 7, 8)

VCC5 SUPPLY (Notes 8, 9)

Input Voltage Range

ENSS = GND

-

1.4

2.0

-

mA

3.0

VIN = VCC5 for 5V configuration

4.5

50

5.0

-

5.5

-

V

Output Voltage

VIN = 5.6V to 28V, I = 3mA to 50mA

L

Maximum Output Current

POWER-ON RESET

VIN = 12V

mA

Rising VCC5 Threshold

VIN connected to VCC5, 5V input

operation

4.310

4.400

4.475

V

Falling VCC5 Threshold

UVLO Threshold Hysteresis

PWM CONVERTERS

Maximum Duty Cycle

Minimum Duty Cycle

FB Pin Bias Current

Undervoltage Protection

Overvoltage Protection

OSCILLATOR

4.090

0.16

4.100

-

4.250

-

V

f

= 300kHz

90

-

96

-

0

%

nA

%

SW

-

80

-

V

Fraction of the set point; ~3µs noise filter

Fraction of the set point; ~1µs noise filter

75

112

85

120

UV

V

-

OVP

Free Running Frequency

Total Variation

RT = VCC5, T = -40°C to +85°C

270

-

300

330

-

kHz

%

A

T = -40°C to +85°C, with frequency set

A

by external resistor at RT

±10%

Frequency Range (Set by RT)

Ramp Amplitude (Note 10)

VIN = 12V

100

-

1400

-

kHz

ΔV

1.25

V

P-P

OSC

FN9169.4

December 4, 2009

7

ISL6420A

Electrical Specifications

Operating Conditions: VIN = 12V, PVCC shorted with VCC5, T = +25°C. Boldface limits

apply over the operating temperature range, -40°C to +85°C. (Continued)

A

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 12) TYP (Note 12) UNITS

REFERENCE AND SOFT-START/ENABLE

Internal Reference Voltage

Soft-Start Current

V

0.594

-

10

-

0.606

V

µA

V

REF

I

-

1.0

-

SS

Soft-Start Threshold

V

SOFT

Enable Low

-

1.0

V

(Converter Disabled)

PWM CONTROLLER GATE DRIVERS

Gate Drive Peak Current

Rise Time

-

0.7

20

-

A

Co = 1000pF

ns

Fall Time

Dead Time Between Drivers

ERROR AMPLIFIER

DC Gain (Note 10)

-

88

15

-

dB

Gain-Bandwidth Product

(Note 10)

GBW

MHz

Slew Rate (Note 10)

SR

-

6

-

V/µs

mA

COMP Souce/Sink Current

(Note 10)

±0.4

OVERCURRENT PROTECTION

OCSET Current Source

I

V

= 4.5V

OCSET

80

100

120

µA

OCSET

POWER-GOOD AND CONTROL FUNCTIONS

Power-Good Lower Threshold

Power-Good Higher Threshold

PGOOD Leakage Current

PGOOD Voltage Low

V

Fraction of the set point; ~3µs noise filter

-14

-10

-

-8

16

1

%

µA

V

PG-

V

9

-

PG+

I

V

= 5.0V (Note 11)

= 4mA

-

PGLKG

PULLUP

I

-

0.5

-

PGOOD

PGOOD Delay

CDEL = 0.1µF

125

2

ms

µA

V

CDEL Current for PGOOD

CDEL Threshold

CDEL threshold = 2.5V

-

2.5

-

EXTERNAL REFERENCE

Min ExternalReference Input at

GPIO1/REFIN

V

= H, C

= 2.2µF

-

0.600

-

V

MSET/MODE

REFOUT

Max External Reference Input

at GPIO1/REFIN

1.250

REFERENCE BUFFER

Buffered Output Voltage -

Internal Reference

V

I

C

= 1mA,V

= High,

0.583

0.575

1.227

1.219

0.595

0.587

1.246

1.238

0.607

0.599

1.265

1.257

V

REFOUT

MSET/MODE

= 2.2µF, T = -40°C to +85°C

A

Buffered Output Voltage -

Internal Reference

I

C

= 20mA,V

= High,

REFOUT

MSET/MODE

= 2.2µF, T = -40°C to +85°C

A

Buffered Output Voltage -

External Reference

V

= 1.25V, I

= 1mA,

REFOUT

REFIN

= High, C

= 2.2µF

MSET2/MODE

REFOUT

Buffered Output Voltage -

External Reference

V

= 1.25V, I

= 20mA,

= 2.2µF

REFIN

REFOUT

= High,C

MSET2/MODE

REFOUT

FN9169.4

December 4, 2009

8

ISL6420A

Electrical Specifications

Operating Conditions: VIN = 12V, PVCC shorted with VCC5, T = +25°C. Boldface limits

apply over the operating temperature range, -40°C to +85°C. (Continued)

A

MIN

MAX

PARAMETER

Current Drive Capability

VOLTAGE MARGINING

SYMBOL

TEST CONDITIONS

(Note 12) TYP (Note 12) UNITS

C

= 2.2µF

20

-

mA

REFOUT

Voltage Margining Range

(Note 10)

-10

-

+10

-

%

CDEL Current for Voltage

Margining

100

µA

Slew Time

CDEL = 0.1µF, VMSET = 330kΩ

-

2.5

-

ms

µA

ISET1 on FB Pin

VMSET = 330k,

GPIO1 = L

7.48

GPIO2 = H

ISET2 on FB Pin

VMSET = 330k,

GPIO1 = H

-

7.48

-

µA

GPIO2 = L

THERMAL SHUTDOWN

Shutdown Temperature

(Note 10)

-

150

20

-

°C

Thermal Shutdown Hysteresis

(Note 10)

NOTES:

7. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications,

i.e., 5.6V to 28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5

= PVCC = 5V.

8. This is the V

CC

current consumed when the device is active but not switching. Does not include gate drive current.

9. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the

internal LDO. When the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the

VIN must be connected to the VCC5. In both cases the PVCC pin should always be connected to VCC5 pin (refer to “Pin

Descriptions” on page 11 for more details).

10. Limits established by characterization and are not production tested.

11. It is recommended to use VCC5 as the pull-up source.

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

FN9169.4

December 4, 2009

9

ISL6420A

Typical Performance Curves

0.604

320

0.602

0.600

0.598

0.596

0.594

310

300

290

280

270

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

FIGURE 1. V

vs TEMPERATURE

FIGURE 2. V

vs TEMPERATURE

REF

SW

94

92

90

88

86

84

82

80

1.15

I

= 5A

OUT

1.05

0.95

0.85

-40

-15

10

35

60

85

0

5

10

15

VIN (V)

20

25

30

TEMPERATURE (°C)

FIGURE 3. I

vs TEMPERATURE

FIGURE 4. EFFICIENCY vs VIN

OCSET

+25°C, VIN = 28V, I = 1.367, I

IN

= 10A

OUT

FIGURE 5.

FIGURE 6.

FN9169.4

December 4, 2009

10

ISL6420A

Typical Performance Curves (Continued)

98

96

94

VIN = 5V

VIN = 12V

92

90

88

86

84

82

80

0

1

2

3

4

5

6

7

8

9

10

LOAD (A)

FIGURE 7. EFFICIENCY vs LOAD CURRENT (V

= 3.3V)

OUT

1400

1300

1200

1100

Pin Descriptions

VIN

This pin powers the controller and must be decoupled

to ground using a ceramic capacitor as close as

possible to the VIN pin.

1000

900

800

700

600

500

400

300

200

100

0

TABLE 1. INPUT SUPPLY CONFIGURATION

INPUT

PIN CONFIGURATION

5.5V to Connect the input to the VIN pin. The VCC5 pin

28V

will provide a 5V output from the internal LDO.

Connect PVCC to VCC5.

5V ±10% Connect the input to the VCC5 pin. Connect the

PVCC and VIN pins to VCC5.

0

25

50

75

100

125

150

RT (kΩ)

FIGURE 8. OSCILLATOR FREQUENCY vs RT

SGND

This pin provides the signal ground for the IC. Tie this

pin to the ground plane through the lowest impedance

connection.

FB

This pin is connected to the feedback resistor divider

and provides the voltage feedback signal for the

controller. This pin sets the output voltage of the

converter.

LGATE

This pin provides the PWM-controlled gate drive for

the lower MOSFET.

COMP

PHASE

This pin is the error amplifier output pin. It is used as

the compensation point for the PWM error amplifier.

This pin is the junction point of the output filter

inductor, the upper MOSFET source and the lower

MOSFET drain. This pin is used to monitor the voltage

drop across the upper MOSFET for overcurrent

protection. This pin also provides a return path for the

upper gate drive.

PGOOD

This pin provides a power good status. It is an open

collector output used to indicate the status of the

output voltage.

UGATE

RT

This pin provides the PWM-controlled gate drive for

the upper MOSFET.

This is the oscillator frequency selection pin.

Connecting this pin directly to VCC5 will select the

oscillator free running frequency of 300kHz. By placing

a resistor from this pin to GND, the oscillator frequency

can be programmed from 100kHz to 1.4MHz. Figure 8

shows the oscillator frequency vs. the RT resistance.

BOOT

This pin powers the upper MOSFET driver. Connect this

pin to the junction of the bootstrap capacitor and the

cathode of the bootstrap diode. The anode of the

bootstrap diode is connected to the PVCC pin.

FN9169.4

December 4, 2009

11

ISL6420A

CDEL

GPIO1/REFIN

The PGOOD signal can be delayed by a time

This is a dual function pin. If VMSET/MODE is not

connected to VCC5 then this pin serves as GPIO1.

Refer to Table 3 for GPIO commands interpretation.

proportional to a CDEL current of 2µA and the value of

the capacitor connected between this pin and ground.

A 0.1µF will typically provide 125ms delay. When in the

Voltage Margining mode, the CDEL current is 100µA

typical and provides the delay for the output voltage

slew rate, 2.5ms typical for the 0.1µF capacitor.

To use GPIO1/REFIN as input reference, connect

VMSET/MODE to VCC5 and GPIO2 to SGND. Connect

the desired reference voltage to the GPIO1/REFIN pin

in the range of 0.6V to 1.25V.

Connect GPIO1/REFIN and VMSET/MODE pins to

VCC5, GPIO2 to SGND, the IC operates with the

internal reference and no voltage margining function.

PGND

This pin provides the power ground for the IC. Tie this

pin to the ground plane through the lowest impedance

connection.

REFOUT

It provides buffered reference output for REFIN.

Connect 2.2µF decoupling capacitor to this pin.

PVCC

This pin is the power connection for the gate drivers.

Connect this pin to the VCC5 pin.

VMSET/MODE

This pin is a dual function pin. Tie this pin to VCC5 to

disable voltage margining. When not tied to VCC5, this

pin serves as VMSET. Connect a resistor from this pin

to ground to set delta for voltage margining.

VCC5

This pin is the output of the internal 5V LDO. Connect a

minimum of 4.7µF ceramic decoupling capacitor as

close to the IC as possible at this pin. Refer to Table 1.

If voltage margining and external reference tracking

mode are not needed, VNSET/MODE, GPIO1/REFIN

and GPIO2 all together can be tied directly to ground.

ENSS

This pin provides enable/disable function and soft-start

for the PWM output. The output drivers are turned off

when this pin is held below 1V.

GPIO2

This is general purpose IO pin for voltage margining.

Refer to Table 3.

OCSET

Connect a resistor (R ) and a capacitor from this

pin to the drain of the upper MOSFET. R , an

internal 100µA current source (I

MOSFET on resistance r

OCSET

Exposed Thermal Pad

OCSET

), and the upper

This pad is electrically isolated. Connect this pad to the

signal ground plane using at least five vias for a robust

thermal conduction path.

OCSET

set the converter

DS(ON)

overcurrent (OC) trip point.

TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION

PIN CONFIGURATIONS

FUNCTION/MODES

VMSET/MODE

REFOUT

GPIO1/REFIN

GPIO2

Enable Voltage Margining

Pin Connected to

Connect a 2.2µF

Serves as a general

GND with resistor. It capacitor for bypass of purpose I/O. Refer to purposeI/O. Referto

is used as VMSET.

external reference.

Table 3.

No Voltage Margining. Normal

operation with internal reference.

H

Connect a 2.2µF

capacitor to GND.

H (Note 14)

L

Buffered V

= 0.6V.

REFOUT

No Voltage Margining. External

reference. Buffered

H

Connect a 2.2µF

capacitor to GND.

Connect to an

external reference

voltage source (0.6V

to 1.25V)

V

= V

REFOUT

REFIN

NOTES:

13. The GPIO1/REFIN and GPIO2 pins cannot be left floating.

14. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.

FN9169.4

December 4, 2009

12

ISL6420A

TABLE 3. VOLTAGE MARGINING CONTROLLED BY

GPIO1 AND GPIO2

V

OUT

GPIO1

GPIO2

VOUT

No Change

+ΔVOUT

-ΔVOUT

L

H

L

I

OUT

PHASE

H

Ignored

ENSS

Functional Description

Initialization

FIGURE 10. TYPICAL OVERCURRENT HICCUP MODE

The ISL6420A automatically initializes upon receipt of

power. The Power-On Reset (POR) function monitors

the internal bias voltage generated from LDO output

(VCC5) and the ENSS pin. The POR function initiates

the soft-start operation after the VCC5 exceeds the

POR threshold. The POR function inhibits operation

with the chip disabled (ENSS pin <1V).

Overcurrent Protection

The overcurrent function protects the converter from

a shorted output by using the upper MOSFET’s

ON-resistance, r

method enhances the converter’s efficiency and

to monitor the current. This

DS(ON)

reduces cost by eliminating a current sensing resistor.

The device can operate from an input supply voltage of

5.5V to 28V connected directly to the VIN pin using the

internal 5V linear regulator to bias the chip and supply

the gate drivers. For 5V ±10% applications, connect

VIN to VCC5 to bypass the linear regulator.

The overcurrent function cycles the soft-start function

in a hiccup mode to provide fault protection. A resistor

connected to the drain of the upper FET and the

OCSET pin programs the overcurrent trip level. The

PHASE node voltage will be compared against the

voltage on the OCSET pin, while the upper FET is on.

A current (100µA typically) is pulled from the OCSET

pin to establish the OCSET voltage. If PHASE is lower

than OCSET while the upper FET is on then an

overcurrent condition is detected for that clock cycle.

The upper gate pulse is immediately terminated, and

a counter is incremented. If an overcurrent condition

is detected for 8 consecutive clock cycles, and the

circuit is not in soft-start, the ISL6420A enters into

the soft-start hiccup mode. During hiccup, the

external capacitor on the ENSS pin is discharged.

After the capacitor is discharged, it is released and a

soft-start cycle is initiated. There are three dummy

soft-start delay cycles to allow the MOSFETs to cool

down, to keep the average power dissipation in hiccup

mode at an acceptable level. At the fourth soft-start

cycle, the output starts a normal soft-start cycle, and

the output tries to ramp.

Soft-Start/Enable

The ISL6420A soft-start function uses an internal

current source and an external capacitor to reduce

stresses and surge current during start-up.

When the output of the internal linear regulator

reaches the POR threshold, the POR function initiates

the soft-start sequence. An internal 10µA current

source charges an external capacitor on the ENSS pin

linearly from 0V to 3.3V.

When the ENSS pin voltage reaches 1V typically, the

internal 0.6V reference begins to charge following the

dv/dt of the ENSS voltage. As the soft-start pin

charges from 1V to 1.6V, the reference voltage charges

from 0V to 0.6V. Figure 9 shows a typical soft-start

sequence.

VIN = 28V, V

= 3.3V, I = 10A

OUT

During soft-start, pulse termination current limiting is

enabled, but the 8-cycle hiccup counter is held in reset

until soft-start is completed. Figure 10 shows the

overcurrent hiccup mode.

The overcurrent function will trip at a peak inductor

current (I ) determined from Equation 1, where

OC

I

is the internal OCSET current source.

OCSET

I

• R

OCSET

(EQ. 1)

---------------------------------------------------

I

=

OC

r

DS(ON)

The OC trip point varies mainly due to the upper

MOSFETs r variations. To avoid overcurrent

DS(ON)

tripping in the normal operating load range, find the

resistor from Equation 1 with:

R

OCSET

FIGURE 9. TYPICAL SOFT-START WAVEFORM

FN9169.4

December 4, 2009

13

ISL6420A

1. The maximum r

temperature.

at the highest junction

DS(ON)

VIN = 12V, V

= 3.3V, NO LOAD

OUT

2. Determine I

for I

> I

+ (ΔI) ⁄ 2 ,

OUT(MAX)

OC

where ΔI is the output inductor ripple current.

A small ceramic capacitor should be placed in parallel

with R to smooth the voltage across R in

OCSET

the presence of switching noise on the input voltage.

Voltage Margining

The ISL6420A has a voltage margining mode that can

be used for system testing. The voltage margining

percentage is resistor selectable up to ±10%. The

voltage margining mode can be enabled by connecting

a margining set resistor from VMSET pin to ground and

using the control pins GPIO1/2 to toggle between

positive and negative margining (Refer to Table 2).

With voltage margining enabled, the VMSET resistor to

ground will set a current, which is switched to the FB

pin. The current will be equal to 2.468V divided by the

value of the external resistor tied to the VMSET pin.

Use a resistor in the range of 150kΩ to 400kΩ for

VMSET resistor.

FIGURE 12A.

VIN = 12V, V

= 3.3V, NO LOAD

OUT

2.468V

-----------------------

I

=

(EQ. 2)

VM

R

VMSET

R

FB

-----------------------

ΔV

= 2.468V

VM

R

(EQ. 3)

VMSET

The power supply output increases when GPIO2 is

HIGH and decreases when GPIO1 is HIGH. The amount

that the output voltage of the power supply changes

with voltage margining, will be equal to 2.468V x the

ratio of the external feedback resistor and the external

resistor tied to VMSET. Figure 11 shows the positive

and negative margining for a 3.3V output, using a

20.5kΩ feedback resistor and using various VMSET

resistor values.

FIGURE 12B.

3.7

3.6

3.5

3.4

3.3

3.2

3.1

VIN = 12V, V

OUT

= 3.3V, I = 10A

OUT

3.0

2.9

2.8

150 175 200 225 250 275 300 325 350 375 400

RVMSET (kΩ)

FIGURE 11. VOLTAGE MARGINING vs. VMSET

RESISTANCE

FIGURE 13. PGOOD DELAY

FN9169.4

December 4, 2009

14

ISL6420A

The slew time of the current is set by an external

capacitor on the CDEL pin, which is charged and

discharged with a 100µA current source. The change in

voltage on the capacitor is 2.5V. This same capacitor is

used to set the PGOOD active delay after soft-start.

When PGOOD is low, the internal PGOOD circuitry uses

the capacitor and when PGOOD is high, the voltage

margining circuit uses the capacitor. The slew time for

voltage margining can be in the range of 300µs to

2ms.

Undervoltage

If the voltage on the FB pin is less than 15% of the

reference voltage for 8 consecutive PWM cycles, then

the circuit enters into soft-start hiccup mode. This

mode is identical to the overcurrent hiccup mode.

Overvoltage Protection

If the voltage on the FB pin exceeds the reference

voltage by 15%, the lower gate driver is turned on

continuously to discharge the output voltage. If the

overvoltage condition continues for 32 consecutive

PWM cycles, then the chip is turned off with the gate

drivers tri-stated. The voltage on the FB pin will fall

and reach the 15% undervoltage threshold. After 8

clock cycles, the chip will enter soft-start hiccup

mode. This mode is identical to the overcurrent hiccup

mode.

External Reference/DDR Supply

The voltage margining can be disabled by connecting

the VMSET/MODE to VCC5. In this mode, the chip can

be configured to work with an external reference input

and provide a buffered reference output.

If VMSET/MODE pin and the GPIO1/REFIN pin are both

tied to VCC5, then the internal 0.6V reference is used

as the error amplifier non-inverting input. The buffered

reference output on REFOUT will be 0.6V ±0.01V,

capable of sourcing 20mA and sinking up to 50µA

current with a 2.2µF capacitor connected to the

REFOUT pin.

Gate Control Logic

The gate control logic translates generated PWM

control signals into the MOSFET gate drive signals

providing necessary amplification, level shifting and

shoot-through protection. Also, it has functions that

help optimize the IC performance over a wide range of

operational conditions.

If the VMSET/MODE pin is tied to high but

GPIO1/REFIN is connected to an external voltage

source between 0.6V to 1.25V, then this external

voltage is used as the reference voltage at the positive

input of the error amplifier. The buffered reference

output on REFOUT will be Vrefin ±0.01V, capable of

sourcing 20mA and sinking up to 50µA current with a

2.2µF capacitor on the REFOUT pin.

Since MOSFET switching time can vary dramatically

from type to type and with the input voltage, the gate

control logic provides adaptive dead time by

monitoring the gate-to-source voltages of both upper

and lower MOSFETs. The lower MOSFET is not turned

on until the gate-to-source voltage of the upper

MOSFET has decreased to less than approximately 1V.

Similarly, the upper MOSFET is not turned on until the

gate-to-source voltage of the lower MOSFET has

decreased to less than approximately 1V. This allows a

wide variety of upper and lower MOSFETs to be used

without a concern for simultaneous conduction, or

shoot-through.

Power-Good

The PGOOD pin can be used to monitor the status of

the output voltage. PGOOD will be true (open drain)

when the FB pin is within ±10% of the reference and

the ENSS pin has completed its soft-start ramp.

Additionally, a capacitor on the CDEL pin will set a

delay for the PGOOD signal. After the ENSS pin

completes its soft-start ramp, a 2µA current begins

charging the CDEL capacitor to 2.5V. The capacitor will

be quickly discharged before PGOOD goes high. The

programmable delay can be used to sequence multiple

converters or as a LOW-true reset signal.

Start-up into Pre-Biased Load

The ISL6420A is designed to power-up into a

pre-biased load. This is achieved by transitioning from

Diode Emulation mode to a Forced Continuous

Conduction mode during start-up. The lower gate turns

ON for a short period of time and the voltage on the

phase pin is sensed. When this goes negative the lower

gate is turned OFF and remains OFF till the next cycle.

As a result, the inductor current will not go negative

during soft-start and thus will not discharge the

pre-biased load. The waveform for this condition is

shown in Figure 14.

If the voltage on the FB pin exceeds ±10% of the

reference, then PGOOD will go low after 1µs of noise

filtering.

Over-Temperature Protection

The IC is protected against over-temperature

conditions. When the junction temperature exceeds

+150°C, the PWM shuts off. Normal operation is

resumed when the junction temperature is cooled

down to +130°C.

Shutdown

When ENSS pin is below 1V, the regulator is disabled

with the PWM output drivers tri-stated. When disabled,

the IC power will be reduced.

FN9169.4

December 4, 2009

15

ISL6420A

VIN = 12V, V

OUT

= 3.3V at 25mA LOAD

VIN

ISL6420A

UGATE

Q1

Q2

L

O

V

OUT

PHASE

C

IN

C

D2

O

LGATE

GND

RETURN

FIGURE 15. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD

Application Guidelines

Layout Considerations

+VIN

BOOT

As in any high frequency switching converter, layout is

very important. Switching current from one power

device to another can generate voltage transients

across the impedances of the interconnecting bond

wires and circuit traces. These interconnecting

impedances should be minimized by using wide, short

printed circuit traces. The critical components should

be located as close together as possible using ground

plane construction or single point grounding.

D

1

Q

1

L

O

C

BOOT

PHASE

+5V

CC

V

OUT

ISL6420A

ENSS

C

Q

O

2

V

C

VCC

C

SS

GND

Figure 15 shows the critical power components of the

converter. To minimize the voltage overshoot the

interconnecting wires indicated by heavy lines should

be part of ground or power plane in a printed circuit

board. The components shown in Figure 15 should be

located as close together as possible. Please note that

FIGURE 16. PRINTED CIRCUIT BOARD SMALL

SIGNAL LAYOUT GUIDELINES

Feedback Compensation

Figure 17 highlights the voltage-mode control loop for

a synchronous-rectified buck converter. The output

the capacitors C and C each represent numerous

IN

O

physical capacitors. Locate the ISL6420A within 3

inches of the MOSFETs, Q and Q . The circuit traces

1

2

voltage (V

) is regulated to the Reference voltage

) is

OUT

for the MOSFETs’ gate and source connections from the

ISL6420A must be sized to handle up to 1A peak

current.

level. The error amplifier (Error Amp) output (V

E/A

compared with the oscillator (OSC) triangular wave to

provide a pulse-width modulated (PWM) wave with an

amplitude of VIN at the PHASE node. The PWM wave

Figure 16 shows the circuit traces that require

additional layout consideration. Use single point and

ground plane construction for the circuits shown.

Minimize any leakage current paths on the ENSS PIN

is smoothed by the output filter (L and C ).

O

The modulator transfer function is the small-signal

transfer function of V /V . This function is

OUT E/A

dominated by a DC Gain and the output filter (L and

and locate the capacitor, C close to the SS pin

ss

O

because the internal current source is only 10µA.

C ), with a double pole break frequency at F and a

O

LC

Provide local V

decoupling between VCC and GND

pins. Locate the capacitor, C as close as practical

CC

zero at F

. The DC Gain of the modulator is simply

ESR

BOOT

the input voltage (VIN) divided by the peak-to-peak

oscillator voltage ΔV

to the BOOT and PHASE pins.

.

OSC

FN9169.4

December 4, 2009

16

ISL6420A

Compensation Break Frequency Equations

VIN

OSC

DRIVER

1

----------------------------------

F

=

PWM

(EQ. 6)

(EQ. 7)

Z1

P1

2π • R2 • C1

L

O

COMPARATOR

V

OUT

-

PHASE

1

+

ΔV

------------------------------------------------------

F

=

OSC

C

O

C1 • C2

C1 + C2

⎛

⎞

----------------------

2π • R2 •

⎝

⎠

ESR

(PARASITIC)

Z

FB

1

-----------------------------------------------------

F

=

V

(EQ. 8)

(EQ. 9)

E/A

Z2

P2

2π • (R1 + R3) • C3

Z

-

IN

+

REFERENCE

ERROR

AMP

1

----------------------------------

=

2π • R3 • C3

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

DETAILED COMPENSATION COMPONENTS

2. Place 1

(~75% F

Zero Below Filter’s Double Pole

)

LC

ND

Z

FB

V

OUT

3. Place 2

4. Place 1

5. Place 2

Zero at Filter’s Double Pole

Pole at the ESR Zero

C

2

Z

IN

ST

C

R

1

3

R

3

ND

2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop

Gain

R

1

COMP

FB

7. Estimate Phase Margin - Repeat if Necessary

-

+

R

Figure 18 shows an asymptotic plot of the DC/DC

converter’s gain vs. frequency. The actual Modulator

Gain has a high gain peak due to the high Q factor of

the output filter and is not shown in Figure 18. Using

the previously mentioned guidelines should give a

Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the

4

ISL6420A

REF

R

⎛

⎞

1

V

= V

× 1 + ------

⎜

⎟

⎠

OUT

REF

R

⎝

4

FIGURE 17. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

compensation gain. Check the compensation gain at

F

with the capabilities of the error amplifier. The Loop

P2

Gain is constructed on the log-log graph of Figure 18

by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

Modulator Break Frequency Equations

1

--------------------------------------

F

=

(EQ. 4)

LC

2π •

L

• C

O

1

100

--------------------------------------------

F

=

(EQ. 5)

F

P1

F

ESR

F

P2

Z2

Z1

2π • (ESR • C

)

O

80

60

OPEN LOOP

ERROR AMP GAIN

The compensation network consists of the error

amplifier (internal to the ISL6420A) and the

40

impedance networks Z and Z . The goal of the

20LOG

(R2/R1)

IN FB

compensation network is to provide a closed loop

transfer function with the highest 0dB crossing

20

20LOG

(VIN/ΔV

)

OSC

0

frequency (f

) and adequate phase margin. Phase

0dB

COMPENSATION

GAIN

margin is the difference between the closed loop phase

at f and 180°. The following equations relate the

MODULATOR

GAIN

-20

-40

-60

0dB

compensation network’s poles, zeros and gain to the

components (R , R , R , C , C , and C ) in Figure 17.

CLOSED LOOP

GAIN

F

LC

F

ESR

100k

FREQUENCY (Hz)

1

2

3

1

2

3

Use the following guidelines for locating the poles and

10

100

1k

10k

1M

10M

zeros of the compensation network.

FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER

GAIN

FN9169.4

December 4, 2009

17

ISL6420A

The compensation gain uses external impedance

current and the output capacitors ESR. The ripple

networks Z and Z to provide a stable, high

voltage and current are approximated by Equations 10

and 11:

FB IN

bandwidth (BW) overall loop. A stable control loop has

a gain crossing with -20dB/decade slope and a phase

margin greater than 45°. Include worst case

V

- V

V

OUT OUT

IN

------------------------------- ---------------

ΔI =

⋅

(EQ. 10)

L

Fs x L

V

IN

component variations when determining phase margin.

ΔV

= ΔI ⋅ ESR

(EQ. 11)

OUT

L

Component Selection

Guidelines

Increasing the value of inductance reduces the ripple

current and voltage. However, larger inductance values

reduce the converter’s response time to a load

transient.

Output Capacitor Selection

An output capacitor is required to filter the output and

supply the load transient current. The filtering

requirements are a function of the switching frequency

and the ripple current. The load transient requirements

are a function of the slew rate (di/dt) and the

magnitude of the transient load current. These

requirements are generally met with a mix of

capacitors and careful layout.

One of the parameters limiting the converter’s

response to a load transient is the time required to

change the inductor current. Given a sufficiently fast

control loop design, the ISL6420A will provide either

0% or 100% duty cycle in response to a load transient.

The response time is the time required to slew the

inductor current from an initial current value to the

transient current level. During this interval the

difference between the inductor current and the

transient current level must be supplied by the output

capacitor. Minimizing the response time can minimize

the output capacitance required.

Modern microprocessors produce transient load rates

above 1A/ns. High frequency capacitors initially supply

the transient and slow the current load rate seen by

the bulk capacitors. The bulk filter capacitor values are

generally determined by the ESR (effective series

resistance) and voltage rating requirements rather

than actual capacitance requirements.

The response time to a transient is different for the

application of load and the removal of load. Equations

12 and 13 give the approximate response time interval

for application and removal of a transient load:

High frequency decoupling capacitors should be placed

as close to the power pins of the load as physically

possible. Be careful not to add inductance in the circuit

board wiring that could cancel the usefulness of these

low inductance components. Consult with the

manufacturer of the load on specific decoupling

requirements. For example, Intel recommends that the

high frequency decoupling for the Pentium Pro be

composed of at least forty (40) 1.0µF ceramic

capacitors in the 1206 surface-mount package.

L

× I

TRAN

O

-------------------------------

t

=

(EQ. 12)

(EQ. 13)

RISE

FALL

V

– V

OUT

IN

L

× I

O

TRAN

------------------------------

t

=

V

OUT

where: I

TRAN

the response time to the application of load, and t

is the transient load current step, t

RISE

is

FALL

is the response time to the removal of load. With a

+5V input source, the worst case response time can be

either at the application or removal of load and

dependent upon the output voltage setting. Be sure to

check both of these equations at the minimum and

maximum output levels for the worst case response

time.

Use only specialized low-ESR capacitors intended

for switching-regulator applications for the bulk

capacitors. The bulk capacitor’s ESR will determine

the output ripple voltage and the initial voltage drop

after a high slew-rate transient. An aluminum

electrolytic capacitor's ESR value is related to the

case size with lower ESR available in larger case

sizes. However, the equivalent series inductance (ESL)

of these capacitors increases with case size and can

reduce the usefulness of the capacitor to high slew-rate

transient loading. Unfortunately, ESL is not a specified

parameter. Work with your capacitor supplier and

measure the capacitor’s impedance with frequency to

select a suitable component. In most cases, multiple

electrolytic capacitors of small case size perform better

than a single large case capacitor.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the

voltage overshoot across the MOSFETs. Use small

ceramic capacitors for high frequency decoupling and

bulk capacitors to supply the current needed each

time Q turns on. Place the small ceramic capacitors

1

physically close to the MOSFETs and between the

drain of Q and the source of Q .

1

2

The important parameters for the bulk input capacitor

are the voltage rating and the RMS current rating. For

reliable operation, select the bulk capacitor with

voltage and current ratings above the maximum input

voltage and largest RMS current required by the circuit.

The capacitor voltage rating should be at least 1.25 x

Output Inductor Selection

The output inductor is selected to meet the output

voltage ripple requirements and minimize the

converter’s response time to the load transients. The

inductor value determines the converter’s ripple

current and the ripple voltage is a function of the ripple

FN9169.4

December 4, 2009

18

ISL6420A

greater than the maximum input voltage and a voltage

Schottky Selection

rating of 1.5 x is a conservative guideline. The RMS

current rating requirement for the input capacitor of a

buck regulator is approximately 1/2 the DC load current.

Equation 14 shows a more specific formula for

determining the input ripple:

Rectifier D is a clamp that catches the negative

2

inductor swing during the dead time between turning off

the lower MOSFET and turning on the upper MOSFET.

The diode must be a Schottky type to prevent the

parasitic MOSFET body diode from conducting. It is

acceptable to omit the diode and let the body diode of

the lower MOSFET clamp the negative inductor swing,

but efficiency will drop one or two percent as a result.

The diode's rated reverse breakdown voltage must be

greater than the maximum input voltage.

2

I

= I

⋅

MAX

(D – D )

(EQ. 14)

RMS

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but

caution must be exercised with regard to the capacitor

surge current rating. These capacitors must be capable

of handling the surge-current at power-up. The TPS

series available from AVX, and the 593D series from

Sprague are both surge current tested.

MOSFET Selection/Considerations

The ISL6420A requires 2 N-Channel power MOSFETs.

These should be selected based upon r

, gate

DS(ON)

supply requirements, and thermal management

requirements.

In high-current applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes

two loss components; conduction loss and switching loss.

The conduction losses are the largest component of

power dissipation for both the upper and the lower

MOSFETs. These losses are distributed between the two

MOSFETs according to duty factor (see Equations 15 and

16). Only the upper MOSFET has switching losses, since

the Schottky rectifier clamps the switching node before

the synchronous rectifier turns on.

2

O

1

2

--

P

= I ⋅ r

⋅ D +

I

⋅ V ⋅ t ⋅ f

IN sw sw

(EQ. 15)

UFET

LFET

DS(ON)

O

2

= I ⋅ r

⋅ (1 – D)

(EQ. 16)

O

Where D is the duty cycle = Vo/VIN, t

SW

is the switching

is the switching frequency.

interval, and f

SW

These equations assume linear voltage-current

transitions and do not adequately model power loss due

the reverse recovery of the lower MOSFET’s body diode.

The gate-charge losses are dissipated by the ISL6420A

and don't heat the MOSFETs. However, large

gate-charge increases the switching interval, t

which

SW

increases the upper MOSFET switching losses. Ensure

that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating

the temperature rise according to package

thermal-resistance specifications. A separate heatsink

may be necessary depending upon MOSFET power,

package type, ambient temperature and air flow.

FN9169.4

December 4, 2009

19

ISL6420A

Package Outline Drawing

L20.4x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 11/06

4X

2.0

4.00

0.50

16X

A

6

B

16

20

PIN #1 INDEX AREA

6

PIN 1

INDEX AREA

1

15

2 . 10 ± 0 . 15

11

5

(4X)

0.15

6

10

0.10 M

C

A B

4

0.25 +0.05 / -0.07

TOP VIEW

20X 0.6 +0.15 / -0.25

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

C

BASE PLANE

( 3. 6 TYP )

(

SEATING PLANE

0.08 C

( 20X 0 . 5 )

2. 10 )

SIDE VIEW

0 . 2 REF

( 20X 0 . 25 )

( 20X 0 . 8)

5

C

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9169.4

December 4, 2009

20

ISL6420A

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M20.15

N

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

AREA

0.25(0.010M) B M

H

E

GAUGE

PLANE

INCHES

MIN

MILLIMETERS

SYM-

BOL

-B-

MAX

0.069

0.010

0.061

0.012

0.010

0.344

0.157

MIN

1.35

0.10

-

MAX NOTES

A

A1

A2

B

0.053

0.004

-

1.75

0.25

1.54

0.30

0.25

8.74

3.98

-

1

2

3

-

L

0.25

0.010

SEATING PLANE

A

-

-A-

0.008

0.007

0.337

0.150

0.20

0.18

8.56

3.81

9

D

h x 45°

C

-

-C-

D

E

3

α

4

A2

e

A1

C

e

0.025 BSC

0.635 BSC

-

B

0.10(0.004)

H

h

0.228

0.0099

0.016

0.244

0.0196

0.050

5.80

0.26

0.41

6.19

0.49

1.27

-

0.17(0.007M)

C A M B S

5

NOTES:

L

6

1. Symbols are defined in the “MO Series Symbol List” in Sec-

tion 2.2 of Publication Number 95.

N

α

20

7

0°

8°

0°

8°

-

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Rev. 1 6/04

3. Dimension “D” does not include mold flash, protrusions or

gate burrs. Mold flash, protrusion and gate burrs shall not

exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protru-

sions. Interlead flash and protrusions shall not exceed

0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a

visual index feature must be located within the cross-

hatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allow-

able dambar protrusion shall be 0.10mm (0.004 inch) total

in excess of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter di-

mensions are not necessarily exact.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9169.4

December 4, 2009

21


型号：	ISL6420AIR
厂家：	RENESAS TECHNOLOGY CORP
描述：	0.05A SWITCHING CONTROLLER, 1400kHz SWITCHING FREQ-MAX, PQCC20, 4 X 4 MM, PLASTIC, MO-220VGGD-1, QFN-20 开关
文件：	总21页 (文件大小：577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6420AIR [RENESAS]

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