R2J20651NP#13 [RENESAS]
IC,DUAL MOSFET DRIVER,LLCC,40PIN,PLASTIC;
| 型号： | R2J20651NP#13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,DUAL MOSFET DRIVER,LLCC,40PIN,PLASTIC 驱动 |
| 文件： | 总18页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R2J20651NP
Integrated Driver – MOS FET (DrMOS)
REJ03G1743-0301
Rev.3.01
Aug 19, 2009
Description
The R2J20651NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier
diode (SBD), eliminating the need for an external SBD for this purpose.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compliant with Intel 6 × 6 DrMOS specification
Built-in power MOS FET suitable for applications with 5 V/12 V input
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
Capable of both 3.3 V and 5 V PWM signal
VIN operating-voltage range: 16 V max
High-frequency operation (above 1 MHz) possible
Large average output current (Max. 35 A)
Achieve low power dissipation
Controllable driver: Remote on/off
Low-side MOS FET disabled function for DCM operation
Built-in thermal warning
Built-in Schottky diode for bootstrapping
Small package: QFN40 (6 mm × 6 mm × 0.95 mm)
Terminal Pb-free/Halogen-free
Outline
Integrated Driver-MOS FET (DrMOS)
QFN40 package 6 mm × 6 mm
VCIN BOOT
MOS FET Driver
CGND VDRV
GH
VIN
1
10
40
11
THWN
DISBL#
LSDBL#
PWM
Driver
Pad
High-side
MOS Pad
VSWH
Low-side MOS Pad
31
20
30
21
GL PGND
(Bottom view)
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 1 of 17
R2J20651NP
Block Diagram
Driver chip
GH VIN
BOOT
VCIN
SBD
UVL
THWN
THWN
CGND
High-side
MOS FET
Level shifter
DISBL#
0.5 μA
VCIN
CGND
150 k
LSDBL#
PWM
VSWH
Overlap
protection
VCIN
Input logic
(TTL level)
(3 state in)
Low-side
MOS FET
CGND
PGND
VDRV
GL
Notes: 1. Truth table for the DISBL# pin.
2. Truth table for the LSDBL# pin.
DISBL# Input
"L"
Driver Chip Status
Shutdown (GL, GH = "L")
Shutdown (GL, GH = "L")
Enable (GL, GH = "Active")
LSDBL# Input
GL Status
"L"
"L"
"Open"
"H"
"Open"
"H"
"Active"
"Active"
3. Output signal from the UVL block
4. Output signal from the THWN block
Thermal
warning
"H"
"H"
THWN Output
Logic Level
For active
Normal
operating
UVL Output
Logic Level
For shutdown
"L"
"L"
VL
VH
TL
TH
VCIN
TIC (°C)
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 2 of 17
R2J20651NP
Pin Arrangement
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
VIN
VIN
PWM
DISBL#
THWN
CGND
GL
VIN
CGND
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
21 22 23 24 25 26 27 28 29 30
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
LSDBL#
VCIN
Pin No.
Description
Remarks
When asserted "L" signal, Low-side gate disable
1
2
3
4
Low-side gate disable
Control input voltage (+5 V input) Driver Vcc input
Gate supply voltage (+5 V input) 5 V gate drive
VDRV
BOOT
CGND
GH
Bootstrap voltage pin
Control signal ground
High-side gate signal
Input voltage
To be supplied +5 V through internal SBD
5, 37, Pad
6
Should be connected to PGND externally
Pin for Monitor
VIN
8 to 14, Pad
VSWH
PGND
GL
7, 15, 29 to 35, Pad Phase output/Switch output
16 to 28
36
Power ground
Low-side gate signal
Thermal warning
Signal disable
Pin for Monitor
THWN
DISBL#
PWM
38
Thermal warning when over 130°C
Disabled when DISBL# is "L"
Capable of both 3.3 V and 5 V logic input
39
40
PWM drive logic input
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 3 of 17
R2J20651NP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Pt(25)
Rating
Units
Note
Power dissipation
25
W
1
Pt(110)
8
Average output current
Input voltage
Iout
35
A
V
VIN (DC)
–0.3 to +16
2
2, 3
2
VIN (AC)
20
Supply voltage & Drive voltage
Switch node voltage
VCIN & VDRV
VSWH (DC)
VSWH (AC)
VBOOT (DC)
VBOOT (AC)
–0.3 to +6
V
V
16
2
25
2, 3
2
BOOT voltage
I/O voltage
22
25
V
V
2, 3
2, 4
Vpwm, Vdisble,
Vlsdbl, Vthwn
–0.3 to VCIN + 0.3
Operating junction temperature
Storage temperature
Tj-opr
Tstg
–40 to +150
–55 to +150
°C
°C
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110°C.
2. Rated voltages are relative to voltages on the CGND and PGND pins.
3. The specification values indicated "AC" are limited within 100 ns.
4. VCIN + 0.3 V < 6 V
Safe Operating Area
45
40
35
30
25
Condition
20
15
VOUT = 1.3 V
VIN = 12 V
VCIN = 5 V
10 VDRV = 5 V
L = 0.45 μH
Fsw = 1 MHz
5
0
0
25
50
75
100
125
150
175
PCB Temperature (°C)
Recommended Operating Condition
Item
Symbol
Rating
Units
Note
Input voltage
Supply voltage & Drive voltage
VIN
4.5 to 14
4.5 to 5.5
V
V
VCIN & VDRV
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 4 of 17
R2J20651NP
Electrical Characteristics
(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Item
Symbol
VH
Min
3.1
2.7
—
Typ
3.5
3.0
0.5
29
Max
3.9
3.3
—
Units
V
Test Conditions
Supply
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VL
V
dUVL
ICIN
V
VH – VL
VCIN operating current
—
—
mA
fPWM = 1 MHz,
Ton_pwm = 120 ns
VCIN disable current
ICIN-DISBL
—
—
50
μA
DISBL# = 0 V, PWM = 0 V,
LSDBL# = Open
PWM
input
PWM rising threshold
PWM falling threshold
PWM input resistance
Tri-state shutdown window
Shutdown hold-off time
Disable threshold
VH-PWM
VL-PWM
RIN-PWM
VIN-SD
1.7
0.9
42
2.1
1.2
70
2.5
1.5
V
V
98
kΩ
V
PWM = 1 V
VL-PWM
—
—
VH-PWM
—
1
tHOLD-OFF
VDISBL
VENBL
*
240
1.2
2.4
0.5
2.4
1.2
–27
130
15
ns
V
DISBL#
input
0.9
1.9
—
1.5
Enable threshold
2.9
V
Input current
IDISBL
2.0
μA
V
DISBL# = 1 V
LSDBL# Low-side activation threshold VLSDBLH
1.9
0.9
–54
110
—
2.9
input
Low-side disable threshold
Input current
VLSDBLL
ILSDBL
TTHWN
1.5
V
–13.5
—
μA
°C
°C
kΩ
μA
LSDBL# = 1 V
1
Thermal Warning temperature
*
Driver IC temperature
1
warning
Temperature hysteresis
THWN on resistance
THWN leakage current
THYS
RTHWN
ILEAK
*
—
1
*
1.0
—
2.5
0.001
4.0
THWN = 1 V
THWN = 5 V
1.0
Note: 1. Reference values for design. Not 100% tested in production.
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 5 of 17
R2J20651NP
Pin Connection
+5 V
0.1 μF
1.0 μF
CGND
Low Side Disable Signal INPUT
VIN
(4.5 V~14 V)
0~10 Ω
CGND
10
9
8
7
6
5
4
3
2
1
PWM
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
PWM INPUT
10 μF × 4
DISBL#
THWN
VIN
CGND
PAD
PAD
PGND
VIN
CGND
GL
DISBL# INPUT
+5 V
VSWH
PGND
51 kΩ
R2J20651NP
VSWH
VSWH
PAD
21 22 23 24 25 26 27 28 29 30
0.45 μF
Vout
PGND
PGND
Power GND Signal GND
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 6 of 17
R2J20651NP
Typical Application
(1) 12 V Input Power
+12 V
+5 V
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
PWM1
+1.3 V
PWM2
PWM
Control
PWM3
Circuit
VCIN VDRV BOOT GH
PWM4
THWN
VIN
DISBL# R2J20651
VSWH
NP
Power GND Signal GND
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 7 of 17
R2J20651NP
(2) 5 V Input Power
+5 V
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
PWM1
+1.5 V
PWM2
PWM
Control
PWM3
Circuit
VCIN VDRV BOOT GH
PWM4
THWN
VIN
DISBL# R2J20651
VSWH
NP
Power GND Signal GND
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20651
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 8 of 17
R2J20651NP
Test Circuit
IIN
A
A
Vinput
Vcont
VIN
V
ICIN
6.2 Ω
VCIN
V
VCIN VDRV
DISBL#
BOOT
0.1 μF
VIN
LSDBL# R2J20651
NP
VSWH
THWN
PGND
Electric
load
PWM
5V pulse
fPWM
IO
CGND
GH
GL
Note: PIN = IIN × VIN + ICIN × VCIN
POUT = IO × VO
Average Output Voltage
VO
Averaging
circuit
V
Efficiency = POUT / PIN
PLOSS(DrMOS) = PIN – POUT
Ta = 27°C
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 9 of 17
R2J20651NP
Typical Data
Power Loss vs. Output Current
VIN = 12 V
Power Loss vs. Input Voltage
10
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VCIN = 5 V
VOUT = 1.3 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
9
8
7
6
5
4
3
2
1
0
VCIN = 5 V
VOUT = 1.3 V
PWM = 600 kHz
L = 0.45 μH
f
f
0
5
10
15
20
25
30
35
4
6
8
10
12
14
16
Output Current (A)
Input Voltage (V)
Power Loss vs. Output Voltage
Power Loss vs. Switching Frequency
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIN = 12 V
VCIN = 5 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
VIN = 12 V
VCIN = 5 V
VOUT = 1.3 V
L = 0.45 μH
IOUT = 25 A
f
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
250
500
750
1000
1250
Output Voltage (V)
Switching Frequency (kHz)
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 10 of 17
R2J20651NP
Typical Data (cont.)
Power Loss vs. Output Inductance
Power Loss vs. VCIN
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIN = 12 V
VCIN = 5 V
VOUT = 1.3 V
VIN = 12 V
VOUT = 1.3 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
f
f
PWM = 600 kHz
IOUT = 25 A
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
4.0
4.5
5.0
5.5
6.0
Output Inductance (μH)
VCIN (V)
Average ICIN vs. Switching Frequency
50
VIN = 12 V
VCIN = 5 V
VOUT = 1.3 V
L = 0.45 μH
IOUT = 0 A
40
30
20
10
0
250
500
750
1000
1250
Switching Frequency (kHz)
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 11 of 17
R2J20651NP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 3.5 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.0 V or less. The
signal on pin DISBL# also enables or disables the circuit.
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.
VCIN
DISBL#
Driver State
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
L
∗
L
H
H
H
H
Open
Disable (GL, GH = L)
PWM & LSDBL#
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the
PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.
PWM
GH
L
GL
H
L
H
H
L
The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low.
Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous
Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal.
This pin is internally pulled up to VCIN with 150 kΩ resistor.
When low-side disable function is not used, keep this pin open or pulled up to VCIN.
CCM Operation (LSDBL# = "H" or Open mode)
IL
GH
GL
Figure 1.1 Typical Signals During CCM
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 12 of 17
R2J20651NP
DCM Operation (LSDBL# = "L")
IL
0 A
GH
GL
Figure 1.2 Typical Signals During Low-Side Disable Operation
The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-
state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become
low, a PWM input voltage of 2.1 V or more is required to make the circuit return to normal operation.
240 ns (tHOLD-OFF
)
240 ns (tHOLD-OFF)
2.1 V
1.2 V
PWM
GH
GL
240 ns (tHOLD-OFF
)
240 ns (tHOLD-OFF)
2.1 V
1.2 V
PWM
GH
GL
Figure 2
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 13 of 17
R2J20651NP
THWN
This thermal warning feature is the indication of the high temperature status.
THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 kΩ) to THWN for systems
with the thermal warning implementation.
When the chip temperature of the internal driver IC becomes over 130°C, thermal warning function operates.
This signal is only indication for the system controller and does not disable DrMOS operation.
When thermal warning function is not used, keep this pin open.
Thermal
warning
"H"
Normal
THWN output
Logic Level
operating
"L"
TIC (°C)
115 130
Figure 3
MOS FETs
The MOS FETs incorporated in R2J20651NP are highly suitable for synchronous-rectification buck conversion. For the
high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-
side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 14 of 17
R2J20651NP
PCB Layout Example
Figure 4 shows an example of the PCB layout for the R2J20651NP. Placing several ceramic capacitors (e.g. 10 μF)
between VIN and PGND can be expected to the decreasing switching noise and improvement of efficiency.
In that case, it is necessary to connect each GND pattern with low impedance by using other PCB layers.
Moreover, by taking the wide VSWH pattern, the effect of letting the heat from the low side MOS FET can be expected.
When R2J20651NP is mounted on a small substrate like POL module, the temperature rising of the device could be
eased if the thermal via-hole is added under the pad of VIN and VSWH.
10 μF
10 μF
Vin
10 μF
10 μF
0.1 μF
GND
Rboot
GND
GND
1 μF
VCIN
VSWH
GND
DISBL#
PWM
To Inductor
Via Hole
Figure 4 R2J20651NP PCB Layout Example (Top View)
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 15 of 17
R2J20651NP
Footprint Example
(Unit: mm)
0.20
6.20
0.20
2.3
C0.4
0.6
0.3
C0.1
13–R0.2
2.15
0.6
0.50
40–0.30
Figure 5 Footprint Example
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 16 of 17
R2J20651NP
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
—
MASS[Typ.]
—
P-HVQFN40-p-0606-0.50
PVQN0040KC-A
HD
D
HD/2
D /2
4-C0.50
B
B
1pin
1pin
INDEX
40
40
2.2
C0.3
A
0.7
0.2
1.95
Dimension in Millimeters
Min Nom Max
5.95 6.00 6.05
5.95 6.00 6.05
Reference
Symbol
2-A section
CAV No.
Die No.
D
E
2.05
1.95
A2 0.87 0.89 0.91
f
—
—
0.20
ZD
A
0.865 0.91 0.95
X 4
e
X 4
t
S AB
A1 0.005 0.02 0.04
0.17 0.22 0.27
b1 0.16 0.20 0.24
0.50
Lp 0.40 0.50 0.60
f
S AB
b
b
x
S AB
y1
S
e
—
—
L1
x
y
y1
t
—
—
—
—
—
—
—
—
0.05
0.05
0.20
0.20
S
HD 6.15 6.20 6.25
HE 6.15 6.20 6.25
y
S
Lp
ZD
ZE
—
—
0.75
0.75
—
—
L1 0.06 0.10 0.14
c1 0.17 0.20 0.23
c2 0.17 0.22 0.27
Ordering Information
Part Name
R2J20651NP#G3
Quantity
Shipping Container
2500 pcs
250 pcs
Taping Reel
Tray
R2J20651NP#13
REJ03G1743-0301 Rev.3.01 Aug 19, 2009
Page 17 of 17
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
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