RJK03R4DPA-00-J5A [RENESAS]

Built in SBD Dual N-channel Power MOS FET High Speed Power Switching; 内置SBD双N沟道功率MOS FET高速电源开关


型号：	RJK03R4DPA-00-J5A
厂家：	RENESAS TECHNOLOGY CORP
描述：	Built in SBD Dual N-channel Power MOS FET High Speed Power Switching 内置SBD双N沟道功率MOS FET高速电源开关开关电源开关
文件：	总11页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary Datasheet

RJK03R4DPA

MOS1 30 V, 20 A, 7.0 mΩ max.

MOS2 30 V, 50 A, 2.3 mΩ max.

Built in SBD Dual N-channel Power MOS FET

High Speed Power Switching

R07DS0888EJ0110

Rev.1.10

Oct 29, 2012

Features



Low on-resistance

Capable of 4.5 V gate drive

High density mounting

Pb-free

Halogen-free

Outline

RENESAS Package code: PWSN0008DD-B

(Package name: WPAK-D(3))

D1 D1 D1

S1/D2

1, 8

Gate

2, 3, 4, 9 Drain

5, 6, 7, 9 Source

S2 S2 S2

(Bottom View)

MOS1

MOS2 and

Schottky Barrier Diode

Absolute Maximum Ratings

(Ta = 25°C)

Ratings

Item

Drain to source voltage

Gate to source voltage

Drain current

Symbol

Unit

MOS1

MOS2

V_DSS

V_GSS

I_D

±20

±12

Note1

Drain peak current

Reverse drain current

Avalanche current

Avalanche energy

Channel dissipation

Channel temperature

Storage temperature

I_D(pulse)

200

I_DR

Note 2

I_AP

Note 2

E_AS

14.4

°C

Pch ^Note3

Tch

150

Tstg

–55 to +150

Notes: 1. PW  10 s, duty cycle  1%

2. Value at Tch = 25C, Rg  50 

3. Tc=25C

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 1 of 10

RJK03R4DPA

Preliminary

Electrical Characteristics

• MOS1

(Ta = 25°C)

Item

Symbol

V_(BR)DSS

I_GSS

Min

—

1.2

—

Typ

—

Max

—

Unit

Test Conditions

Drain to source breakdown voltage

Gate to source leak current

Zero gate voltage drain current

Gate to source cutoff voltage

I_D= 10 mA, V_GS= 0

V_GS= ±20 V, V_DS= 0

V_DS= 30 V, V_GS= 0

V_DS= 10 V, I _D= 1 mA

I_D= 10 A, V_GS= 10 V ^Note4

I_D= 10 A, V_GS= 4.5 V ^Note4

I_D= 10 A, V_DS= 5 V ^Note4

V_DS= 10 V

—

±0.1

A

I_DSS

—

V_GS(off)

R_DS(on)

|y_fs|

—

2.5

7.0

10.9

—

Static drain to source on state

resistance

5.8

8.4

m

Forward transfer admittance

Input capacitance

Ciss

Coss

Crss

1180

252

1650

—



V_GS= 0

Output capacitance

Reverse transfer capacitance

Gate Resistance

f = 1MHz

—

1.0

7.7

3.3

2.0

3.8

3.4

13.2

3.8

0.83

9.0

2.2

—

Total gate charge

V_DD= 10 V

V_GS= 4.5 V

I_D= 20 A

Gate to source charge

Gate to drain charge

Turn-on delay time

Rise time

Qgs

Qgd

t_d(on)

t_r

—

V_GS=10 V, I_D= 10 A

V_DD 10 V

R_L= 1.0 

R_g= 4.7 

—

Turn-off delay time

Fall time

t_d(off)

t_f

—

Body–drain diode forward voltage

V_DF

1.08

—

IF = 20 A, V_GS= 0 ^Note4

Body–drain diode reverse

recovery time

t_rr

IF =20 A, V_GS= 0

di_F/ dt = 500 A/s

Notes: 4. Pulse test

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 2 of 10

RJK03R4DPA

• MOS2

Preliminary

(Ta = 25°C)

Item

Symbol

V_(BR)DSS

I_GSS

Min

—

1.2

—

Typ

—

Max

—

Unit

Test Conditions

Drain to source breakdown voltage

Gate to source leak current

I_D= 10 mA, V_GS= 0

V_GS= ±12 V, V_DS= 0

V_DS= 24 V, V_GS= 0

V_DS= 10 V, I _D=1 mA

I_D=25 A, V_GS= 8 V ^Note4

I_D= 25 A, V_GS= 4.5 V ^Note4

I_D= 25 A, V_DS= 5 V ^Note4

V_DS= 10 V

—

±0.5

A

Zero gate voltage drain current

Gate to source cutoff voltage

I_DSS

—

V_GS(off)

R_DS(on)

|y_fs|

—

2.5

2.3

2.8

—

Static drain to source on state

resistance

1.9

2.1

133

6980

740

450

1.0

m

Forward transfer admittance

Input capacitance

Ciss

Coss

Crss

9770

—



V_GS= 0

Output capacitance

Reverse transfer capacitance

Gate Resistance

f = 1MHz

—

2.2

—

Total gate charge

V_DD= 10 V

V_GS= 4.5 V

I_D= 50 A

Gate to source charge

Gate to drain charge

Turn-on delay time

Rise time

Qgs

Qgd

t_d(on)

t_r

—

12.4

6.8

87.2

—

V_GS= 8 V, I_D= 25 A

V_DD 10 V

R_L= 0.4 

R_g= 4.7 

—

Turn-off delay time

Fall time

t_d(off)

t_f

—

Schottky Barrier diode forward voltage

V_F

0.40

10.0

—

IF = 2 A, V_GS= 0 ^Note4

Body–drain diode reverse

recovery time

t_rr

—

IF = 50 A, V_GS= 0

di_F/ dt = 500 A/s

Notes: 4. Pulse

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 3 of 10

RJK03R4DPA

Preliminary

Main Characteristics

• MOS1

Power vs. Temperature Derating

Maximum Safe Operation Area

1000

100

Operation in

this area is

limited by R_DS(on)

Tc = 25 °C

1 shot Pulse

0.1

100

150

200

Drain to Source Voltage V_DS(V)

Case Temperature Tc (°C)

Typical Output Characteristics

Typical Transfer Characteristics

3.4 V

Pulse Test

4.5 V

10 V

V_DS= 5 V

Pulse Test

3.2 V

3.0 V

2.8 V

25°C

_GS= 2.6 V

Tc = 75°C

–25°C

Drain to Source Voltage V_DS(V)

Gate to Source Voltage V_GS(V)

Static Drain to Source On State Resistance

vs. Drain Current

Drain to Source Saturation Voltage vs.

Gate to Source Voltage

100

160

Pulse Test

120

V_GS= 4.5 V

10 V

I_D= 10 A

5 A

2 A

0.1 0.3

100

Gate to Source Voltage V_GS(V)

Drain Current I_D(A)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 4 of 10

RJK03R4DPA

Preliminary

Static Drain to Source On State Resistance

vs. Temperature

Typical Capacitance vs.

Drain to Source Voltage

10000

3000

1000

Pulse Test

I_D= 2 A, 5 A, 10 A

Ciss

V_GS= 4.5 V

300

100

Coss

Crss

2 A, 5 A, 10 A

10 V

V_GS= 0

f = 1 MHz

–25

50 75 100 125 150

Case Temperature Tc (°C)

Drain to Source Voltage V_DS(V)

Reverse Drain Current vs.

Source to Drain Voltage

Dynamic Input Characteristics

I_D= 20 A

V_GS

10 V

Pulse Test

5 V

V_DD= 25 V

10 V

V_DS

V_GS= 0, –5 V

V_DD= 25 V

10 V

0.4

0.8

1.2

1.6

2.0

Source to Drain Voltage V_SD(V)

Gate Charge Qg (nc)

Maximum Avalanche Energy vs.

Channel Temperature Derating

100

125

150

Channel Temperature Tch (°C)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 5 of 10

RJK03R4DPA

Preliminary

Normalized Transient Thermal Impedance vs. Pulse Width

D = 1

0.5

0.3

0.1

D =

0.03

0.01

1 m

10 m

100 m

Pulse Width PW (S)

Avalanche Test Circuit

Avalanche Waveform

V_DSS

E_AS

L • I_AP

•

V_DSS– V_DD

V_DS

Monitor

I_AP

Monitor

V_(BR)DSS

I_AP

V_DS

V_DD

D. U. T

I_D

Vin

V_DD

Switching Time Test Circuit

Switching Time Waveform

90%

Vout

Monitor

Vin Monitor

D.U.T.

10%

Vin

R_L

Vout

10%

V_DS

= 10 V

Vin

90%

d(on)

d(off)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 6 of 10

RJK03R4DPA

• MOS2

Preliminary

Power vs. Temperature Derating

Maximum Safe Operation Area

1000

100

Operation in

this area is

limited by R_DS(on)

Tc = 25 °C

1 shot Pulse

0.1

100

150

200

Drain to Source Voltage V_DS(V)

Case Temperature Tc (°C)

Typical Output Characteristics

Typical Transfer Characteristics

Pulse Test

4.5 V

10 V

V_DS= 5 V

Pulse Test

2.8 V

2.7 V

2.6 V

25°C

_GS= 2.5 V

Tc = 75°C

–25°C

Drain to Source Voltage V_DS(V)

Gate to Source Voltage V_GS(V)

Static Drain to Source On State Resistance

vs. Drain Current

Drain to Source Saturation Voltage vs.

Gate to Source Voltage

Pulse Test

V_GS= 4.5 V

8 V

_D= 20 A

10 A

5 A

0.3

0.1

100 300 1000

Gate to Source Voltage V_GS(V)

Drain Current I_D(A)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 7 of 10

RJK03R4DPA

Preliminary

Static Drain to Source On State Resistance

vs. Temperature

Typical Capacitance vs.

Drain to Source Voltage

10000

3000

1000

Pulse Test

Ciss

I_D= 5 A, 10 A, 20 A

Coss

Crss

V_GS= 4.5 V

300

100

5 A, 10 A, 20 A

10 V

V_GS= 0

f = 1 MHz

–25

50 75 100 125 150

Case Temperature Tc (°C)

Drain to Source Voltage V_DS(V)

Reverse Drain Current vs.

Source to Drain Voltage

Dynamic Input Characteristics

I_D= 50 A

100

10 V

Pulse Test

5 V

V_GS

V_DD= 25 V

10 V

V_DS

V_GS= 0, –5 V

V_DD= 25 V

10 V

100

0.4

0.8

1.2

1.6

2.0

Source to Drain Voltage V_SD(V)

Gate Charge Qg (nc)

Maximum Avalanche Energy vs.

Channel Temperature Derating

100

125

150

Channel Temperature Tch (°C)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 8 of 10

RJK03R4DPA

Preliminary

Normalized Transient Thermal Impedance vs. Pulse Width

D = 1

0.5

0.3

0.1

D =

0.03

0.01

1 m

10 m

100 m

Pulse Width PW (S)

Avalanche Test Circuit

Avalanche Waveform

V_DSS

E_AS

L • I_AP

•

V_DSS– V_DD

V_DS

Monitor

I_AP

Monitor

V_(BR)DSS

I_AP

V_DS

V_DD

D. U. T

I_D

Vin

V_DD

Switching Time Test Circuit

Switching Time Waveform

90%

Vout

Monitor

Vin Monitor

D.U.T.

10%

Vin

R_L

Vout

10%

V_DS

= 10 V

Vin

90%

d(on)

d(off)

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 9 of 10

RJK03R4DPA

Preliminary

Package Dimensions

Package Name

JEITA Package Code

RENESAS Code

PWSN0008DD-B

Previous Code

WPAK-D(3)V

MASS[Typ.]

0.07g

Unit : mm

WPAK-D(3)

⎯

5.1 0.2

0.85 Max

0.47 0.08

3.92 0.22

0.21 Typ

1.27 Typ

0.545Typ

0.945 0.16

2.92 0.22

4.9 0.1

(Sn plating)

Ordering Information

Orderable Part Number

Quantity

Shipping Container

RJK03R4DPA-00-J5A

3000 pcs

Taping

Note: The symbol of 2nd "-" is occasionally presented as "#".

R07DS0888EJ0110 Rev.1.10

Oct 29, 2012

Page 10 of 10

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Colophon 2.2

RJK03R4DPA-00-J5A [RENESAS]

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