UPD98431S1-F6 [RENESAS]
8 CHANNEL(S), 100Mbps, LOCAL AREA NETWORK CONTROLLER, PBGA352, 35 X 35 MM, BGA-352;
| 型号： | UPD98431S1-F6 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8 CHANNEL(S), 100Mbps, LOCAL AREA NETWORK CONTROLLER, PBGA352, 35 X 35 MM, BGA-352 局域网 数据传输 外围集成电路 |
| 文件： | 总38页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98431
10/100 Mbps EthernetTM CONTROLLER
DESCRIPTION
The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control (MAC) ports conforming
to IEEE 802.3 and IEEE 802.3u.
Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the
generation of receive packet loss.
Both a 32-bit dual bus and 64-bit single bus FIFO bus interface are supported for interfacing with higher systems.
Both provide a high-speed 66 MHz bus interface.
This controller is suitable for applications such as LAN switches and routers since a statistics counter is provided
on each port to support RMON/SNMP.
Detailed function descriptions are provided in the following User’s Manual. Be sure to read them before
designing.
µPD98431 User’s Manual: (S14054E)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Eight 10/100 Mbps Ethernet MAC ports conforming to IEEE 802.3 and IEEE 802.3u
Supports MII and 10 Mbps serial interface as interface with physical layer devices
Each port has 2 KB of receive FIFO and 512 bytes of transmit FIFO.
High-speed FIFO data bus interface of 32/64 bits × 66 MHz
Full-duplex operation and IEEE 802.3x flow control
Statistics counter supporting RMON/SNMP
Filtering conditions can be set according to address type
VLAN frame detection function
Mirror port function
JTAG support
Supply voltage: 3.3 V
ORDERING INFORMATION
Part Number
Package
µPD98431S1-F6
352-pin plastic BGA (35 × 35)
Remark Active low pins/signals are indicated as ×××# (symbol # after pin/signal names) in this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14150EJ4V0DS00 (4th edition)
Date Published March 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
1999
©
µPD98431
BLOCK DIAGRAM
PORT#7
PORT#6
MII/10M serial × 8
PORT#5
PORT#4
PORT#3
•
•
•
•
•
•
PORT#2
PORT#1
PORT#0
FIFO
DATA BUS
FIFO DATA
Common
bus
TX-FIFO
10/100M
MAC
RX-FIFO
Interface
Register/Statistics Counter
CPU BUS
TEST port
MII
CPU bus
Interface
serial management
MII
management
Interface
JTAG
SYSTEM CONFIGURATION EXAMPLE of SWITCH/ROUTER
Address Search
Line Interface Module
(LIM)
Control Module
Memory
CPU
µPD98421
10/100M
Multi-MAC
Optical
Switch
Forwarding
Engine
10/100M
µPD98431
Module
Chip
Multi-PHY
Line Interface Module
(LIM)
Address Search
10/100/1000M
Multi-MAC
µPD98421
Switch
Chip
Optical
Module
10/100/1000M
Multi-PHY
Forwarding
Engine
LIM
µPD98433
Switching
Module
2
Data Sheet S14150EJ4V0DS
µPD98431
PIN CONFIGURATION
352-pin plastic BGA (35 × 35)
µPD98431S1-F6
PD98431
µ
352-pin plastic BGA
Top View
Index mark
51 52
60
70
75 76
26
24
22
20
18
16
14
12
10
8
50 147 148
146 235 236
234 315 316
150
160
169 170 77
25
23
21
19
17
15
13
11
9
240
250
255 256 171
333 334 257
335
320
330
314
80
260
230
140
310
340
40
180
PD98431
µ
352-pin plastic BGA
Bottom View
90
270
220
130
300
297
350
352
7
6
275 190
30
5
280
215 296 295
125 214 213
290
200
110
10
277 276 191
4
210
20
193 192 99
101 100
3
27 124 123
26 25
120
2
2
1
1
AE AC AA
AF AD AB
W
U
R
N
L
J
G
E
C
A
Index mark
Y
V
T
P
M
K
H
F
D
B
3
Data Sheet S14150EJ4V0DS
µPD98431
PIN NAMES
(1/2)
Pin No.
Pin Name
Pin No.
Pin Name
D28
Pin No.
Pin Name
Pin No.
151 (AA25) D16
152 (Y25) D13
153 (W25) D9
Pin Name
1 (A1)
TXFD30/FD62
TXFD29/FD61
TXFD26/FD58
TXFD23/FD55
TXFD20/FD52
TXFD17/FD49
TXFD14/FD46
TXFD10/FD42
TXFD7/FD39
TXFD4/FD36
TXFD0/FD32
RXFDQ2/FDQ2
RXFD31/FD31
RXFD30/FD30
RXFD29/FD29
RXFD27/FD27
RXFD24/FD24
RXFD21/FD21
RXFD18/FD18
RXFD14/FD14
RXFD11/FD11
RXFD8/FD8
RXFD4/FD4
RXFD0/FD0
TEST0
51 (AF26)
101 (B2)
102 (C2)
103 (D2)
104 (E2)
105 (F2)
106 (G2)
107 (H2)
108 (J2)
109 (K2)
110 (L2)
111 (M2)
112 (N2)
113 (P2)
114 (R2)
115 (T2)
116 (U2)
117 (V2)
118 (W2)
119 (Y2)
TXFD27/FD59
TXFD28/FD60
TXFD24/FD56
TXFD21/FD53
TXFD18/FD50
TXFD15/FD47
TXFD11/FD43
TXFD8/FD40
TXFD5/FD37
TXFD1/FD33
RXFDQ1/FDQ1
FCLK
2 (B1)
52 (AE26) D27
53 (AD26) D24
54 (AC26) D21
55 (AB26) D18
56 (AA26) D15
3 (C1)
4 (D1)
154 (V25)
155 (U25)
156 (T25)
157 (R25)
158 (P25)
159 (N25)
D6
D3
5 (E1)
6 (F1)
TXFBA7
TXFBA4
TXFBA0
TXFBA1
7 (G1)
57 (Y26)
58 (W26)
59 (V26)
60 (U26)
61 (T26)
62 (R26)
63 (P26)
64 (N26)
65 (M26)
66 (L26)
67 (K26)
68 (J26)
69 (H26)
70 (G26)
71 (F26)
72 (E26)
73 (D26)
74 (C26)
75 (B26)
76 (A26)
77 (A25)
78 (A24)
79 (A23)
80 (A22)
81 (A21)
82 (A20)
83 (A19)
84 (A18)
85 (A17)
86 (A16)
87 (A15)
88 (A14)
89 (A13)
90 (A12)
91 (A11)
92 (A10)
93 (A9)
D12
8 (H1)
D8
9 (J1)
D5
10 (K1)
11 (L1)
12 (M1)
13 (N1)
14 (P1)
15 (R1)
16 (T1)
17 (U1)
18 (V1)
19 (W1)
20 (Y1)
21 (AA1)
22 (AB1)
23 (AC1)
24 (AD1)
25 (AE1)
26 (AF1)
27 (AF2)
28 (AF3)
29 (AF4)
30 (AF5)
31 (AF6)
32 (AF7)
33 (AF8)
34 (AF9)
D2
160 (M25) TXFPT2
TXFBA6
TXFBA3
RXFPT2
RXFPT1
RXFPT0
TXFPT1
TXFDQ2
RXFEN#/FEN#
SKIP
161 (L25)
162 (K25)
163 (J25)
164 (H25)
TXFPT0
TXFDQ1
TXFEN#/FRW
ACK#
RXFA
RXFD28/FD28
RXFD26/FD26
RXFD23/FD23
RXFD20/FD20
RXFD17/FD17
RXFD13/FD13
165 (G25) RW
166 (F25)
167 (E25)
168 (D25)
169 (C25)
170 (B25)
171 (B24)
172 (B23)
173 (B22)
174 (B21)
175 (B20)
176 (B19)
177 (B18)
178 (B17)
179 (B16)
180 (B15)
181 (B14)
182 (B13)
183 (B12)
184 (B11)
185 (B10)
186 (B9)
187 (B8)
188 (B7)
189 (B6)
190 (B5)
191 (B4)
192 (B3)
193 (C3)
194 (D3)
195 (E3)
196 (F3)
A8
A5
A3
TCK
CS#
120 (AA2) RXFD10/FD10
121 (AB2) RXFD7/FD7
122 (AC2) RXFD5/FD5
123 (AD2) RXFD1/FD1
124 (AE2) TXD43
125 (AE3) TXEN4
126 (AE4) TXD40
127 (AE5) RXDV4
128 (AE6) RXD41
129 (AE7) COL5
130 (AE8) TXEN5
131 (AE9) TXD51
132 (AE10) RXDV5
133 (AE11) RXD51
134 (AE12) COL6
135 (AE13) TXD63
136 (AE14) TXEN6
137 (AE15) TXCLK6
138 (AE16) RXDV6
139 (AE17) RXD60
140 (AE18) CRS7
141 (AE19) TXD73
142 (AE20) TXD70
143 (AE21) RXDV7
144 (AE22) RXD71
145 (AE23) RXCLK7
146 (AE24) TEST2
147 (AE25) D25
TEST3
A9
MDIO
A6
TXER0
A2
TXD02
TDO
TXCLK0
RXD03
TRST#
TDI
CRS4
RXD00
TXER4
MDC
CRS1
TXD42
COL0
TXD12
TXCLK4
TXEN0
TXD01
RXER0
RXD02
RXCLK0
TXER1
TXD11
RXER1
RXD12
COL2
TXCLK1
RXD13
RXD43
RXD40
RXCLK1
RXD10
CRS5
TXD53
TXEN2
TXD50
TXD22
35 (AF10) RXD53
36 (AF11) RXD50
37 (AF12) CRS6
38 (AF13) TXD62
39 (AF14) TXD61
40 (AF15) TXD60
41 (AF16) RXER6
42 (AF17) RXD61
43 (AF18) COL7
44 (AF19) TXEN7
45 (AF20) TXD71
46 (AF21) RXER7
47 (AF22) RXD72
48 (AF23) RESET#
49 (AF24) D31
RXER2
RXD22
RXCLK2
TXER3
CRS2
TXD32
TXER2
TXD23
TXCLK2
RXD23
RXD20
CRS3
TXCLK3
RXDV3
RXD30
TXFD31/FD63
TXFD25/FD57
TXFD22/FD54
TXFD19/FD51
TXFD16/FD48
TXFD12/FD44
TXFD9/FD41
TXFD6/FD38
94 (A8)
95 (A7)
96 (A6)
TXD33
TXD30
RXD33
RXCLK3
TEST1
97 (A5)
197 (G3)
198 (H3)
199 (J3)
98 (A4)
148 (AD25) D26
99 (A3)
149 (AC25) D22
50 (AF25) D30
100 (A2)
150 (AB25) D19
200 (K3)
Remark Active low pins/signals are indicated as ×××# (symbol # after pin/signal names) in this document.
4
Data Sheet S14150EJ4V0DS
µPD98431
(2/2)
Pin No.
Pin Name
Pin No.
Pin Name
D14
Pin No.
Pin Name
GND
Pin No.
Pin Name
201 (L3)
202 (M3)
203 (N3)
204 (P3)
205 (R3)
206 (T3)
207 (U3)
208 (V3)
209 (W3)
210 (Y3)
TXFD3/FD35
TXFD2/FD34
RXFDQ0/FDQ0
RXFDQ3/FDQ3
RXFD25/FD25
RXFD22/FD22
RXFD19/FD19
RXFD16/FD16
RXFD12/FD12
RXFD9/FD9
239 (Y24)
277 (D4)
278 (E4)
279 (F4)
280 (G4)
281 (H4)
282 (J4)
283 (K4)
284 (L4)
285 (M4)
286 (N4)
287 (P4)
288 (R4)
289 (T4)
290 (U4)
291 (V4)
292 (W4)
293 (Y4)
315 (AC23) GND
316 (AB23) GND
317 (AA23) VDD
240 (W24) D10
GND
241 (V24)
242 (U24)
243 (T24)
244 (R24)
245 (P24)
246 (N24)
D7
VDD
D4
GND
318 (Y23)
GND
D1
GND
319 (W23) GND
D0
TXFD13/FD45
VDD
320 (V23)
321 (U23)
322 (T23)
323 (R23)
324 (P23)
325 (N23)
D11
TXFBA5
TXFBA2
VDD
GND
VDD
GND
GND
GND
247 (M24) TXFDQ3
VDD
248 (L24)
249 (K24)
250 (J24)
251 (H24)
TXFDQ0
PASS
HCLK
A10
GND
211 (AA3) RXFD6/FD6
212 (AB3) RXFD3/FD3
213 (AC3) RXFD2/FD2
214 (AD3) COL4
215 (AD4) TXD41
216 (AD5) RXER4
217 (AD6) RXD42
218 (AD7) RXCLK4
219 (AD8) TXER5
220 (AD9) TXD52
221 (AD10) RXER5
222 (AD11) TXCLK5
223 (AD12) RXD52
224 (AD13) RXCLK5
225 (AD14) TXER6
226 (AD15) RXD63
227 (AD16) RXCLK6
228 (AD17) TXER7
229 (AD18) TXD72
230 (AD19) TXCLK7
231 (AD20) RXD73
232 (AD21) RXD70
233 (AD22) TEST4
234 (AD23) TEST5
235 (AD24) D29
GND
VDD
326 (M23) VDD
GND
327 (L23)
328 (K23)
329 (J23)
330 (H23)
GND
VDD
INT#
GND
252 (G24) A7
VDD
253 (F24)
254 (E24)
255 (D24)
256 (C24)
257 (C23)
258 (C22)
259 (C21)
260 (C20)
261 (C19)
262 (C18)
263 (C17)
264 (C16)
265 (C15)
266 (C14)
267 (C13)
268 (C12)
269 (C11)
270 (C10)
271 (C9)
A4
RXFD15/FD15
GND
A1
A0
GND
331 (G23) GND
TMS
294 (AA4) VDD
295 (AB4) GND
296 (AC4) GND
297 (AC5) VDD
298 (AC6) CLAMP
299 (AC7) GND
300 (AC8) VDD
301 (AC9) CLAMP
302 (AC10) GND
303 (AC11) VDD
304 (AC12) CLAMP
305 (AC13) GND
306 (AC14) RXD62
307 (AC15) VDD
308 (AC16) VDD
309 (AC17) GND
310 (AC18) CLAMP
311 (AC19) VDD
312 (AC20) GND
313 (AC21) CLAMP
314 (AC22) VDD
332 (F23)
333 (E23)
334 (D23)
335 (D22)
336 (D21)
337 (D20)
338 (D19)
339 (D18)
340 (D17)
341 (D16)
342 (D15)
343 (D14)
344 (D13)
345 (D12)
346 (D11)
347 (D10)
348 (D9)
VDD
CRS0
TXD03
TXD00
RXDV0
RXD01
COL1
TXD13
TXEN1
TXD10
RXDV1
RXD11
TXD21
RXDV2
RXD21
COL3
TXEN3
TXD31
RXER3
RXD32
RXD31
GND
GND
VDD
CLAMP
GND
VDD
CLAMP
GND
VDD
CLAMP
GND
TXD20
VDD
VDD
GND
272 (C8)
CLAMP
VDD
273 (C7)
349 (D8)
236 (AC24) D23
274 (C6)
350 (D7)
GND
237 (AB24) D20
275 (C5)
351 (D6)
CLAMP
VDD
238 (AA24) D17
276 (C4)
352 (D5)
Remark Active low pins/signals are indicated as ×××# (symbol # after pin/signal names) in this document.
5
Data Sheet S14150EJ4V0DS
µPD98431
1. PIN FUNCTIONS
(1) Register interface
Pin Name
CS#
Pin No.
I/O
Function
70
Input
Chip select.
When this signal is low, the internal registers of the chip can be accessed.
RW
165
Input
Input
Host read/write.
This pin is used by the host system to access the register bus. When a high
level is input to this pin, the register bus is accessed for read. When a low
level is input, the register bus is accessed for write.
A[10:0]
251, 71, 166, 252,
72, 167, 253, 168,
73, 254, 255
Register address.
The address necessary for selecting a port or register to be accessed when
an internal register of the µPD98431 is to be accessed is given to A[10:0].
The µPD98431 has a 32-bit register for each port. A[10:8] specifies a port,
and [A7:0] specifies a register address.
The relationship between the setting of A[10:8] and a port number is as
follows:
Port 0 → A[10:8] = 000B
Port 1 → A[10:8] = 001B
Port 2 → A[10:8] = 010B
Port 3 → A[10:8] = 011B
Port 4 → A[10:8] = 100B
Port 5 → A[10:8] = 101B
Port 6 → A[10:8] = 110B
Port 7 → A[10:8] = 111B
D[31:0]
49, 50, 235, 51,
I/O,
Register data.
52, 148, 147, 53,
236, 149, 54, 237,
150, 55, 238, 151,
56, 239, 152, 57,
320, 240, 153, 58,
241, 154, 59, 242,
155, 60, 243, 244
3-state
These pins form a bidirectional data bus through which the internal registers
of the µPD98431 are accessed.
INT#
329
Output,
open
Interrupt signal.
Interrupt request signal. This signal goes low if an interrupt source is generated.
It is kept low until all the interrupt statuses are cleared if an interrupt occurs.
This signal is an open-drain output signal.
drain
RESET#
ACK#
HCLK
48
Input
Hardware reset.
Active-low asynchronous reset signal. Immediately after hardware reset, all
the registers are set to their default values, and all the FIFOs and counters
are cleared.
164
250
Output,
3-state
Register data acknowledge.
This signal indicates that the data on D[31:0] is valid when a register is read.
When this signal is low, the data read from the register exists on D[31:0].
When a register is written, this signal indicates completion of the writing.
Input
Register interface clock.
This pin inputs a synchronization clock used to access a register. The
maximum frequency of the input clock is 66 MHz.
Caution Set HCLK so that its frequency always exceeds the frequency of
RXCLK and TXCLK.
6
Data Sheet S14150EJ4V0DS
µPD98431
(2) FIFO interface
(1/3)
Pin Name
Pin No.
I/O
Function
RXFEN#/
FEN#
68
Input
FIFO bus reception enable/FIFO bus enable.
The function of this signal differs as follows depending on the FIFO bus
mode:
(1) 32-bit dual bus mode
In this mode, this signal functions as RXFEN#. If this signal goes low,
the receive FIFO bus interface is enabled, and data can be read from the
receive FIFO.
(2) 64-bit single bus mode
In this mode, this signal functions as FEN#. If this signal goes low, the
FIFO bus interface is enabled, and data can be read from the receive
FIFO or written to the transmit FIFO.
TXFEN#/
FRW
163
Input
FIFO bus transmission enable/FIFO bus direction.
The function of this signal differs as follows depending on the FIFO bus
mode:
(1) 32-bit dual bus mode
In this mode, this signal functions as TXFEN#. If this signal goes low,
the transmit FIFO bus interface is enabled, and data can be written to
the transmit FIFO.
(2) 64-bit single bus mode
In this mode, this signal functions as FRW, and specifies the direction of
FIFO bus access.
While this signal is high, the FIFO bus is accessed by the receive FIFO
for read.
While it is low, the bus is accessed by the transmit FIFO for write.
FCLK
112
Input
FIFO bus clock.
The FIFO bus is synchronized with FCLK. The maximum frequency of the
input clock is 66 MHz.
Caution Set FCLK so that its frequency always exceeds the frequency
of RXCLK and TXCLK.
RXFPT[2:0]
63 to 65
Output,
3-state
Receive port number.
These signals indicate a port number from which receive data is output when
the receive FIFO is accessed for read. The relation between RXFPT[2:0] and
a port number is as follows:
Port 0 → RXFPT[2:0] = 000B
Port 1 → RXFPT[2:0] = 001B
Port 2 → RXFPT[2:0] = 010B
Port 3 → RXFPT[2:0] = 011B
Port 4 → RXFPT[2:0] = 100B
Port 5 → RXFPT[2:0] = 101B
Port 6 → RXFPT[2:0] = 110B
Port 7 → RXFPT[2:0] = 111B
7
Data Sheet S14150EJ4V0DS
µPD98431
(2/3)
Pin Name
Pin No.
I/O
Function
TXFPT[2:0]
160, 66, 161
Input
Transmit port number.
These signals indicate the port number of the transmit FIFO to which transmit
data is written when the transmit FIFO is accessed for write. The relation
between TXFPT[2:0] and a port number is as follows:
Port 0 → TXFPT[2:0] = 000B
Port 1 → TXFPT[2:0] = 001B
Port 2 → TXFPT[2:0] = 010B
Port 3 → TXFPT[2:0] = 011B
Port 4 → TXFPT[2:0] = 100B
Port 5 → TXFPT[2:0] = 101B
Port 6 → TXFPT[2:0] = 110B
Port 7 → TXFPT[2:0] = 111B
TXFD[31:0],
RXFD[31:0]/
FD[63:0]
193, 1, 2, 102,
Input,
Output,
I/O,
32-bit transmit FIFO data bus, 32-bit receive FIFO data bus/64-bit FIFO
data bus.
101, 3, 194, 103,
4, 195, 104, 5,
These signals provide the data bus of the FIFO bus interface. The functions
of these signals differ as follows depending on the FIFO bus mode.
196, 105, 6, 197,
106, 7, 282, 198,
107, 8, 199, 108,
9, 200, 109, 10,
201, 202, 110, 11,
13 to 15, 114, 16,
115, 205, 17, 116,
206, 18, 117, 207,
19, 118, 208, 291,
20, 119, 209, 21,
120, 210, 22, 121,
211, 122, 23, 212,
213, 123, 24
3-state
(1) 32-bit dual bus mode
These signals function as TXFD[31:0] and RXFD[31:0]. This 64-bit data
bus is divided into two unidirectional buses, TXFD[31:0] and RXFD[31:0],
when the BUSWTH bit of the MISCR register is cleared to 0.
(2) 64-bit single bus mode
These signals function as FD[63:0]. This 64-bit data bus is used as a
64-bit bidirectional bus to access the FIFO when the BUSWTH bit of the
MISCR register is set to 1.
TXFDQ[3:0]
247, 67, 162, 248
Input
Transmit data attribute.
These signals indicate the attribute of the transmit data on the FIFO bus in
the 32-bit dual bus mode. They indicate the attribute of the transmit data on
FD[63:0] when the transmit FIFO is accessed for write.
These signals are meaningless in the 64-bit single bus mode.
RXFDQ[3:0]/
FDQ[3:0]
204, 12, 111, 203
Output,
I/O,
Receive data attribute/FIFO bus attribute.
These signals indicate the attribute of data on the FIFO bus. The functions of
these signals differ as follows depending on the bus mode:
3-state
(1) 32-bit dual bus mode
These signals function as RXFDQ[3:0] and output the attribute of the
receive data output onto RXFD[31:0] when the FIFO bus is accessed by
the receive FIFO for read.
(2) 64-bit single bus mode
These signals function as FDQ[3:0] and input the attribute of the transmit
data on FD[63:0] when the transmit FIFO is accessed for write. When
the receive FIFO is accessed for read, the attribute of the receive data
output onto FD[63:0] is output.
8
Data Sheet S14150EJ4V0DS
µPD98431
(3/3)
Pin Name
Pin No.
I/O
Function
TXFBA[7:0]
156, 61, 245, 157,
62, 246, 159, 158
Output,
3-state
Transmit FIFO buffer available.
When these signals are high, the transmit FIFO has space to which transmit
data can be written. If the quantity of the data in the transmit FIFO exceeds
the value set to the TFDMH field of the TFIC register, these signals go low.
A TXFBA signal is provided for each port, and TXFBA[n] is the TXFBA signal
of port n.
RXFA
113
Output,
3-state
Receive frame available.
When this signal is high, the port indicated by RXFPT has at least one packet
from the receive data stream that is ready to be transferred to the host
system.
PASS
SKIP
249
69
Input
Input
Receive frame pass.
This signal is input to start transfer of the receive data currently on the FIFO
bus when the bus is accessed by the receive FIFO for read.
Receive frame skip.
This signal is input to skip the port currently on the FIFO bus and read data
from the next port when the FIFO bus is accessed by the receive FIFO for
read.
9
Data Sheet S14150EJ4V0DS
µPD98431
(3) MII (Media Independent Interface)
(1/3)
Pin Name
Pin No.
I/O
Function
TXCLK[7:0]
230, 137, 222, 29,
190, 92, 179, 174
Input
MII transmit clock.
These pins input the transmit clock (duty: 50%) necessary for outputting data
to the PHY device connected to each port. Transmit data from each port,
TXD7[3:0] through TXD0[3:0], and TXEN[7:0] that indicates that the transmit
data on TXD is valid are output to each port in synchronization with this clock.
In the MII mode, a 2.5 MHz clock is input for 10 Mbps operation, and a 25
MHz clock is input for 100 Mbps operation. In this mode, TXD and TXEN are
output in synchronization with the rising of TXCLK.
In the 10 Mbps serial mode, a 10 MHz clock is input. In this mode, TXD and
TXEN are output in synchronization with the rising of TXCLK. For the unused
ports, fix TXCLK to high or low level.
TXD0[3:0]
TXD1[3:0]
TXD2[3:0]
TXD3[3:0]
TXD4[3:0]
TXD5[3:0]
258, 173, 80, 259
263, 178, 85, 265
91, 184, 268, 344
96, 189, 273, 97
124, 28, 215, 126
33, 220, 131, 34
Output
Output
Output
Output
Output
Output
MII transmit data (port 0).
These pins output transmit data to the PHY device connected to port 0.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK0.
In the 10 Mbps serial mode, only TXD0[0] is used to output serial transmit
data at the rising edge of TXCLK0.
MII transmit data (port 1).
These pins output transmit data to the PHY device connected to port 1.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK1.
In the 10 Mbps serial mode, only TXD1[0] is used to output serial transmit
data at the rising edge of TXCLK1.
MII transmit data (port 2).
These pins output transmit data to the PHY device connected to port 2.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK2.
In the 10 Mbps serial mode, only TXD2[0] is used to output serial transmit
data at the rising edge of TXCLK2.
MII transmit data (port 3).
These pins output transmit data to the PHY device connected to port 3.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK3.
In the 10 Mbps serial mode, only TXD3[0] is used to output serial transmit
data at the rising edge of TXCLK3.
MII transmit data (port 4).
These pins output transmit data to the PHY device connected to port 4.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK4.
In the 10 Mbps serial mode, only TXD4[0] is used to output serial transmit
data at the rising edge of TXCLK4.
MII transmit data (port 5).
These pins output transmit data to the PHY device connected to port 5.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK5.
In the 10 Mbps serial mode, only TXD5[0] is used to output serial transmit
data at the rising edge of TXCLK5.
10
Data Sheet S14150EJ4V0DS
µPD98431
(2/3)
Pin Name
TXD6[3:0]
Pin No.
I/O
Function
135, 38 to 40
MII transmit data (port 6).
Output
These pins output transmit data to the PHY device connected to port 6.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK6.
In the 10 Mbps serial mode, only TXD6[0] is used to output serial transmit
data at the rising edge of TXCLK6.
TXD7[3:0]
TXEN[7:0]
RXCLK[7:0]
141, 229, 45, 142
MII transmit data (port 7).
Output
Output
Input
These pins output transmit data to the PHY device connected to port 7.
In the MII mode, transmit data of nibble width (4 bits wide) is output at the
rising edge of TXCLK7.
In the 10 Mbps serial mode, only TXD7[0] is used to output serial transmit
data at the rising edge of TXCLK7.
44, 136, 130, 125,
272, 183, 264, 79
MII transmission enable.
These signals indicate whether the transmit data (TXD) of each port is valid.
In the 10 Mbps serial mode, they remain high starting from the fist bit of a
preamble, until the last bit of the transmit frame is output.
In the MII mode, they remain high starting from the first nibble data indicating
a preamble, until the last nibble data of the transmit frame is output.
145, 227, 224,
218, 99, 187, 181,
83,
MII receive clock.
These pins input the clock (duty: 50%) received from the PHY device.
RXD7[3:0] through RXD0[3:0] that are the data received from each port, and
TXEN[7:0] that indicates the existence of transmit data on TXD are output in
synchronization with this clock.
In the MII mode, a 2.5 MHz clock is input for 10 Mbps operation, and a 25
MHz clock is input for 100 Mbps operation. In this mode, RXD and RXDV are
input at the rising edge of RXCLK.
In the 10 Mbps serial mode, a 10 MHz clock is input. In this mode, RXD is
input at the rising edge of RXCLK.
Fix RXCLK of an unused port to the high or low level.
RXD0[3:0]
RXD1[3:0]
RXD2[3:0]
RXD3[3:0]
175, 82, 261, 176
180, 87, 267, 182
93, 186, 270, 94
98, 275, 276, 192
Input
Input
Input
Input
MII receive data (port 0).
These pins input data received from the PHY device connected to port 0.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK0.
In the 10 Mbps serial mode, only RXD0[0] is used and serial receive data is
input at the rising edge of RXCLK0.
MII receive data (port 1).
These pins input data received from the PHY device connected to port 1.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK1.
In the 10 Mbps serial mode, only RXD1[0] is used and serial receive data is
input at the rising edge of RXCLK1.
MII receive data (port 2).
These pins input data received from the PHY device connected to port 2.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK2.
In the 10 Mbps serial mode, only RXD2[0] is used and serial receive data is
input at the rising edge of RXCLK2.
MII receive data (port 3).
These pins input data received from the PHY device connected to port 3.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK3.
In the 10 Mbps serial mode, only RXD3[0] is used and serial receive data is
input at the rising edge of RXCLK3.
11
Data Sheet S14150EJ4V0DS
µPD98431
(3/3)
Pin Name
RXD4[3:0]
Pin No.
I/O
Function
Input
30, 217, 128, 31
MII receive data (port 4).
These pins input data received from the PHY device connected to port 4.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK4.
In the 10 Mbps serial mode, only RXD4[0] is used and serial receive data is
input at the rising edge of RXCLK4.
Input
Input
Input
RXD5[3:0]
RXD6[3:0]
RXD7[3:0]
35, 223, 133, 36
226, 306, 42, 139
231, 47, 144, 232
MII receive data (port 5).
These pins input data received from the PHY device connected to port 5.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK5.
In the 10 Mbps serial mode, only RXD5[0] is used and serial receive data is
input at the rising edge of RXCLK5.
MII receive data (port 6).
These pins input data received from the PHY device connected to port 6.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK6.
In the 10 Mbps serial mode, only RXD6[0] is used and serial receive data is
input at the rising edge of RXCLK6.
MII receive data (port 7).
These pins input data received from the PHY device connected to port 7.
In the MII mode, receive data of nibble width (4 bits wide) is input at the rising
edge of RXCLK7.
In the 10 Mbps serial mode, only RXD7[0] is used and serial receive data is
input at the rising edge of RXCLK7.
Input
Input
CRS[7:0]
140, 37, 32, 26,
95, 89, 177, 257
Carrier sense.
These are carrier sense signals input from the PHY device connected to each
port.
Fix CRS of an unused port to the low level.
RXDV[7:0]
143, 138, 132,
127, 191, 269,
266, 260
MII receive data valid.
These signals indicate, in the MII mode, that the data on RXD is valid for
each port.
When these signals are high, the data on RXD is valid.
Fix RXDV of an unused port to the high or low level.
Input
COL[7:0]
43, 134, 129, 214,
271, 88, 262, 78
Collision.
These pins input the collision signals detected by the PHY device connected
to each port.
Fix COL of an unused port to the low level.
TXER[7:0]
RXER[7:0]
228, 225, 219, 27,
188, 90, 84, 172
Output
Input
MII transmission error.
These signals indicate that an error occurs at each port of the µPD98431
during transmission.
46, 41, 221, 216,
274, 185, 86, 81
MII reception error.
These are input signals to detect errors occurring at each port of the PHY
device during reception.
Fix RXER of an unused port to the low level.
MDC
77
Output
I/O
MII management clock.
This is a transfer clock for MII serial management data.
MDIO
171
MII management data.
This is a bidirectional MII serial management data signal.
12
Data Sheet S14150EJ4V0DS
µPD98431
(4) JTAG pins (These functions can be supported upon request.)
Pin Name
TMS
Pin No.
I/O
Function
Input
256
76
JTAG test mode select.
This signal controls the boundary scan state machine. This pin is internally
pulled up. (pull-up resistor: 50 kΩ)
Input
TDI
JTAG test data input.
This signal is serial data input for boundary scan. This pin is internally pulled
up. (pull-up resistor: 50 kΩ)
TDO
TCK
74
Output
3-state
JTAG test data output.
This signal is serial data output for boundary scan.
Input
169
JTAG test clock.
This is clock input used to synchronize test data input and output. This pin is
internally pulled up (pull-up resistor: 50 kΩ)
Input
TRST#
75
JTAG reset.
When this signal is deasserted low, the boundary scan operation is reset.
This signal must be kept high during boundary scan operation. When not
using the JTAG function, fix pins to low.
This pin is internally pulled up. (pull-up resistor: 50 kΩ)
(5) Test pins and power pins
Pin Name
TEST
Pin No.
I/O
Function
234, 233, 170,
146, 100, 25
Input
Test pins.
These pins are used to test the device. Always fix these pins to low.
VDD
279, 283, 285,
288, 290, 294,
297, 300, 303,
307, 308, 311,
314, 317, 321,
323, 326, 328,
332, 335, 338,
341, 345, 346,
349, 352
–
Power supply (+3.3 V)
GND
277, 278, 280,
281, 284, 286,
287, 289, 292,
293, 295, 296,
299, 302, 305,
309, 312, 315,
316, 318, 319,
322, 324, 325,
327, 330, 331,
333, 334, 337,
340, 343, 347,
350
–
Ground (0 V)
CLAMP
298, 301, 304,
310, 313, 336,
339, 342, 348,
351
–
Clamp power supply.
This pin supplies a clamp voltage to the MII buffer circuit. Supply +5 V to this
pin when an external 5 V PHY device is used. Supply +3.3 V when an
external 3.3 V PHY device is used.
13
Data Sheet S14150EJ4V0DS
µPD98431
(6) µPD98431 MII output signal pin connection
When connecting the PHY device to the MII output signals (TXD, TTEN, TXER, MDC, MDIO), connect a serial
resistor of 18 Ω to 27 Ω to each MII output signal as follows so that the drivability of the MII output buffer
accords with the IEEE802.3u standard.
PD98431
18 Ω to 27 Ω
External PHY device
µ
TXD/TXEN/TXER/MDC/MDIO
TXD/TXEN/TXER/MDC/MDIO
14
Data Sheet S14150EJ4V0DS
µPD98431
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
Unit
−0.5 to +4.6
−0.5 to +6.6
−0.5 to +4.6
−0.5 to +7.3
2.60
V
V
Clamp supply voltage
Input/output voltage
VCLAMP
VIO
Except MII signal
MII signal
V
V
Maximum power consumption
Operating temperature
Storage temperature
PMAX
TA
W
°C
°C
−40 to +85
−65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Symbol
VDD
Conditions
MIN.
3.135
3.135
0
TYP.
3.3
MAX.
3.465
5.5
Unit
Supply voltage
V
V
Clamp supply voltage
Operating temperature
VCLAMP
TA
VDD/5.0
°C
70
15
Data Sheet S14150EJ4V0DS
µPD98431
DC Characteristics (TA = 0 to +70°C, VDD = +3.3 V 5%)
Parameter Symbol
Input leakage current ILI
Conditions
VI = 0.0 to 3.3 V
MIN.
TYP.
MAX.
Unit
µA
µA
mA
V
10
10
Output leakage current
Operating current
ILO
VO = 0.0 to 3.3 V
IDD
750
0.8
Clock input voltage, low
Clock input voltage, high
Input voltage, low
VCL
VCH
VIL
VIH
HCLK, FCLK
HCLK, FCLK
2.0
0
V
+0.8
4.6
V
Input voltage, high
Except MII interface
MII interface
2.0
2.0
V
5.5
V
Output voltage, low
VOL
IOL = 6 mA,
0.4
V
FD[63:0], FDQ[3:0], TXFBA[7:0],
RXFPT[2:0], RXFA
IOL = 4 mA,
TXDn [0:3], TXEN[7:0], TXER[7:0]
0.4
0.4
V
V
V
IOL = 3 mA, signals other than
the above
IOH = −6 mA,
VOH
2.4
Output voltage, high
FD[63:0], FDQ[3:0], TXFBA[7:0],
RXFPT[2:0], RXFA
IOH = −4 mA,
TXDn [0:3], TXEN[7:0], TXER[7:0]
2.4
2.4
V
V
IOH = −3 mA, signals other than
the above
Capacitance (TA = 25°C, fC = 1 MHz)
Parameter
Input capacitance
Symbol
CI
Conditions
VI = 0 V
MIN.
TYP.
MAX.
15
Unit
pF
I/O capacitance
CIO
VIO = 0 V
15
pF
AC Characteristics (TA = 0 to +70°C, VDD = +3.3 V 5%)
All AC characteristics values are based on the following conditions.
AC test conditions
• Load condition: 30 pF (1 Schottky TTL gate + CL)
• Input pulse level: 0.4 V to 2.4 V
• Test reference level: 1.5 V
16
Data Sheet S14150EJ4V0DS
µPD98431
Register Bus Interface Timing
Parameter
HCLK clock widthNote
HCLK low-level width
HCLK high-level width
RESET# pulse width
A[10:0] setup time
A[10:0] hold time
Symbol
tCYHK
tHKL
Conditions
MIN.
TYP.
MAX.
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
7
22
tHKH
7
22
tRSL
16 tCYHK
tSHKA
5
0
5
0
5
0
tHHKA
tSHKRW
tHHKRW
tSHKCS
tHHKCS
tDHKAC
tFHKAC
tDHKD
tSHKD
tHHKD
tFHKD
RW setup time
RW hold time
CS# setup time
CS# hold time
tCYHK
10
ACK# output delay time
ACK# float time
10
D[31:0] output delay time
D[31:0] setup time
D[31:0] hold time
10
5
0
D[31:0] float time
10
Note The HCLK clock width must always be shorter than both the RXCLK clock width and TXCLK clock width.
17
Data Sheet S14150EJ4V0DS
µPD98431
(1) HCLK timing
t
HKL
t
HKH
HCLK
t
CYHK
HCLK
RESET#
t
RSL
(2) Register bus interface write timing
HCLK
tSHKA
tHHKA
A[10:0]
tSHKRW
tHHKRW
tHHKCS
RW
tSHKCS
CS#
tDHKAC
tDHKAC
tDHKAC
tFHKAC
ACK#
Hi-Z
Hi-Z
tSHKD
tHHKD
D[31:0]
Hi-Z
Hi-Z
(3) Register bus interface read timing
HCLK
t
SHKA
t
t
t
HHKA
A[10:0]
RW
t
SHKRW
HHKRW
HHKCS
tSHKCS
CS#
tDHKAC
tDHKAC
tDHKAC
tFHKAC
ACK#
D[31:0]
Hi-Z
Hi-Z
Hi-Z
t
DHKD
t
DHKD
t
FHKD
tDHKD
Valid
data
XXXXXXXX
XXXXXXXX
Hi-Z
18
Data Sheet S14150EJ4V0DS
µPD98431
Ethernet Transmit Interface Timing
Parameter
TXDn[3:0] delay time
Symbol
tDTKTD
tDTKTE
tFTKTE
Conditions
MIN.
TYP.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 20 pF
CL = 20 pF
CL = 20 pF
MII mode
Transmit signal assert delay time
Transmit signal deassert delay time
TXCLK clock width
20
20
tCYTK
40/400
100
10 Mbps serial mode
MII mode
TXCLK high-level width
TXCLK low-level width
tTKH
20/200
50
10 Mbps serial mode
MII mode
tTKL
20/200
50
10 Mbps serial mode
(a) 10 Mbps serial mode
(b) MII mode
tCYTK
tTKH
tTKL
t
CYTK
t
TKH
t
TKL
TXCLK
TXDn [0]
TXEN
TXCLK
tDTKTD
tDTKTE
t
t
DTKTD
DTKTE
TXDn [3:0]
TXEN
tFTKTE
t
FTKTE
t
DTKTE
t
FTKTE
TXER
19
Data Sheet S14150EJ4V0DS
µPD98431
Ethernet Receive Interface Timing
Parameter
RXDn[3:0] setup time
RXDn[3:0] hold time
Symbol
tSRDRK
tHRKRD
tSRSRK
tHRKRS
tCYRK
Conditions
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
Receive signal setup time
Receive signal hold time
RXCLK clock width
MII mode
40/400
100
10 Mbps serial mode
MII mode
RXCLK high-level width
RXCLK low-level width
tRKH
20/200
50
10 Mbps serial mode
MII mode
tRKL
20/200
50
10 Mbps serial mode
(a) 10 Mbps serial mode
(b) MII mode
tCYRK
tRKH
tRKL
tCYRK
tRKH
tRKL
RXCLK
RXCLK
tSRDRK
tSRDRK
RXDn [3:0]
RXDV
RXDn [0]
tHRKRD
tHRKRS
tHRKRD
tSRSRK
RXER
tSRSRK
tHRKRS
20
Data Sheet S14150EJ4V0DS
µPD98431
MII Management Interface Timing
Parameter
MDC cycle
Symbol
tCYM
Conditions
MIN.
TYP.
MAX.
1080
Unit
ns
400
tCYHK−5
tCYHK+20
0
MDIO delay time
MDIO setup time
MDIO hold time
tDMCMD
tSMDMC
tHMCMD
tCYHK+10
ns
ns
ns
t
CYM
MDC
(a) Output
(b) Input
MDC
MDC
tDMCMD
tSMDMC tHMCMD
MDIO
(output)
MDIO
(input)
FIFO Bus Interface Write Timing
Parameter
FCLK clock widthNote
Symbol
tCYFK
Conditions
MIN.
15
7
TYP.
MAX.
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FCLK high-level width
tFKH
22
FCLK low-level width
tFKL
7
22
TXFEN#/FRW setup time
TXFEN#/FRW hold time
TXFBA[N] output delay time
TXFBA[N] float time
tSFKTE
tHFKTE
tDFKBA
tFFKBA
tSFKDQ
tHFKDQ
tSFKTP
tHFKTP
tSFKFD
tHFKFD
tSFKRE
tHFKRE
6
0
10
10
TXFDQ[3:0]/FDQ[3:0] setup time
TXFDQ[3:0]/FDQ[3:0] hold time
TXFPT[2:0] setup time
5
0
5
0
6
0
5
0
TXFPT[2:0] hold time
TXFD[31:0]/FD[63:0] setup time
TXFD[31:0]/FD[63:0] hold time
RXFEN#/FEN# setup time
RXFEN#/FEN# hold time
Note The FCLK clock width must always be shorter than both the RXCLK clock width and TXCLK clock width.
Remark TXFBA[N]: N = 0 to 7
21
Data Sheet S14150EJ4V0DS
µPD98431
(1) FIFO bus interface write timing (32-bit dual bus mode)
tCYFK
tFKH
FCLK
TXFEN#
tHFKTE
tSFKTE
tFKL
tDFKBA
tFFKBA
TXFBA[N]
TXFDQ[3]
TXFDQ[2]
TXFDQ[1]
TXFDQ[0]
TXFPT[2:0]
TXFD[31:0]
Hi-Z
Hi-Z
t
HFKDQ
t
SFKDQ
L
t
SFKDQ
tHFKDQ
t
HFKDQ
t
SFKDQ
tSFKTP
tHFKTP
Port enable
tSFKFD
t
HFKFD
3rd
word
4th
word
n−1 th
n th
word
1st
word
2nd
word
n−2 th
word
word
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
24 bits
Idle
Start
Middle
3-byte
ending
Idle
Remark TXFBA[N]: N = 0 to 7
22
Data Sheet S14150EJ4V0DS
µPD98431
(2) FIFO bus interface write timing (64-bit single bus mode)
FCLK
t
HFKRE
HFKTE
t
SFKRE
SFKTE
FEN#
FRW
t
t
tDFKBA
tFFKBA
TXFBA[N]
FDQ[3]
Hi-Z
Hi-Z
t
SFKDQ
SFKDQ
t
HFKDQ
t
t
HFKDQ
HFKDQ
FDQ[2]
tSFKDQ
t
FDQ[1]
tHFKDQ
tSFKDQ
FDQ[0]
tSFKTP
tHFKTP
TXFPT[2:0]
FD[63:0]
Port enable
tSFKFD
t
HFKFD
1st
word
2nd
word
3rd
word
4th
word
n−2 th
n−1 th
n th
word
word
word
64 bits
64 bits
64 bits
64 bits
64 bits
64 bits
56 bits
Idle
Start
Middle
7-byte
ending
Idle
Remark TXFBA[N]: N = 0 to 7
23
Data Sheet S14150EJ4V0DS
µPD98431
FIFO Bus Interface Read Timing
Parameter
RXFA output delay time
RXFA float time
Symbol
tDFKFA
tFFKFA
tDFKDQ
tFFKDQ
tDFKRP
tFFKRP
tDFKFD
tFFKFD
tSFKPS
tHFKPS
tSFKSP
tHFKSP
Conditions
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
10
10
10
10
RXFDQ[3:0]/FDQ[3:0] output delay time
RXFDQ[3:0]/FDQ[3:0] float time
RXFPT[2:0] output delay time
RXFPT[2:0] float time
RXFD[31:0]/FD[63:0] output delay time
RXFD[31:0]/FD[63:0] float time
PASS setup time
5
0
6
0
PASS hold time
SKIP setup time
SKIP hold time
(1) FIFO bus interface read timing (32-bit dual bus mode) 1
FCLK
t
SFKRE
tHFKRE
RXFEN#
RXFA
t
t
t
t
t
DFKFA
DFKDQ
DFKDQ
DFKDQ
DFKDQ
t
DFKFA
t
FFKFA
Hi-Z
FFKDQ
Hi-Z
t
DFKDQ
t
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[31:0]
PASS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
FFKDQ
Hi-Z
FFKDQ
t
DFKDQ
t
Hi-Z
FFKDQ
t
DFKDQ
t
Hi-Z
t
t
DFKRP
DFKFD
t
FFKRP
Port number
Hi-Z
t
FFKFD
1st Dword
32 bits
2nd
Dword
3rd
n
−
2
n−
1
n
Dword
Dword
32 bits
Dword
32 bits
Dword
24 bits
Hi-Z
32 bits
32 bits
t
HFKPS
t
SFKPS
SKIP
L
Idle
Start
Middle
3-byte Idle
ending
24
Data Sheet S14150EJ4V0DS
µPD98431
(2) FIFO bus interface read timing (32-bit dual bus mode) 2
FCLK
RXFEN#
RXFA
Hi-Z
RXFDQ[3]
Hi-Z
RXFDQ[2]
Hi-Z
RXFDQ[1]
Hi-Z
RXFDQ[0]
Hi-Z
RXFPT[2:0]
RXFD[31:0]
PASS
Port number N
XX
XX
Port number N + 1
Hi-Z
Hi-Z
1st
Dword
1st
Dword
2nd
Dword
3rd
Dword
tHFKPS
SKIP
tSFKPS
Skip frame
Idle
Start
Middle
25
Data Sheet S14150EJ4V0DS
µPD98431
(3) FIFO bus interface read timing (32-bit dual bus mode) 3
FCLK
t
SFKRE
RXFEN#
RXFA
t
t
t
t
t
DFKFA
DFKDQ
DFKDQ
DFKDQ
DFKDQ
t
DFKFA
Hi-Z
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[31:0]
PASS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
DFKDQ
t
DFKDQ
t
DFKDQ
t
DFKRP
DFKFD
Port number
t
Length & Status
Dword
1st
Dword
2nd
Dword
3rd
Dword
t
HFKPS
t
SFKPS
SKIP
L
Idle
Length Start
Middle
&
Status
26
Data Sheet S14150EJ4V0DS
µPD98431
(4) FIFO bus interface read timing (32-bit dual bus mode) 4
FCLK
t
HFKRE
RXFEN#
RXFA
t
FFKFA
Hi-Z
tDFKDQ
t
FFKDQ
RXFDQ[3]
RXFDQ[2]
RXFDQ[1]
RXFDQ[0]
RXFPT[2:0]
RXFD[31:0]
PASS
Hi-Z
t
DFKDQ
DFKDQ
t
FFKDQ
Hi-Z
FFKDQ
t
t
Hi-Z
FFKDQ
t
DFKDQ
t
Hi-Z
tFFKRP
Port number
Hi-Z
tFFKFD
n
−
3 th
n
−
2 th
n−1 th
n th
Dword
Dword
Dword
Dword
Hi-Z
Length
&
Status
Dword
L
L
SKIP
Middle
3-byte Length Idle
ending
&
Status
27
Data Sheet S14150EJ4V0DS
µPD98431
(5) FIFO bus interface read timing (64-bit single bus mode) 1
FCLK
t
SFKRE
tHFKRE
FEN#
FRW
t
SFKTE
t
HFKTE
t
t
t
t
t
DFKFA
DFKDQ
DFKDQ
DFKDQ
DFKDQ
t
DFKFA
t
t
t
t
t
FFKFA
RXFA
Hi-Z
FFKDQ
Hi-Z
t
t
DFKDQ
DFKDQ
FDQ[3]
FDQ[2]
FDQ[1]
FDQ[0]
RXFPT[2:0]
FD[63:0]
PASS
Hi-Z
FFKDQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FFKDQ
t
DFKDQ
Hi-Z
FFKDQ
t
DFKDQ
Hi-Z
t
t
DFKRP
DFKFD
t
FFKRP
Port number
Hi-Z
t
FFKFD
1st Dword
64 bits
2nd
64 bits
3rd
64 bits
n
−
2 th
n−
1 th
n th
56 bits
64 bits
64 bits
Hi-Z
t
HFKPS
t
SFKPS
SKIP
L
Idle
Start
Middle
7-byte Idle
ending
28
Data Sheet S14150EJ4V0DS
µPD98431
(6) FIFO bus interface read timing (64-bit single bus mode) 2
FCLK
FEN#
FRW
RXFA
Hi-Z
FDQ[3]
Hi-Z
FDQ[2]
Hi-Z
FDQ[1]
Hi-Z
FDQ[0]
Hi-Z
RXFPT[2:0]
FD[63:0]
PASS
Port number N
XX
XX
Port number N + 1
Hi-Z
Hi-Z
1st
64 bits
1st
64 bits
2nd
64 bits
3rd
64 bits
tHFKPS
SKIP
tSFKPS
Skip frame
Idle
Start
Middle
29
Data Sheet S14150EJ4V0DS
µPD98431
(7) FIFO bus interface read timing (64-bit single bus mode) 3
FCLK
t
SFKRE
FEN#
FRW
t
SFKTE
t
t
t
t
t
DFKFA
DFKDQ
DFKDQ
DFKDQ
DFKDQ
t
DFKFA
RXFA
Hi-Z
FDQ[3]
FDQ[2]
FDQ[1]
FDQ[0]
RXFPT[2:0]
FD[63:0]
PASS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
DFKDQ
t
DFKDQ
t
DFKDQ
t
DFKRP
DFKFD
Port number
t
Length & Status Dword
32 bits
1st
64 bits
2nd
64 bits
3rd
64 bits
t
HFKPS
t
SFKPS
SKIP
L
Idle
Length Start
Middle
&
Status
30
Data Sheet S14150EJ4V0DS
µPD98431
(8) FIFO bus interface read timing (64-bit single bus mode) 4
FCLK
t
HFKRE
FEN#
FRW
tHFKTE
tFFKFA
RXFA
Hi-Z
tDFKDQ
t
FFKDQ
FDQ[3]
FDQ[2]
FDQ[1]
FDQ[0]
RXFPT[2:0]
FD[63:0]
PASS
Hi-Z
t
DFKDQ
DFKDQ
t
FFKDQ
Hi-Z
FFKDQ
t
t
Hi-Z
FFKDQ
t
DFKDQ
t
Hi-Z
tFFKRP
Port number
Hi-Z
tFFKFD
n
−
3 th
n
−
2 th
n−1 th
n th
24 bits
64 bits
64 bits
64 bits
Hi-Z
Length
&
Status
32 bits
L
L
SKIP
Middle
3-byte Length Idle
ending
&
Status
31
Data Sheet S14150EJ4V0DS
µPD98431
Boundary Scan (JTAG) Timing
Parameter
TCK clock width
Symbol
tCYJK
tJKL
Conditions
MIN.
100
50
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TCK low-level width
TCK high-level width
TDI setup time
tJKH
50
tSJKI
5
TDI hold time
tHJKI
10
TDO output delay time
TMS setup time
tDJKO
tSJKM
tHJKM
15
5
5
TMS hold time
tCYJK
tJKL
tJKH
TCK
t
HJKI
t
SJKI
TDI
TDO
TMS
t
DJKO
t
HJKM
t
SJKM
32
Data Sheet S14150EJ4V0DS
µPD98431
3. PACKAGE DRAWING
352-PIN PLASTIC BGA (35x35)
A
B
A
B
S
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
C
D
8
7
6
5
4
3
2
1
AE AC AA W
AF AD AB Y
U
R
N
L
J G E C A
P
Index mark
R
V
T P M K H F D B
J
I
H
S
K
S
G
F
E
φ
M
M
N
S
S
A B
L
φ
M
ITEM MILLIMETERS
35.00 0.20
32.0
A
B
C
D
E
F
G
H
I
32.0
35.00 0.20
1.62
1.27 (T.P.)
0.6 0.1
0.56
1.73 0.15
2.33 0.25
0.15
J
K
L
φ
0.75 0.15
M
N
P
R
S
0.30
0.10
C4.0
25°
1.5
Y352S1-127-F6-4
33
Data Sheet S14150EJ4V0DS
µPD98431
4. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, contact your NEC sales representative.
Surface mounting type
µPD98431S1-F6: 352-pin plastic BGA (35 × 35)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or
higher), Count: Three times or less, Exposure limit: 3 daysNote (after that,
prebake at 125°C for 20 hours)
IR30-203-3
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
34
Data Sheet S14150EJ4V0DS
µPD98431
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Ethernet is a trademark of Xerox Corporation.
35
Data Sheet S14150EJ4V0DS
µPD98431
•
The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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