X9520V20IZ-B [RENESAS]
SPECIALTY TELECOM CIRCUIT, PDSO20, LEAD FREE, PLASTIC, TSSOP-20;
| 型号： | X9520V20IZ-B |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY TELECOM CIRCUIT, PDSO20, LEAD FREE, PLASTIC, TSSOP-20 光电二极管 转换器 |
| 文件： | 总29页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9520
®
igabit Ethernet Laser Diode Control for Fiber Optic Modules
ta Sheet
August 20, 2007
FN8206.2
Triple DCP, POR, 2kbit EEPROM Memory,
Dual Voltage Monitors
Features
• Three Digitally Controlled Potentiometers (DCPs)
- 64 Tap - 10kΩ
The X9520 combines three Digitally Controlled
- 100 Tap - 10kΩ
- 256 Tap - 100kΩ
- Nonvolatile
Potentiometers (DCPs), V1/VCC Power-on Reset (POR)
circuitry, two programmable voltage monitor inputs with
software and hardware indicators, and integrated EEPROM
with Block Lock™ protection. All functions of the X9520 are
accessed by an industry standard 2-Wire serial interface.
- Write Protect Function
™
• 2kbit EEPROM Memory with Write Protect & Block Lock
• 2-Wire Industry Standard Serial Interface
Two of the DCPs of the X9520 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber Optic
module. The third DCP may be used to set other various
reference quantities, or as a coarse trim for one of the other two
DCPs. The 2kbit integrated EEPROM may be used to store
module definition data. The programmable POR circuit may be
used to ensure that V1/VCC is stable before power is applied to
the laser diode/module. The programmable voltage monitors
may be used for monitoring various module alarm levels.
- Complies to the Gigabit Interface Converter (GBIC)
specification
• Power-on Reset (POR) Circuitry
- Programmable Threshold Voltage
- Software Selectable Reset Timeout
- Manual Reset
• Two Supplementary Voltage Monitors
- Programmable Threshold Voltages
The features of the X9520 are ideally suited to simplifying the
design of fiber optic modules which comply to the Gigabit
Interface Converter (GBIC) specification. The integration of
these functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
• Single Supply Operation
- 2.7V to 5.5V
• Hot Pluggable
• 20 Ld Package
- TSSOP
• Pb-free available (RoHS compliant)
Ordering Information
PART
MARKING
PRESET (FACTORY SHIPPED) TRIPx
TEMP. RANGE
(°C)
PKG.
PART NUMBER
X9520V20I-A
THRESHOLD LEVELS (x = 2, 3)
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 5V system monitoring**
Optimized for 5V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 3.3V system monitoring**
Optimized for 5V system monitoring**
Optimized for 5V system monitoring**
PACKAGE
20 Ld TSSOP
DWG. #
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
X9520V IA
X9520V IA
X9520V IA
X9520V IB
X9520V IB
X9520V ZIA
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
X9520V20I-AT1*
X9520V20I-AT2*
X9520V20I-B
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
20 Ld TSSOP
X9520V20I-BT1*
X9520V20IZ-A (Note)
20 Ld TSSOP (Pb-free) MDP0044
20 Ld TSSOP (Pb-free) MDP0044
20 Ld TSSOP (Pb-free) MDP0044
20 Ld TSSOP (Pb-free) MDP0044
20 Ld TSSOP (Pb-free) MDP0044
X9520V20IZ-AT1* (Note) X9520V ZIA
X9520V20IZ-AT2* (Note) X9520V ZIA
X9520V20IZ-B (Note)
X9520V ZIB
X9520V20IZ-BT1* (Note) X9520V ZIB
* Please refer to TB347 for details on reel specifications.
** For details, see DC Operating characteristics
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9520
Block Diagram
R
R
R
H0
W0
L0
WIPER
COUNTER
REGISTER
8
6 - BIT
NONVOLATILE
MEMORY
WP
PROTECT LOGIC
R
R
R
H1
W1
L1
WIPER
COUNTER
REGISTER
CONSTAT
REGISTER
DATA
REGISTER
4
SDA
SCL
7 - BIT
NONVOLATILE
MEMORY
COMMAND
DECODE &
CONTROL
LOGIC
2kbit
EEPROM
ARRAY
R
R
R
H2
W2
L2
WIPER
COUNTER
REGISTER
THRESHOLD
RESET LOGIC
MR
V3
2
8 - BIT
NONVOLATILE
MEMORY
V3RO
V2RO
V1RO
-
+
VTRIP3
VTRIP2
VTRIP1
V2
-
+
POWER-ON /
LOW VOLTAGE
RESET
V1/VCC
+
-
GENERATION
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware output
(V3RO, V2RO) are allowed to go HIGH. If the input voltage
becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding binary
representation of the two monitor circuit outputs (V2RO and
V3RO) are also stored in latched, volatile (CONSTAT)
register bits. The status of these two monitor outputs can be
read out via the 2-wire serial port.
Detailed Device Description
The X9520 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, V1/VCC power-on reset
control, V1/VCC low voltage reset control, two
supplementary voltage monitors, and integrated EEPROM
with Block Lock™ protection, in one package. These
functions are suited to the control, support, and monitoring of
various system parameters in Fiber Channel/Gigabit
Ethernet fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reliability,
and reduces board space requirements using Intersil’s
unique XBGA™ packaging.
An application of the V1RO output may be to drive the
“ENABLE” input of a Laser Driver IC, with MR as a
“TX_DISABLE” input. V2RO and V3RO may be used to
monitor “TX_FAULT” and “RX_LOS” conditions respectively.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolution
DCP may be used for setting sundry system parameters
such as maximum laser output power (for eye safety
requirements).
Intersil’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This gives
the designer great flexibility in changing system parameters,
either at the time of manufacture, or in the field.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s Block Lock™ protection. This
memory may be used to store fiber optic module
manufacturing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized as x
8, and utilizes Intersil’s proprietary Direct Write™ cells,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
Applying voltage to V
activates the Power-on Reset circuit
CC
which allows the V1RO output to go HIGH, until the supply
the supply voltage stabilizes for a period of time (selectable
via software). The V1RO output then goes LOW. The Low
Voltage Reset circuitry allows the V1RO output to go HIGH
when V
falls below the minimum V
trip point. V1RO
returns to proper operating level. A
CC
remains HIGH until V
CC
CC
Manual Reset (MR) input allows the user to externally trigger
the V1RO output (HIGH).
The device features a 2-Wire interface and software protocol
allowing operation on an I C™ compatible serial bus.
2
FN8206.2
August 20, 2007
2
X9520
Pinout
X9520
(20 LD TSSOP)
TOP VIEW
V1/VCC
V1RO
R
H2
20
19
18
17
1
2
3
R
W2
R
V2RO
V2
L2
V3
4
5
6
V3RO
MR
R
R
16
15
14
13
12
11
L0
W0
WP
SCL
SDA
7
8
R
R
H0
H1
9
R
R
W1
V
SS
10
L1
NOT TO SCALE
Pin Descriptions
TSSOP NAME
FUNCTION
1
2
3
4
R
R
Connection to end of resistor array for (the 256 Tap) DCP 2.
H2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
w2
R
L2
V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the
V
threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to V when not used.
SS
TRIP3
5
6
V3RO V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V
and goes LOW
TRIP3
when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up”
resistor.
MR
WP
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin
(V1/VCC RESET Output pin). V1RO will remain HIGH for time t
after MR has returned to it’s normally LOW state. The
purst
reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
7
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock
feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed
in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin
uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
8
9
SCL
SDA
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input
buffer is always active (not gated). This pin requires an external pull up resistor.
10
11
12
13
14
15
16
17
Vss
Ground.
R
Connection to other end of resistor for (the 100 Tap) DCP 1.
L1
w1
H1
H0
W0
R
R
R
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the
R
R
L0
V2
V
threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to V when not used.
SS
TRIP2
18
V2RO V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than V
, and goes LOW
TRIP2
when V2 is less than V
. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an
TRIP2
external “pull-up” resistor.
FN8206.2
August 20, 2007
3
X9520
Pin Descriptions (Continued)
TSSOP NAME
FUNCTION
19
V1RO V1/VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever V1/VCC falls below
. V1RO becomes active on power-up and remains active for a time t after the power supply stabilizes (t
V
can
purst
TRIP1
purst
be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external
“pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin.
20
V1/VCC Supply Voltage.
START condition and does not respond to any command
until this condition has been met. See Figure 2.
Principles of Operation
Serial Interface
SERIAL STOP CONDITION
SERIAL INTERFACE CONVENTIONS
All communications must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
The STOP condition is also used to place the device into the
Standby power mode after a read sequence. A STOP
condition can only be issued after the transmitting device has
released the bus. See Figure 2.
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the X9520 operates as a slave in all applications.
SERIAL CLOCK AND DATA
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure 1.
On power-up of the X9520, the SDA pin is in the input mode.
SERIAL START CONDITION
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 1. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 2. VALID START AND STOP CONDITIONS
FN8206.2
August 20, 2007
4
X9520
SCL from
SCL
Master
1
8
9
Data Output from
Transmitter
Data Output from
Receiver
START
ACKNOWLEDGE
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SERIAL ACKNOWLEDGE
Device Internal Addressing
An ACKNOWLEDGE (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to ACKNOWLEDGE that it received the eight
bits of data. Refer to Figure 3.
Addressing Protocol Overview
The user addressable internal components of the X9520 can
be split up into three main parts:
• Three Digitally Controlled Potentiometers (DCPs)
• EEPROM array
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent eight
bit word.
• Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being issued on the SDA pin. The Slave address selects the
part of the X9520 to be addressed, and specifies if a Read or
Write operation is to be performed.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected and
no STOP condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an ACKNOWLEDGE is not
detected. The master must then issue a STOP condition to
place the device into a known state.
It should be noted that in order to perform a write operation
to either a DCP or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock
protection bits - (Nonvolatile)” on page 13.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4). This byte consists of
three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The
Device Type Identifier must always be set to 1010 in order
to select the X9520.
• The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111 selects
the DCP structures in the X9520. The CONSTAT Register
may be selected using the Internal Device Address 010.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA3 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 4.)
FN8206.2
August 20, 2007
5
X9520
Byte load completed
by issuing STOP.
Enter ACK Polling
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
R/W
1 0 1 0
Issue START
READ/
WRITE
INTERNAL
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
Issue Slave Address
Byte (Read or Write)
Issue STOP
INTERNAL ADDRESS INTERNALLY ADDRESSED
(SA3 - SA1)
DEVICE
EEPROM Array
CONSTAT Register
DCP
000
NO
ACK
010
returned?
111
YES
BIT SA0
OPERATION
WRITE
NO
High Voltage Cycle
complete. Continue
command sequence?
0
1
Issue STOP
READ
FIGURE 4. SLAVE ADDRESS FORMAT
YES
Continue normal
Read or Write
command sequence
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the
EEPROM array, the Non Volatile Memory of a DCP (NVM),
or the CONSTAT Register) has been correctly issued
(including the final STOP condition), the X9520 initiates an
internal high voltage write cycle. This cycle typically requires
5 ms. During this time, no further Read or Write commands
can be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
PROCEED
FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
To perform acknowledge polling, the master issues a START
condition followed by a Slave Address Byte. The Slave
Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set to
either 1 or 0 in this case. If the device is still busy with the
high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation, an
ACKNOWLEDGE will be returned and the host can then
proceed with a read or write operation (Refer to Figure 5.).
R
N
Hx
WIPER
COUNTER
REGISTER
(WCR)
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
2
1
0
Digitally Controlled Potentiometers
NON
VOLATILE
MEMORY
DCP Functionality
(NVM)
The X9520 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R and R
R
R
Lx
Wx
FIGURE 6. DCP INTERNAL STRUCTURE
Hx
Lx
inputs - where x = 0,1,2).
FN8206.2
August 20, 2007
6
X9520
V1/VCC
V1/VCC (Max)
V
TRIP1
t
trans
t
purst
t
0
MAXIMUM WIPER RECALL TIME
FIGURE 7. DCP POWER
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
t
. It should be noted that t
is determined by
purst
trans
system hot plug conditions.
(R ) output. Within each individual array, only one switch
x
w
DCP Operations
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See Figure
6). The WCR is a volatile register.
In total there are three operations that can be performed on
any internal DCP structure:
• DCP Nonvolatile Write
• DCP Volatile Write
• DCP Read
On power-up of the X9520, wiper position data is
automatically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The table below shows the
Initial Values of the DCP WCR’s before the contents of the
NVM is loaded into the WCR.
A nonvolatile write to a DCP will change the “wiper position”
by simultaneously writing new data to the associated WCR
and NVM. Therefore, the new “wiper position” setting is
recalled into the WCR after V1/VCC of the X9520 is powered
down and then powered back up.
DCP
INITIAL VALUES BEFORE RECALL
R 64 TAP
V TAP = 63
0/
H/
R 100 TAP
V TAP = 0
1/
R 256 TAP
L/
TAP = 255
H/
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated WCR
only. The contents of the associated NVM register remains
unchanged. Therefore, when V1/VCC to the device is
powered down then back up, the “wiper position” reverts to
that last position written to the DCP using a nonvolatile write
operation.
V
2/
The data in the WCR is then decoded to select and enable
one of the respective FET switches. A “make before break”
sequence is used internally for the FET switches when the
wiper is moved from one tap position to another.
Hot Pluggability
Both volatile and nonvolatile write operations are executed
using a three byte command sequence: (DCP) Slave
Address Byte, Instruction Byte, followed by a Data Byte (See
Figure 9).
Figure 7 shows a typical waveform that the X9520 might
experience in a Hot Pluggable situation. On power-up,
V1/VCC applied to the X9520 may exhibit some amount of
ringing, before it settles to the required value.
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting of
the (DCP) Slave Address Byte followed by an Instruction
Byte and the Slave Address Byte again (Refer to Figure 10.).
The device is designed such that the wiper terminal (R ) is
Wx
recalled to the correct position (as per the last stored in the
DCP NVM), when the voltage applied to V1/VCC exceeds
V
for a time exceeding t
(the Power-on Reset
purst
TRIP1
time, set in the CONSTAT Register - See “Control and Status
Register” on page 12.).
Instruction Byte
Therefore, if t
is defined as the time taken for V1/VCC
trans
to settle above V
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which DCP
is being addressed.
(Figure 7): then the desired wiper
TRIP1
terminal position is recalled by (a maximum) time: t
+
trans
FN8206.2
August 20, 2007
7
X9520
DCP Write Operation
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
A write to DCPx (x = 0,1,2) can be performed using the three
byte command sequence shown in Figure 9.
WT
In order to perform a write operation on a particular DCP, the
Write Enable Latch (WEL) bit of the CONSTAT Register
must first be set (See “BL1, BL0: Block Lock protection bits -
(Nonvolatile)” on page 13.)
WRITE TYPE
DCP SELECT
†
WT
DESCRIPTION
The Slave Address Byte 10101110 specifies that a Write to a
DCP is to be conducted. An ACKNOWLEDGE is returned by
the X9520 after the Slave Address, if it has been received
correctly.
0
Select a Volatile Write operation to be performed on the
DCP pointed to by bits P1 and P0
1
Select a Nonvolatile Write operation to be performed on
the DCP pointed to by bits P1 and P0
Next, an Instruction Byte is issued on SDA. Bits P1 and P0
of the Instruction Byte determine which WCR is to be written,
while the WT bit determines if the Write is to be volatile or
nonvolatile. If the Instruction Byte format is valid, another
ACKNOWLEDGE is then returned by the X9520.
†
This bit has no effect when a Read operation is being performed.
FIGURE 8. INSTRUCTION BYTE FORMAT
Following the Instruction Byte, a Data Byte is issued to the
X9520 over SDA. The Data Byte contents is latched into the
WCR of the DCP on the first rising edge of the clock signal,
after the LSB of the Data Byte (D0) has been issued on SDA
(See Figure 34).
The Instruction Byte (Figure 8) is valid only when the Device
Type Identifier and the Internal Device Address bits of the
Slave Address are set to 1010111. In this case, the two
Least Significant Bit’s (I1 - I0) of the Instruction Byte are
used to select the particular DCP (0 - 2). In the case of a
Write to any of the DCPs (i.e. the LSB of the Slave Address
is 0), the Most Significant Bit of the Instruction Byte (I7),
determines the Write Type (WT) performed.
The Data Byte determines the “wiper position” (which FET
switch of the DCP resistive array is switched ON) of the
DCP. The maximum value for the Data Byte depends upon
which DCP is being addressed (see Table below).
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR and
NVM. Therefore, the new “wiper position” setting is recalled
into the WCR after V1/VCC of the X9520 has been powered
down then powered back up
P1 - P0
DCPX
x = 0
x = 1
x = 2
# TAPS
64
MAX DATA BYTE
0
0
1
1
0
1
0
1
3Fh
Refer to Appendix 1
FFh
100
256
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing new
data to the associated WCR only. The contents of the
associated NVM register remains unchanged. Therefore,
when V1/VCC to the device is powered down then back up,
the “wiper position” reverts to that last written to the DCP
using a nonvolatile write operation.
Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP “wiper
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
FIGURE 9. DCP WRITE COMMAND SEQUENCE
FN8206.2
August 20, 2007
8
X9520
terminal”. Therefore, the Data Byte 00001111 (15
corresponds to setting the “wiper terminal” to tap position 15.
Similarly, the Data Byte 00011100 (28 ) corresponds to
10
)
DCP Read Operation
10
A read of DCPx (x = 0,1,2) can be performed using the three
byte random read command sequence shown in Figure 10.
setting the “wiper terminal” to tap position 28. The mapping
of the Data Byte to “wiper position” data for DCP1 (100 Tap),
is shown in “Appendix 1” . An example of a simple C
language function which “translates” between the tap
position (decimal) and the Data Byte (binary) for DCP1, is
given in “Appendix 2” .
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation sets
which DCP is to be read (in the preceding Read operation).
An ACKNOWLEDGE is returned by the X9520 after the
Slave Address if received correctly. Next, an Instruction Byte
is issued on SDA. Bits P1-P0 of the Instruction Byte
determine which DCP “wiper position” is to be read. In this
case, the state of the WT bit is “don’t care”. If the Instruction
Byte format is valid, then another ACKNOWLEDGE is
returned by the X9520.
It should be noted that all writes to any DCP of the X9520
are random in nature. Therefore, the Data Byte of
consecutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits P1 = 1, P0 = 1
is a reserved sequence, and will result in no
ACKNOWLEDGE after sending an Instruction Byte on SDA.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave address
byte with the R/W bit set to 1. Then the X9520 issues an
ACKNOWLEDGE followed by Data Byte, and finally, the
master issues a STOP condition. The Data Byte read in this
operation, corresponds to the “wiper position” (value of the
WCR) of the DCP pointed to by bits P1 and P0.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corresponds
to having the “wiper teminal” R
(x = 0,1,2) at the “lowest”
WX
tap position, Therefore, the resistance between R
and
WX
is a minimum (essentially only the Wiper Resistance,
R
LX
R ).
W
WRITE Operation
Instruction
READ Operation
S
S
t
S
t
Signals from the
Master
a
r
Slave
Address
Slave
Address
t
Byte
a
r
o
p
t
Data Byte
t
SDA Bus
P
0
P
1
W
T
1 0 1 0 1 1 1 0
0 0 0 0 0
1 0 1 0 1 1 1 1
A
C
K
A
C
K
A
C
K
Signals from the
Slave
DCPx
x = 0
- -
-
x = 1
x = 2
“Dummy” write
LSB
MSB
“-” = DON’T CARE
FIGURE 10. DCP READ SEQUENCE
S
t
a
r
WRITE Operation
S
t
o
p
Signals from the
Master
Address
Byte
Slave
Address
Data
Byte
t
SDA Bus
1 0 1 0 0 0 0 0
A
C
K
A
C
K
A
C
K
Signals from the
Slave
Internal
Device
Address
FIGURE 11. EEPROM BYTE WRITE SEQUENCE
FN8206.2
August 20, 2007
9
X9520
S
t
a
r
S
t
o
p
(2 < n < 16)
Signals from the
Master
Address
Byte
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
1 0 1 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from the
Slave
FIGURE 12. EEPROM PAGE WRITE OPERATION
It should be noted that when reading out the data byte for
DCP0 (64 Tap), the upper two most significant bits are
“unknown” bits. For DCP1 (100 Tap), the upper most
significant bit is an “unknown”. For DCP2 (256 Tap) however,
all bits of the data byte are relevant (See Figure 10).
EEPROM Page Write
In order to perform an EEPROM Page Write operation to the
EEPROM array, the Write Enable Latch (WEL) bit of the
CONSTAT Register must first be set (See “BL1, BL0: Block
Lock protection bits - (Nonvolatile)” on page 13.)
2KBIT EEPROM ARRAY
The X9520 is capable of a page write operation. It is initiated
in the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit an unlimited number of
8-bit bytes. After the receipt of each byte, the X9520
responds with an ACKNOWLEDGE, and the address is
internally incremented by one. The page address remains
constant. When the counter reaches the end of the page, it
“rolls over” and goes back to ‘0’ on the same page.
Operations on the 2kbit EEPROM Array, consist of either 1,
2 or 3 byte command sequences. All operations on the
EEPROM must begin with the Device Type Identifier of the
Slave Address set to 1010000. A Read or Write to the
EEPROM is selected by setting the LSB of the Slave
Address to the appropriate value R/W (Read = “1”,
Write = ”0”).
In some cases when performing a Read or Write to the
EEPROM, an Address Byte may also need to be specified.
This Address Byte can contain the values 00h to FFh.
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6. Afterwards, the address counter
would point to location 7. If the master supplies more than 16
bytes of data, then new data overwrites the previous data,
one byte at a time (See Figure 13).
EEPROM BYTE WRITE
In order to perform an EEPROM Byte Write operation to the
EEPROM array, the Write Enable Latch (WEL) bit of the
CONSTAT Register must first be set (See “BL1, BL0: Block
Lock protection bits - (Nonvolatile)” on page 13.)
The master terminates the Data Byte loading by issuing a
STOP condition, which causes the X9520 to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 12 for the address, ACKNOWLEDGE, and
data transfer sequence.
For a write operation, the X9520 requires the Slave Address
Byte and an Address Byte. This gives the master access to
any one of the words in the array. After receipt of the
Address Byte, the X9520 responds with an
ACKNOWLEDGE, and awaits the next eight bits of data.
After receiving the 8 bits of the Data Byte, it again responds
with an ACKNOWLEDGE. The master then terminates the
transfer by generating a STOP condition, at which time the
X9520 begins the internal write cycle to the nonvolatile
memory (See Figure 11). During this internal write cycle, the
X9520 inputs are disabled, so it does not respond to any
requests from the master. The SDA output is at high
impedance. A write to a region of EEPROM memory which
has been protected with the Block-Lock feature (See “BL1,
BL0: Block Lock protection bits - (Nonvolatile)” on page 13.),
suppresses the ACKNOWLEDGE bit after the Address Byte.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and
receiving the subsequent ACKNOWLEDGE signal. If the
master issues a STOP within a Data Byte, or before the
X9520 issues a corresponding ACKNOWLEDGE, the X9520
cancels the write operation. Therefore, the contents of the
EEPROM array does not change.
FN8206.2
August 20, 2007
10
X9520
5 BYTES
7 BYTES
ADDRESS = 15
10
ADDRESS = 6
10
ADDRESS = 11
10
ADDRESS POINTER
ENDS HERE
ADDRESS = 7
10
FIGURE 13. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
S
T
S
SIGNALS FROM
THE MASTER
A
R
T
T
O
P
SLAVE
ADDRESS
SDA BUS
1
0 1 0 0 0 0
1
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 14. CURRENT EEPROM ADDRESS READ SEQUENCE
Another important point to note regarding the “Current
EEPROM Array Read Operations
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using the
Device Type Identifier 1010111 or 1010010). Immediately
after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential EEPROM
Read” is once again available (assuming that no access to a
DCP or CONSTAT Register occur in the interim).
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the START condition and the Slave Address Byte, receives
an ACKNOWLEDGE, then issues an Address Byte. This
“dummy” Write operation sets the address pointer to the
address from which to begin the random EEPROM read
operation.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an ACKNOWLEDGE and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an ACKNOWLEDGE during the ninth clock and then issues
a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a STOP condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a STOP condition.
After the X9520 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9520 and then by the eight bit word. The master terminates
FN8206.2
August 20, 2007
11
X9520
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from the
Master
a
r
Slave
Address
Address
Byte
Slave
Address
a
r
t
t
SDA Bus
1 0 1 0 0 0 0
1 0 1 0 0 0 0
1
0
A
C
K
A
C
K
A
C
K
Signals from the
Slave
Data
“Dummy” Write
FIGURE 15. RANDOM EEPROM ADDRESS READ SEQUENCE
the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
the address space the counter “rolls over” to address 00h and
the device continues to output data for each
ACKNOWLEDGE received (Refer to Figure 16.).
A similar operation called “Set Current Address” also exists.
This operation is performed if a STOP is issued instead of
the second START shown in Figure 15. In this case, the
device sets the address pointer to that of the Address Byte,
and then goes into standby mode after the STOP bit. All bus
activity will be ignored until another START is detected.
Control and Status Register
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the status
of various parameters of the X9520 (See Figure 17).
The CONSTAT register is a combination of both volatile and
nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when V1/VCC is
powered down, then powered back up. The volatile bits
however, will always power-up to a known logic state “0”
(irrespective of their value at power-down).
Sequential EEPROM Read
Sequential reads can be initiated as either a current address
read or random address read. The first Data Byte is
transmitted as with the other modes; however, the master
now responds with an ACKNOWLEDGE, indicating it
requires additional data. The X9520 continues to output a
Data Byte for each ACKNOWLEDGE received. The master
terminates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition.
A detailed description of the function of each of the
CONSTAT register bits follows:
WEL: WRITE ENABLE LATCH (VOLATILE)
The WEL bit controls the Write Enable status of the entire
X9520 device. This bit must first be enabled before ANY
write operation (to DCPs, EEPROM memory array, or the
CONSTAT register). If the WEL bit is not first enabled, then
ANY proceeding (volatile or nonvolatile) write operation to
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address counter
for read operations increments through the entire memory
contents to be serially read during one operation. At the end of
S
Slave
Address
A
C
K
A
C
K
A
C
K
t
Signals from the
Master
o
p
SDA Bus
1
0
0 0
A
C
K
Signals from the
Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FIGURE 16. SEQUENTIAL EEPROM READ SEQUENCE
FN8206.2
August 20, 2007
12
X9520
BL1, BL0: BLOCK LOCK PROTECTION BITS -
(NONVOLATILE)
CS3
BL0
CS7 CS6
CS4
BL1
CS5
CS2 CS1 CS0
The Block Lock protection bits (BL1 and BL0) are used to:
POR1
NV
V2OS V3OS
RWEL
WEL
POR0
NV
• Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
NV
NV
• Inhibit a DCP write operation (changing the “wiper
position”)
BIT(S)
DESCRIPTION
The region of EEPROM memory which is protected/locked is
determined by the combination of the BL1 and BL0 bits
written to the CONSTAT register. It is possible to lock the
regions of EEPROM memory shown in the table below:
WEL
RWEL
Write Enable Latch bit
Register Write Enable Latch bit
V2 Output Status flag
V2OS
V3OS
V3 Output Status flag
PROTECTED ADDRESSES
(SIZE)
PARTITION OF
ARRAY LOCKED
BL1 BL0
BL1 - BL0
POR1 - POR0
Sets the Block Lock partition
Sets the Power-on Reset time
0
0
1
1
0
1
0
1
None (Default)
None (Default)
Upper 1/4
Upper 1/2
All
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
C0h - FFh (64 bytes)
80h - FFh (128 bytes)
00h - FFh (256 bytes)
FIGURE 17. CONSTAT REGISTER FORMAT
DCPs, EEPROM array, as well as the CONSTAT register, is
aborted and no ACKNOWLEDGE is issued after a Data
Byte.
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation is
aborted without changing any data in the array.
The WEL bit is a volatile latch that powers up in the disabled,
LOW (0) state. The WEL bit is enabled/set by writing
00000010 to the CONSTAT register. Once enabled, the WEL
bit remains set to “1” until either it is reset to “0” (by writing
00000000 to the CONSTAT register) or until the X9520
powers down, and then up again.
When the Block Lock bits of the CONSTAT register are set to
something other than BL1 = 0 and BL0 = 0, then the “wiper
position” of the DCPs cannot be changed - i.e. DCP write
operations cannot be conducted:
BL1
0
BL0
0
DCP WRITE OPERATION PERMISSABLE
Writes to the WEL bit do not cause an internal high voltage
write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed in
the CONSTAT Write command sequence (See Figure 18).
YES (Default)
0
1
NO
NO
NO
1
0
RWEL: REGISTER WRITE ENABLE LATCH (VOLATILE)
1
1
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9520. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL), the
RWEL bit must first be set to “1”. The RWEL bit is a volatile
bit that powers up in the disabled, LOW (“0”) state.
The factory default setting for these bits are BL1 = 0, BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write operations
to both the EEPROM memory and DCPs are inhibited,
irrespective of the Block Lock bit settings (See "WP: Write
Protection Pin").
It must be noted that the RWEL bit can only be set, once the
WEL bit has first been enabled (See "CONSTAT Register
Write Operation").
POR1, POR0: POWER-ON RESET BITS – (NONVOLATILE)
The RWEL bit will reset itself to the default “0” state, in one
of three cases:
Applying voltage to V
activates the Power-on Reset circuit
CC
which holds V1RO output HIGH, until the supply voltage
stabilizes above the V threshold for a period of time,
• After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure 18).
TRIP1
(See Figure 30).
t
PURST
The Power-on Reset bits, POR1 and POR0 of the CONSTAT
register determine the t delay time of the Power-on
• When the X9520 is powered down.
• When attempting to write to a Block Lock protected region
of the EEPROM memory (See "BL1, BL0: Block Lock
protection bits - (Nonvolatile)").
PURST
Reset circuitry (See "Voltage Monitoring Functions"). These
bits of the CONSTAT register are nonvolatile, and therefore
power-up to the last written state.
FN8206.2
August 20, 2007
13
X9520
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
FIGURE 18. CONSTAT REGISTER WRITE COMMAND SEQUENCE
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to the
CONSTAT register:
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps.
• Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so there
is no delay after the write. (Operation preceded by a
START and ended with a STOP).
POR1
POR0
POWER-ON RESET DELAY (T
)
PUV1RO
0
0
1
1
0
1
0
1
50ms
100ms (Default)
200ms
• Write a 06H to the CONSTAT Register to set the Register
Write Enable Latch (RWEL) AND the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required.
(Operation preceded by a START and ended with a STOP).
300ms
The default for these bits are POR1 = 0, POR0 = 1.
• Write a one byte value to the CONSTAT Register that has
all the bits set to the desired state. The CONSTAT register
can be represented as qxyst01r in binary, where xy are the
Voltage Monitor Output Status (V2OS and V3OS) bits, st
are the Block Lock Protection (BL1 and BL0) bits, and qr
V2OS, V3OS: VOLTAGE MONITOR STATUS BITS
(VOLATILE)
Bits V2OS and V3OS of the CONSTAT register are latched,
volatile flag bits which indicate the status of the Voltage
Monitor reset output pins V2RO and V3RO.
are the Power-on Reset delay time (t
) control bits
PUV1RO
(POR1 - POR0). This operation is proceeded by a START
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2 is set
to ‘1’ in this third step (qxys t11r) then the RWEL bit is set,
but the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits
remain unchanged. Writing a second byte to the control
register is not allowed. Doing so aborts the write operation
and the X9520 does not return an ACKNOWLEDGE.
At power-up the VxOS (x = 2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate value to
the CONSTAT register. To provide consistency between the
VxRO and VxOS however, the status of the VxOS bits can only
be set to a “1” when the corresponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be reset to
“0” if:
• The device is powered down, then back up
• The corresponding VxRO output becomes LOW
CONSTAT Register Write Operation
For example, a sequence of writes to the device CONSTAT
register consisting of [02H, 06H, 02H] will reset all of the
nonvolatile bits in the CONSTAT Register to “0”.
The CONSTAT register is accessed using the Slave Address
set to 1010010 (Refer to Figure 4.). Following the Slave
Address Byte, access to the CONSTAT register requires an
Address Byte which must be set to FFh. Only one data byte
is allowed to be written for each CONSTAT register Write
operation. The user must issue a STOP, after sending this
byte to the register, to initiate the nonvolatile cycle that
stores the BP1, BP0, POR1 and POR0 bits. The X9520 will
not ACKNOWLEDGE any data bytes written after the first
byte is entered (Refer to Figure 18.).
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin of
the X9520 is active (HIGH) (See "WP: Write Protection Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at any time
by performing a random read (See Figure 19). Using the Slave
Address Byte set to 10100101, and an Address Byte of FFh.
Only one byte is read by each register read operation. The
X9520 resets itself after the first byte is read. The master should
supply a STOP condition to be consistent with the bus protocol.
After setting the WEL and/or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write operation.
FN8206.2
August 20, 2007
14
X9520
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from the
Master
a
r
Slave
Address
a
r
Address
Byte
Slave
Address
t
t
CS7 … CS0
SDA Bus
1
0
10 1 0 0 1 0
1 0 1 0 0 1 0
A
C
K
A
C
K
A
C
K
Signals from the
Slave
Data
“Dummy” Write
FIGURE 19. CONSTAT REGISTER READ COMMAND SEQUENCE
Data Protection
V1/VCC
There are a number of levels of data protection features
designed into the X9520. Any write to the device first
requires setting of the WEL bit in the CONSTAT register. A
write to the CONSTAT register itself, further requires the
setting of the RWEL bit. Block Lock protection of the device
enables the user to inhibit writes to certain regions of the
EEPROM memory, as well as to all the DCPs. One further
level of data protection in the X9520, is incorporated in the
form of the Write Protection pin.
V
TRIP1
0 Volts
0 Volts
MR
V1RO
0 Volts
t
WP: Write Protection Pin
PURST
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9520.
FIGURE 20. MANUAL RESET RESPONSE
The table below (X9520 Write Permission Status)
summarizes the effect of the WP pin (and Block Lock), on
the write permission status of the device.
is that the value of t
the CONSTAT register (See “POR1, POR0: Power-on Reset
bits – (Nonvolatile)” on page 13.).
may be selected in software via
PURST
Additional Data Protection Features
It is recommended to stop communication to the device
while V1R0 is HIGH. Also, setting the Manual Reset (MR)
pin HIGH overrides the Power-on/Low Voltage circuitry and
forces the V1RO output pin HIGH (See "MR: Manual
Reset").
In addition to the preceding features, the X9520 also
incorporates the following data protection functionality:
• The proper clock count and data bit sequence is required
prior to the STOP bit in order to start a nonvolatile write
cycle.
MR: Manual Reset
The V1RO output can be forced HIGH externally using the
Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connecting a
push-button directly from V1/VCC to the MR pin.
Voltage Monitoring Functions
V1/VCC Monitoring
The X9520 monitors the supply voltage and drives the V1RO
output HIGH (using an external “pull up” resistor) if V1/VCC
V1RO remains HIGH for time t
after MR has returned
PURST
is lower than V
threshold. The V1RO output will remain
TRIP1
HIGH until V1/VCC exceeds V
to its LOW state (See Figure 20). An external “pull down”
resistor is required to hold this pin (normally) LOW.
for a minimum time of
TRIP1
t
. After this time, the V1RO pin is driven to a LOW
PURST
state. See Figure 30.
For the Power-on/Low Voltage Reset function of the X9520,
the V1RO output may be driven HIGH down to a V1/VCC of
1V (V
RVALID
). See Figure 30. Another feature of the X9520,
FN8206.2
August 20, 2007
15
X9520
X9520 Write Permission Status
BLOCK
LOCK BITS
WRITE TO CONSTAT REGISTER
PERMITTED
DCP VOLATILE WRITE
DCP NONVOLATILE
WRITE PERMITTED
WRITE TO EEPROM
PERMITTED
NONVOLATILE
BL0
x
BL1
1
WP
1
PERMITTED
VOLATILE BITS
BITS
NO
NO
NO
NO
NO
NO
YES
NO
NO
NO
NO
NO
1
x
1
NO
NO
0
0
1
YES
NO
NO
NO
x
1
0
NO
Not in locked region
Not in locked region
Yes (All Array)
YES
YES
YES
YES
YES
YES
1
x
0
NO
0
0
0
YES
precision/tolerance is required, the X9520 trip points may be
adjusted by the user, using the steps detailed below.
V
TRIPx
0V
Vx
Setting a V
TRIPx
Voltage (x = 1,2,3)
There are two procedures used to set the threshold voltages
(V ), depending if the threshold voltage to be stored is
TRIPx
higher or lower than the present value. For example, if the
present V is 2.9 V and the new V is 3.2 V, the
VxRO
0V
TRIPx TRIPx
new voltage can be stored directly into the V
cell. If
TRIPx
however, the new setting is to be lower than the present
V1/VCC
setting, then it is necessary to “reset” the V
before setting the new value.
voltage
TRIPx
V
TRIP1
0 Volts
(x = 2,3)
FIGURE 21. VOLTAGE MONITOR RESPONSE
Setting a Higher V
Voltage (x = 1,2,3)
threshold to a new voltage which is higher
TRIPx
To set a V
TRIPx
than the present threshold, the user must apply the desired
threshold voltage to the corresponding input pin
V
TRIPx
(V1/VCC, V2 or V3). Then, a programming voltage (Vp) must
be applied to the WP pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h,
V2 Monitoring
The X9520 asserts the V2RO output HIGH if the voltage V2
exceeds the corresponding V threshold (See Figure
21). The bit V2OS in the CONSTAT register is then set to a
“0” (assuming that it has been set to “1” after system
initilization).
followed by the Byte Address 01h for V
, 09h for
, and a 00h Data Byte in order to
TRIP2
TRIP1
V
, and 0Dh for V
TRIP3
TRIP2
program V
. The STOP bit following a valid write
TRIPx
operation initiates the programming sequence. Pin WP must
then be brought LOW to complete the operation (See Figure
23). The user does not have to set the WEL bit in the
CONSTAT register before performing this write sequence.
The V2RO output may remain active HIGH with V
1V.
down to
CC
V3 Monitoring
Setting a Lower V
Voltage (x = 1,2,3).
TRIPx
The X9520 asserts the V3RO output HIGH if the voltage V3
exceeds the corresponding V threshold (See Figure
21). The bit V3OS in the CONSTAT register is then set to a
“0” (assuming that it has been set to “1” after system
initilization).
In order to set V
to a lower voltage than the present
must first be “reset” according to the
TRIPx
TRIP3
value, then V
TRIPx
procedure described below. Once V
has been “reset”,
TRIPx
can be set to the desired voltage using the
then V
TRIPx
procedure described in “Setting a Higher V
Voltage”.
TRIPx
The V3RO output may remain active HIGH with V
1V.
down to
CC
Resetting the V
Voltage (x = 1,2,3).
voltage, apply the programming voltage
TRIPx
To reset a V
TRIPx
(Vp) to the WP pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h followed
V
Thresholds (x = 1,2,3)
TRIPx
The X9520 is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
by the Byte Address 03h for V
, 0Bh for V
, and
TRIPx
TRIP1
TRIP2
thresholds are different from the default values, or if a higher
0Fh for V
, followed by 00h for the Data Byte in order to
TRIP3
reset V
. The STOP bit following a valid write operation
TRIPx
FN8206.2
August 20, 2007
16
X9520
initiates the programming sequence. Pin WP must then be
brought LOW to complete the operation (See Figure 23).The
user does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
Once the desired V threshold has been set, the error
TRIPx
between the desired and (new) actual set threshold can be
determined. This is achieved by applying V1/VCC to the
device, and then applying a test voltage higher than the desired
threshold voltage, to the input pin of the voltage monitor circuit
After being reset, the value of V
value of 1.7V.
becomes a nominal
TRIPx
whose V
was programmed. For example, if V was
TRIPx
TRIP2
set to a desired level of 3.0 V, then a test voltage of 3.4 V may
be applied to the voltage monitor input pin V2. In the case of
V
Accuracy (x = 1,2,3).
TRIPx
The accuracy with which the V
setting of V
then only V1/VCC need be applied. In all
TRIP1
thresholds are set, can
TRIPx
cases, care should be taken not to exceed the maximum input
voltage limits.
be controlled using the iterative process shown in Figure 24.
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x = 1,2,3).").
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage monitor
circuit changes state. At this point, the error between the
actual/measured, and desired threshold levels is calculated.
The desired threshold voltage is then applied to the appropriate
input pin (V1/VCC, V2 or V3) and the procedure described in
Section “Setting a Higher V
Voltage“ must be followed.
TRIPx
For example, the desired threshold for V
TRIP2
is set to 3.0 V,
and a test voltage of 3.4 V was applied to the input pin V2 (after
V
V1/VCC
V2, V3
TRIPx
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
00h
†
†
†
01h sets V
TRIP1
A0h
Data Byte
†
S
T
A
R
T
09h sets V
TRIP2
†
†
0Dh sets V
All others Reserved.
TRIP3
FIGURE 22. SETTING V
TRIPX
TO A HIGHER LEVEL (X = 1,2,3).
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
†
00h
SDA
†
†
A0h
03h Resets VTRIP1
Data Byte
S
T
A
R
T
†
0Bh Resets VTRIP2
†
0Fh Resets VTRIP3
†
All others Reserved.
FIGURE 23. RESETTING THE V
TRIPx
LEVEL
FN8206.2
August 20, 2007
17
X9520
applying power to V1/VCC). The input voltage is decreased,
and found to trip the associated output level of pin V2RO from a
LOW to a HIGH, when V2 reaches 3.09 V. From this, it can be
calculated that the programming error is 3.09 - 3.0 = 0.09 V.
to the previously set V minus the calculated error. If it is
TRIPx
the case that the error is less than zero, then the V
must
TRIPx
be programmed to a value equal to the previously set V
plus the absolute value of the calculated error.
TRIPx
If the error between the desired and measured V
is
Continuing the previous example, we see that the calculated
error was 0.09V. Since this is greater than zero, we must first
TRIPx
less than the maximum desired error, then the programming
process may be terminated. If however, the error is greater
than the maximum desired error, then another iteration of the
“reset” the V
threshold, then apply a voltage equal to the
TRIP2
last previously programmed voltage, minus the last previously
calculated error. Therefore, we must apply V = 2.91 V to
V
programming sequence can be performed (using the
TRIPx
TRIP2
pin V2 and execute the programming sequence.
calculated error) in order to further increase the accuracy of
the threshold voltage.
Using this process, the desired accuracy for a particular
V threshold may be attained using a successive
If the calculated error is greater than zero, then the V
TRIPx
must first be “reset”, and then programmed to the a value equal
TRIPx
number of iterations.
Note: X = 1,2,3.
V
Programming
TRIPx
Let: MDE = Maximum Desired Error
+
NO
Desired V
<
MDE
TRIPx
present value?
Acceptable
Error Range
Desired Value
–
YES
MDE
Execute
Error = Actual - Desired
V
Reset
TRIPx
Sequence
Set Vx = desired V
TRIPx
Execute
New Vx applied =
Old Vx applied - | Error |
New Vx applied =
Old Vx applied + | Error |
Set Higher V
TRIPx
Sequence
Execute
Apply VCC & Voltage
> Desired V to Vx
Reset V
TRIPx
TRIPx
Sequence
Decrease Vx
Output
switches?
NO
YES
Actual V
TRIPx
= Error
–
+
TRIPx
Error < MDE
Error >MDE
- Desired V
| Error | < | MDE |
DONE
FIGURE 24. V
SETTING/RESET SEQUENCE (X = 1,2,3)
TRIPx
FN8206.2
August 20, 2007
18
X9520
Absolute Maximum Ratings
Thermal Information
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Voltage on WP pin (With respect to Vss). . . . . . . . . . . . -1.0 to +15V
Voltage on other pins (With respect to Vss). . . . . . . . . . . -1.0 to +7V
| Voltage on RHx– Voltage on RLx |
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(x = 0,1,2. Referenced to Vss) . . . . . . . . . . . . . . . . . . . . . V1/VCC
DC Output Current (SDA,V1RO,V2RO,V3RO) . . . . . . . . . . . . . 5mA
Supply Voltage Limits
Recommended Operating Conditions
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
(Applied V1/VCC voltage, referenced to Vss) . . . . . . . 2.7 to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications
SYMBOL
PARAMETER
Current into V Pin
TEST CONDITIONS/NOTES
f = 400kHz
SCL
MIN
TYP
MAX UNIT
(1)
I
I
I
mA
CC1
CC
(X9520: Active)
(3)
Read memory array
0.4
1.5
Write nonvolatile memory
(2)
Current into V
Pin
V = V
SDA CC
MR = Vss
WP = Vss or Open/Floating
μA
CC2
LI
CC
(X9520:Standby)
(3)
With 2-Wire bus activity
No 2-Wire bus activity
50
50
V
V
= V
SCL
(when no bus activity else f
= 400kHz)
SCL
CC
(4)
Input Leakage Current (SCL, SDA, MR)
Input Leakage Current (WP)
Analog Input Leakage
= GND to V
0.1
10
10
10
10
μA
μA
µA
μA
IN
CC.
I
I
V
V
= V to V
SS
with all other analog inputs floating
1
ai
IN
CC
= GND to V X9520 is in Standby
CC.
(5)
Output Leakage Current (SDA, V1RO,
V2RO, V3RO)
0.1
LO
OUT
(2)
V
V
V
V
V
Programming Range
2.75
1.8
4.70
4.70
V
V
V
TRIP1PR
TRIPxPR
TRIP1
TRIPx
Programming Range (x = 2,3)
(6)
Pre - programmed V
Pre - programmed V
Pre - programmed V
threshold
threshold
threshold
Factory shipped default option A
Factory shipped default option B
2.85
4.55
3.0
4.7
3.05
4.75
TRIP1
TRIP1
TRIP2
TRIP3
(6)
V
V
Factory shipped default option A
Factory shipped default option B
1.65
2.85
1.8
3.0
1.85
3.05
V
V
TRIP2
(6)
Factory shipped default option A
Factory shipped default option B
1.65
2.85
1.8
3.0
1.85
3.05
TRIP3
I
V2 Input leakage current
V3 Input leakage current
V
= V = V
SCL CC
1
1
μA
Vx
SDA
Others = GND or V
CC
(7)
(7)
V
V
V
Input LOW Voltage (SCL, SDA, WP, MR)
Input HIGH Voltage (SCL,SDA, WP, MR)
-0.5
2.0
0.8
V
V
V
IL
V
+0.5
IH
CC
V1RO, V2RO, V3RO, SDA Output Low
Voltage
I
= 2.0mA
SINK
0.4
OLx
NOTES:
1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address
Byte are incorrect; 200ns after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
2. The device goes into Standby: 200ns after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that initiates a high
WC
voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
3. Current through external pull up resistor not included.
4. V = Voltage applied to input pin.
IN
5. V
OUT
= Voltage applied to output pin.
6. See Ordering Information Table.
7. V Min. and V Max. are for reference only and are not tested.
IL IH
FN8206.2
August 20, 2007
19
X9520
AC Characteristics (See Figure 27, Figure 28, Figure 29)
400kHz
SYMBOL
PARAMETER
MIN
MAX
UNITS
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
0
50
400
SCL
(5)
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
IN
(5)
0.1
0.9
μs
AA
1.3
μs
BUF
1.3
μs
LOW
Clock HIGH Time
0.6
μs
HIGH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
μs
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
0.6
μs
100
0
ns
Data In Hold Time
μs
Stop Condition Setup Time
Data Output Hold Time
0.6
μs
(5)
50
ns
DH
(5)
R
(2)
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
20 +.1Cb
20 +.1Cb
0.6
300
300
ns
(5)
F
(2)
ns
μs
SU:WP
WP Hold Time
0
μs
HD:WP
(5)
Cb
Capacitive load for each bus line
400
pF
AC TEST CONDITIONS
Input Pulse Levels
0.1V
to 0.9V
CC
CC
10ns
0.5V
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
CC
See Figure 25
Nonvolatile Write Cycle Timing
SYMBOL
PARAMETER
Nonvolatile Write Cycle Time
MIN
TYP (Note 1)
MAX
UNITS
t
(Note 4)
5
10
ms
WC
Capacitance (T = +25°C, f = 1.0MHz, V = 5V)
A
CC
PARAMETER
(Note 5) Output Capacitance (SDA, V1RO, V2RO, V3RO)
SYMBOL
MAX
UNITS
pF
TEST CONDITIONS
= 0V
C
C
8
6
V
OUT
OUT
V = 0V
IN
(Note 5)
Input Capacitance (SCL, WP, MR)
pF
IN
NOTES:
1. Typical values are for T = 25°C and V
= 5.0V.
A
CC
2. Cb = total capacitance of one bus line in pF.
3. Over recommended operating conditions, unless otherwise specified.
4. t is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
WC
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
5. This parameter is not 100% tested.
FN8206.2
August 20, 2007
20
X9520
Potentiometer Characteristics
LIMITS
MAX
+20
SYMBOL
PARAMETER
End to End Resistance Tolerance
Terminal Voltage (x = 0,1,2)
TEST CONDITIONS/NOTES
MIN
-20
TYP
UNITS
%
R
TOL
RHx
RLx
R
V
V
P
R
Vss
Vss
V
V
V
H
CC
CC
R Terminal Voltage (x = 0,1,2)
L
V
(1) (6)
Power Rating
R
R
= 10kΩ (DCP0, DCP1)
= 100kΩ (DCP2)
10
5
mW
mW
Ω
TOTAL
TOTAL
R
DCP Wiper Resistance
I
= 1mA, V
= 5 V, V = VCC,
RHx
200
400
400
W
W
CC
= Vss (x = 0,1,2).
V
RLx
I
= 1mA, V
= 2.7 V, V = VCC,
RHx
1200
4.4
Ω
W
CC
= Vss (x = 0,1,2)
V
RLx
(6)
I
Wiper Current
mA
W
Noise
R
R
= 10kΩ (DCP0, DCP1)
= 100kΩ (DCP2)
mV/
√(Hz)
TOTAL
mV/
TOTAL
√(Hz)
(2)
(4)
MI
Absolute Linearity
R
R
R
R
- R
-1
-1
+1
+1
w(n)(actual)
w(n)(expected)
(3)
(4)
MI
Relative Linearity
- [R
]
w(n+1)
TOTAL
TOTAL
w(n)+MI
R
Temperature Coefficient
= 10kΩ (DCP0, DCP1)
= 100kΩ (DCP2)
±300
±300
ppm/°C
ppm/°C
pF
TOTAL
(6)
C /C /C
Potentiometer Capacitances
See Figure 26.
10/10/25
H
L
W
(6)
t
Wiper Response time
See Figure 34.
200
μs
wr
NOTES:
1. Power Rating between the wiper terminal R
and the end terminals R or R - for ANY tap position n, (x = 0,1,2).
WX(n)
HX
LX
2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R
Maximum (x = 0,1,2).
(actual) - R
(expected)) = ±1 Ml
wx(n)
wx(n)
3. Relative Linearity is a measure of the error in step size between taps = R
- [R
+ Ml] = ±1 Ml (x = 0,1,2)
Wx(n+1)
wx(n)
4. 1 Ml = Minimum Increment = R
/(Number of taps in DCP - 1).
TOT
5. Typical values are for T = 25°C and nominal supply voltage.
A
6. This parameter is periodically sampled and not 100% tested.
V
(x = 1,2,3) Programming Parameters (See Figure 33)
TRIPX
PARAMETER
DESCRIPTION
Program Enable Voltage Setup time
MIN
10
10
10
10
1
TYP
MAX
UNITS
μs
t
V
V
V
V
V
V
VPS
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
t
Program Enable Voltage Hold time
Setup time
μs
VPH
t
μs
TSU
THD
VPO
t
Hold (stable) time
μs
t
Program Enable Voltage Off time (Between successive adjustments)
Write Cycle time
ms
ms
V
t
5
10
15
wc
V
Programming Voltage
10
-100
-25
P
ta
tv
V
V
V
V
Program Voltage accuracy (Programmed at 25°C.)
+100
+25
mV
mV
TRIPx
Program variation after programming (-40 - 85°C). (Programmed at 25°C.)
+10
TRIP
NOTE: The above parameters are not 100% tested.
FN8206.2
August 20, 2007
21
X9520
V1RO, V2RO, V3RO Output Timing. (See Figure 30, Figure 31, Figure 32)
SYMBOL
DESCRIPTION
CONDITION
POR1 = 0, POR0 = 0
POR1 = 0, POR0 = 1
POR1 = 1, POR0 = 0
POR1 = 1, POR0 = 1
MIN
25
TYP
50
MAX
75
UNITS
ms
(5)
t
Power On Reset delay time
PURST
50
100
200
300
150
300
450
5
ms
100
150
ms
ms
(2)
(1) (2) (4)
See
t
(Figure 31)
(5)
MR to V1RO propagation delay
MR pulse width
μs
MRD
(5)
t
t
500
ns
MRDPW
(5)
V1/VCC, V2, V3 to V1RO, V2RO, V3RO
propagation delay (respectively)
20
μs
RPDx
(5)
Fx
t
t
V1/VCC, V2, V3 Fall Time
20
20
1
mV/μs
mV/μs
V
(5)
Rx
V1/VCC, V2, V3 Rise Time
(5)
V
V1/VCC for V1RO, V2RO, V3RO Valid
RVALID
(3)
.
NOTES:
1. See Figure 31 for timing diagram.
2. See Figure 25 for equivalent load.
3. This parameter describes the lowest possible V1/VCC level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to their
inputs (V1/VCC, V2, V3).
4. From MR rising edge crossing V , to V1RO rising edge crossing V
IH
.
OH
5. The above parameters are not 100% tested.
V1/VCC = 5V
R
TOTAL
R
R
Hx
Lx
2300Ω
C
L
C
H
10pF
R
W
C
SDA
V2RO
10pF
W
100pF
V3RO
V1RO
25pF
(x = 0,1,2)
FIGURE 25. EQUIVALENT AC CIRCUIT
R
Wx
FIGURE 26. DCP SPICE MACROMODEL
Timing Diagrams
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
FIGURE 27. BUS TIMING
FN8206.2
August 20, 2007
22
X9520
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
FIGURE 28. WP PIN TIMING
SCL
SDA
8th BIT OF LAST BYTE
ACK
t
WC
STOP
CONDITION
START
CONDITION
FIGURE 29. WRITE CYCLE TIMING
t
t
R
F
V1/VCC
V
TRIP1
0V
t
PURST
t
PURST
t
t
RPD
RPD
V1RO
MR
0V
0V
FIGURE 30. POWER-UP AND POWER-DOWN TIMING
FN8206.2
August 20, 2007
23
X9520
MR
t
MRPW
0V
0V
t
t
PURST
MRD
V1RO
V1/VCC
V1/VCC
V
TRIP1
FIGURE 31. MANUAL RESET TIMING DIAGRAM
t
t
Fx
Rx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0V
t
RPDx
VxRO
0V
V1/VCC
V
TRIP1
V
RVALID
0V
Note : x = 2,3.
FIGURE 32. V2, V3 TIMING DIAGRAM
FN8206.2
August 20, 2007
24
X9520
V1/VCC, V2, V3
V
TRIPx
t
t
TSU
THD
V
P
WP
t
VPS
t
VPO
SCL
SDA
t
wc
00h
t
VPH
NOTE : V1/VCC must be greater than V2, V3 when programming.
FIGURE 33. V
PROGRAMMING TIMING DIAGRAM (X = 1,2,3)
TRIPX
Rwx (x = 0,1,2)
R
wx(n+1)
R
wx(n)
R
wx(n-1)
t
wr
n = tap position
Time
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
FIGURE 34. DCP “WIPER POSITION” TIMING
FN8206.2
August 20, 2007
25
X9520
Appendix 1
DCP1 (100 Tap) Tap Position to Data Byte Translation Table
DATA BYTE
TAP
POSITION
DECIMAL
BINARY
0000 0000
0000 0001
0
1
0
1
.
.
.
.
.
.
23
24
25
26
23
24
56
55
0001 0111
0001 1000
0011 1000
0011 0111
.
.
.
.
.
.
48
49
50
51
33
32
64
65
0010 0001
0010 0000
0100 0000
0100 0001
.
.
.
.
.
.
73
74
75
76
87
88
0101 0111
0101 1000
0111 1000
0111 0111
120
119
.
.
.
.
.
.
98
99
97
96
0110 0001
0110 0000
FN8206.2
August 20, 2007
26
X9520
Appendix 2
DCP1 (100 Tap) Tap Position to Data Byte Translation Algorithm Example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
FN8206.2
August 20, 2007
27
X9520
Appendix 2
DCP1 (100 TAP) TAP POSITION TO DATA BYTE TRANSLATION ALGORITHM EXAMPLE. (EXAMPLE 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
FN8206.2
August 20, 2007
28
X9520
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
D
A
(N/2)+1
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
B
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
c
2X
1
(N/2)
N/2 LEAD TIPS
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
L
±0.15
e
C
L1
Reference
Rev. E 12/02
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8206.2
August 20, 2007
29
相关型号：
X9521B20I
DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PBGA20, XBGA-20
RENESAS
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