RT5112A [RICHTEK]
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| 型号： | RT5112A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 |
| 文件： | 总63页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT5112A
Smart Power-Management Integrated Circuit for Camera
Module Application
General Description
Features
The RT5112A device is a smart power management IC
which includes two low-quiescent-current HCOT Buck
converters and four high PSRR low dropout regulators
(LDO). One can control the channel power sequence,
output voltage level andDVS slew rate by setting registers
via I2C interface. The output voltage OVP/UVP, OCP and
OTP protection are built in the RT5112A. The RT5112Ais
available in a WL-CSP-25B 2.2x2.3 (BSC) package.
System Control
Hardware Enable Pin
I2C Controlled Interface
Programmable Channel Power Sequence
IRQ Output for Indication
Over-Voltage Protection
Under-Voltage Protection
Over-Current Protection
Over-Temperature Protection
Available in a WL-CSP-25B 2.2x2.3 (BSC) Package
Applications
Camera Module
Optical Module
SSD
Two High Efficiency Buck Converters
Wide 2.5V to 5.5V Operating Input Range
Programmable Output Voltage from 0.6V to 3.3V
by 12.5mV/Step
Ordering Information
RT5112A
Maximum Continuous Load Current : 1.2A
HCOT Control Operation
Low Quiescent Current
Package Type
WSC : WL-CSP-25B 2.2x2.3 (BSC)
Four Low Dropout Regulators
Note :
Wide 1.9V to 5.5V Operating Input Range
Programmable Output Voltage from 0.6V to 3.775V
by 25mV/Step
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
High PSRR : 70dB @ 1kHz, 40dB @ 100kHz with
LDO1/LDO2
High PSRR : 50dB @ 1kHz, 40dB @ 10kHz with
LDO3/LDO4
300mA Low Dropout Voltage Regulators
Low Quiescent Current
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
1
RT5112A
Marking Information
Pin Configuration
(TOP VIEW)
1E : Product Code
YMDNN : Date Code
1E YM
DNN
A1
A2
A3
A4
A5
LXB1 VINB1 VINB2 LXB2 LXB2
B1
GNDB1 FB1
C1 C2
FB2 HWEN DGND SDA
D1 D2 D3 D4
B2
B3
B4
B5
NC INTRB GNDB2
C3
C4
C5
SCL
D5
VIN4 VIN3 VSYS REF VIN12
E1 E2 E3 E4 E5
LDO4 LDO3 AGND LDO2 LDO1
WL-CSP-25B 2.2 x 2.3 (BSC)
Typical Application Circuit
V
V
3.8V
IN_B1
3.8V
IN_B2
RT5112A
C3
10µF
C1
10µF
A2
A1
VINB2 A3
L2
VINB1
LXB1
1.2A Buck1
1.2A Buck2
L1
1µH
1µH
A4, A5
LXB2
V
V
OUT_BUCK1
0.6V to 3.3V
OUT_BUCK2
Driver
&
Control
Driver
&
Control
0.6V to 3.3V
C4
10µF
C2
10µF
B2
B1
FB2 C1
FB1
GNDB2 B5
GNDB1
D3 VSYS
B4 INTRB
HWEN C2
V
IN_SYS
3.8V
R1
Control Logic
NC
B3
C13
1µF
V
IN_B1
3.8V
2.2K
C5 SCL
E5
LDO1
2
300mA LDO1
Driver &
Control
V
OUT_LDO1
I C
BUS
2
I C
C4
SDA
C6 0.6 to 3.775V
2.2µF
VIN12 D5
V
IN_VIN12
3.8V
2.2µF
C5
300mA LDO2
Driver &
Control
LDO2 E4
LDO3 E2
V
OUT_LDO2
C7
0.6 to 3.775V
2.2µF
300mA LDO3
V
OUT_LDO3
C9 0.6 to 3.775V
2.2µF
Driver &
Control
VIN3 D2
VIN4 D1
V
IN_VIN3
C8
2.2µF
3.8V
D4 REF
Ref
C11
10nF
V
IN_VIN4
300mA LDO4
Driver &
Control
C12
3.8V
2.2µF
LDO4 E1
V
OUT_LDO4
C10 0.6 to 3.775V
2.2µF
AGND
E3
DGND
C3
Component List of Evaluation Board
Reference
C1, C2, C3, C4
C5, C8, C12
C6, C7, C9, C10
C11
Qty
1
Part Number
Description
10F/X5R/6.3V
2.2F/X5R/6.3V
2.2F/X5R/6.3V
10nF/X5R/6.3V
1F/X5R/10V
Package
0402
Manufacturer
TAIYO YUDEN
TAIYO YUDEN
MURATA
JMK105CBJ106MV-F
JMK105BJ225KV-F
GRM033R60J225ME47D
LMK105BJ103KV-F
LMK063BBJ105MPLF
MEKK2016T1R0M
1
0402
1
0201
1
0402
TAIYO YUDEN
TAIYO YUDEN
TAIYO YUDEN
C13
1
0201
L1, L2
1
1H/3.1A/50m
2016
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS5112A-02 August 2019
RT5112A
Functional Pin Description
Pin No.
Pin Name
Pin Function
A1
LXB1
Buck1 switch output. Connect with a wide PCB trace.
Supply voltage input of Buck1. The IC operates from a 2.5V to 5.5V input rail.
Requires a 10F ceramic capacitor to decouple the input rail. Connect using a
wide PCB trace.
A2
A3
VINB1
VINB2
Supply voltage input of Buck2. The IC operates from a 2.5V to 5.5V input rail.
Requires a 10F ceramic capacitor to decouple the input rail. Connect using a
wide PCB trace.
A4, A5
B1
LXB2
GNDB1
FB1
Buck2 switch output. Connect with a wide PCB trace.
Buck1 power ground.
B2
Feedback of Buck1. Directly connect the Buck1’s output to this pin.
This pin should connect to ground.
B3
NC
Interrupt output. Open drain output. When interrupt happens, interrupt pin is
pulled down.
B4
INTRB
B5
C1
C2
C3
C4
C5
GNDB2
FB2
Buck2 power ground.
Feedback of Buck2. Directly connect the Buck2’s output to this pin.
HWEN
DGND
SDA
Chip enable control input.
Digital ground.
I2C data pin.
SCL
I2C clock signal input.
LDO4 power supply input. Requires a 2.2F ceramic capacitor to decouple the
input rail.
D1
D2
VIN4
VIN3
LDO3 power supply input. Requires a 2.2F ceramic capacitor to decouple the
input rail.
System analog power supply. Requires a 1uF ceramic capacitor to decouple
the input rail. It also connected to VINB externally.
D3
D4
D5
VSYS
REF
Internal reference output, require a 10nF decouple capacitor.
LDO1 and 2 power supply input. Requires a 2.2F ceramic capacitor to
decouple the input rail.
VIN12
E1
E2
E3
E4
E5
LDO4
LDO3
AGND
LDO2
LDO1
LDO4 output. Requires a 2.2F ceramic decouple capacitor.
LDO3 output. Requires a 2.2F ceramic decouple capacitor.
Analog ground.
LDO2 output. Requires a 2.2F ceramic decouple capacitor.
LDO1 output. Requires a 2.2F ceramic decouple capacitor.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
3
RT5112A
Functional Block Diagram
1.2A Buck2
VINB2
LXB2
1.2A Buck1
VINB1
LXB1
Driver
&
Control
Driver
&
Control
FB2
FB1
GNDB2
GNDB1
VSYS
HWEN
Control Logic
INTRB
300mA LDO1
Driver &
Control
SCL
SDA
2
LDO1
VIN12
I C
300mA LDO2
Driver &
Control
LDO2
LDO3
VIN3
VIN4
300mA LDO3
Driver &
Control
Ref
REF
300mA LDO4
Driver &
Control
LDO4
AGND
DGND
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS5112A-02 August 2019
RT5112A
Absolute Maximum Ratings (Note 1)
VSYS, VINB1, VINB2, VIN12, VIN3, VIN4, LDO1, LDO2,
LDO3, LDO4, FB1, FB2, REF, SCL, SDA, HWEN, INTRB --------------------------------------------- −0.3V to 6.5V
LXB1, LXB2 (< 20ns) --------------------------------------------------------------------------------------------- −2V to 9V
PowerDissipation, PD @ TA = 25°C
WL-CSP-25B 2.2x2.3 (BSC) ----------------------------------------------------------------------------------- 3.05W
Package Thermal Resistance (Note 2)
WL-CSP-25B 2.2x2.3 (BSC), θJA ------------------------------------------------------------------------------ 32.7°C/W
Junction Temperature --------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.)----------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
Supply Voltage VIN_B1, VIN_B2, VSYS ---------------------------------------------------------------------------------- 2.5V to 5.5V
Supply Voltage VIN_VIN12, VIN_VIN3, VIN_VIN4 ------------------------------------------------------------------------ 1.9V to 5.5V
Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
System Parameter
HWEN = H, VIN_SYS = VIN_B1
=
=
VIN_B2 = VIN_VIN12 = VIN_VIN3
--
138
107
IQTATOL
VIN_VIN4 = 3.8V,
LDO/Buck1/Buck2 on, no load,
automode 40°C to 85°C
HWEN = H, VIN_SYS = VIN_VIN12
--
--
118
10
95
7
IQLDO
= VIN_VIN3 = VIN_VIN4 = 3.8V,
LDO on, no load, automode
HWEN = H, VIN_SYS = VIN_B1
VIN_B2 = VIN_VIN12 = VIN_VIN3
=
=
Quiescent Current
A
IQBASE
VIN_VIN4 = 3.8V, all power
regulators are off
HWEN = H, VIN_SYS = VIN_B1
3.8V, Buck1 on, no load,
automode
=
=
--
--
13
13
20
20
IQBUCK1
HWEN = H, VIN_SYS = VIN_B2
3.8V, Buck2 on, no load,
automode
IQBUCK2
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
5
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Leak current, HWEN = H, VIN_SYS
= VIN_B1 = VIN_B2 = VIN_VIN12
VIN_VIN3 = VIN_VIN4 = 2.5V to
5.5V, 40°C to 85°C
=
Leakage Current
--
--
1.5
A
ILEAK
VSYS Under-Voltage
Lockout Threshold Rising
UVLO
--
--
2.35
100
2.45
--
V
Hysteresis Voltage of
UVLO
UVLO_H
mV
HWEN Control
HWEN Low Level Input
Voltage
--
1.2
--
--
--
1
0.4
--
V
V
VIL
HWEN High Level Input
Voltage
VIH
REN
HWEN Pull Down
Resistor
-
M
Step Down Converter Buck1 (VIN_B1 = 3.8V, C1 = C2 = 10F, L1 = 1H)
Input Voltage Range
Output Voltage Range
Output Voltage Step
2.5
0.6
--
--
--
5.5
3.3
--
V
V
VIN_B1
VOUT_BUCK1
12.5
mV
All output range of VOUT_BUCK1
,
Output Voltage Accuracy
Switching Frequency
--
2
%
2
2
VOUT_ACCBUCK1
IOUT = IOUT(MAX)
VOUT_BUCK1 = 1.1V, operating
2.5
3
MHz
m
fSW_BUCK1
under CCM
P-Channel MOSFET On
Resistance
From VINB1 pin to LXB1 pin
--
150
200
RON_HG_BUCK1
N-Channel MOSFET On
Resistance
From LXB1 pin to GNDB1 pin
--
--
70
--
140
100
140
m
%
RON_LG_BUCK1
DMAX_BUCK1
RDIS_BUCK1
Maximum Duty Cycle
Output Discharge
Resistor
80
100
VOUT_
Over-Voltage Rising
Threshold Detection
--
--
--
--
--
--
--
--
V
V
V
V
OVP_R_BUCK1
OVP_F_BUCK1
UVP_R_BUCK1
UVP_F_BUCK1
BUCK1
x 120%
VOUT_
Over-Voltage Falling
Threshold Detection
BUCK1
x 109%
VOUT_
Under-Voltage Rising
Threshold Detection
BUCK1
x 92%
VOUT_
Under-Voltage Falling
Threshold Detection
BUCK1
x 80%
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS5112A-02 August 2019
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Buck1 disable, 0x0B[7] = 0
FB1 Leakage Current
0
50
100
nA
(Buck1 discharge disable), VIN_B1
= 5.5V, VLXB1 = 5.5V, VFB1 = 5.5V
Buck1 disable, 0x0B[7] = 0
IFB1_LK
Switch Leakage Current
(Buck1 discharge disable), VIN_B1
= 5.5V, VLXB1 = 0 or 5.5V
0
--
1
A
ILXB1_LK
2.5V
V
5.5V
UG Peak Current Limit
LG Valley Current Limit
1.5
1
2
2.5
2
A
A
IN_B1
ICL_peak_B1
ICL_valley_B1
1.5
VIN_B1 = 3.6V
LG Negative Current
Limit
0.5
--
3
A
INCL_NEG_B1
VIN_B1 = 3.6V, CCM
VIN_B1 = 3.6V, VOUT_BUCK1
1.8V
=
Minimum On Time
Minimum Off Time
167
20
200
40
250
60
ns
ns
tMIN_ON_B1
tMIN_OFF_B1
VIN_B1 = VOUT_BUCK1 = 3.3V
Step Down Converter Buck2 (VIN_B2 = 3.8V, C3 = C4 = 10F, L2 = 1H)
Input Voltage Range
Output Voltage Range
Output Voltage Step
2.5
0.6
--
--
--
5.5
3.3
--
V
V
VIN_B2
VOUT_BUCK2
12.5
mV
All output range of VOUT_BUCK2
,
Output Voltage Accuracy
Switching Frequency
--
2
%
2
2
VOUT_ACCBUCK2
fSW_BUCK2
IOUT = IOUT(MAX)
VOUT_BUCK2 = 2.85V, operating
under CCM
2.5
95
3
MHz
m
P-Channel MOSFET On
Resistance
From VINB2 pin to LXB2 pin
From LXB2 pin to GNDB2 pin
--
120
RON_HG_BUCK2
N-Channel MOSFET On
Resistance
--
--
100
--
130
100
120
m
%
RON_LG_BUCK2
DMAX_BUCK2
RDIS_BUCK2
Maximum Duty Cycle
Output Discharge
Resistor
80
100
VOUT_
Over-Voltage Rising
Threshold Detection
--
--
--
--
--
--
--
--
V
V
V
V
OVP_R_BUCK2
OVP_F_BUCK2
UVP_R_BUCK2
UVP_F_BUCK2
BUCK2
x 120%
VOUT_
Over-Voltage Falling
Threshold Detection
BUCK2
x 109%
VOUT_
Under-Voltage Rising
Threshold Detection
BUCK2
x 92%
VOUT_
Under-Voltage Falling
Threshold Detection
BUCK2
x 80%
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
7
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Buck2 disable, 0x0B[2] = 0
FB2 Leakage Current
(Buck2 discharge disable), VIN_B2
= 5.5V, VLXB2 = 5.5V, VFB2 = 5.5V
0
50
100
nA
IFB2_LK
Buck2 disable, 0x0B[2] = 0
(Buck 2discharge disable), VIN_B2
= 5.5V, VLXB2 = 0 or 5.5V
Switch Leakage Current
0
--
1
A
ILXB2_LK
UG Peak Current Limit
LG Valley Current Limit
2.5V
V
5.5V
1.5
1
2
2.5
2
A
A
ICL_peak_B2
ICL_valley_B2
IN_B2
1.5
VIN_B2 = 3.6V
LG Negative Current
Limit
0.5
--
3
A
INCL_NEG_B2
VIN_B2 = 3.6V, CCM
V
1.8V
IN_B2 = 3.6V, VOUT_BUCK2
=
Minimum On Time
Minimum Off Time
167
20
200
40
250
60
ns
ns
tMIN_ON_B2
tMIN_OFF_B2
VIN_B2 = VOUT_BUCK2 = 3.3V
Low Dropout Voltage Regulator LDO1 and LDO2 (VIN_VIN12 = VOUT_LDO1/VOUT_LDO2 + 1V, VHWEN = 1.2V, IOUT
= 1mA, CIN = 2.2F, COUT = 2.2F)
Input Voltage Range
Output Voltage Range
Output Voltage Step
1.9
0.6
--
--
5.5
3.775
--
V
V
VIN_VIN12
2.8
25
VOUT_LDO1
VOUT_LDO2
IOUT_LDO1
/
mV
/
Maximum Output Current
300
--
--
mA
s
IOUT_LDO2
Time from VOUT_LDO1/ VOUT_LDO2
start rising to 90% nominal value,
tSS_LDO1
/
Soft-Start Time
--
--
150
VOUT_LDO1/ VOUT_LDO2 = 2.8V, no
tSS_LDO2
load
DC Output Voltage
Accuracy
VOUT_ACCLDO1
VOUT_ACCLDO2
VLOAD_REG_LDO1
VLOAD_REG_LDO2
VLINE_REG_LDO1
VLINE_REG_LDO2
/
All output range of VOUT_LDO1
/
--
--
--
2
%
%
%
2
VOUT_LDO2, IOUT = IOUT(MAX)
/
Load Regulation
Line Regulation
0.5
0.5
0.5
0.5
I
OUT = 0 to IOUT(MAX)
/
IOUT = 50mA to 300mA, VIN_VIN12
= 3.0V to 4.4V, VO = 2.8V
IOUT = 300mA,
VDROPLDO1
/
Dropout Voltage
--
--
--
250
--
mV
VOUT_LDO1/VOUT_LDO2 = 2.8V
(Note 5)
VDROPLDO2
Output Discharge
Resistor
RDIS_LDO1
/
10
RDIS_LDO2
VOUT_
/
LDO1
Over-Voltage Rising
Threshold Detection
OVP_R_LDO1
/
--
--
V
VOUT_
OVP_R_LDO2
LDO2
x 120%
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS5112A-02 August 2019
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VOUT_
/
LDO1
Over-Voltage Falling
Threshold Detection
OVP_F_LDO1
/
--
--
V
VOUT_
OVP_F_LDO2
LDO2
x 110%
VOUT_
/
LDO1
Under-Voltage Rising
Threshold Detection
UVP_R_LDO1
/
--
--
--
--
V
V
VOUT_
UVP_R_LDO2
LDO2
x 90%
VOUT_
/
LDO1
Under-Voltage Falling
Threshold Detection
UVP_F_LDO1
/
VOUT_
UVP_F_LDO2
LDO2
x 80%
--
--
22
27
1
HWEN = 1.2V, IOUT = 0mA
HWEN = 0.3V (disable)
Quiescent Current
A
I
Q_LDO1/IQ_LDO2
0.1
Short Circuit Current
Limit
Isc_LDO1
/
360
--
--
mA
Isc_LDO2
0x01[3:2] = 11
ILimt_LDO1
/
(LDO1 current limit = 360mA),
0x02[3:2] = 11
(LDO2 current limit = 360mA)
Current Limit
360
415
470
mA
ILimt_LDO2
Short Protection On
Timer
tscp_ON_LDO1
tscp_ON_LDO2
tscp_OFF_LDO1
tscp_OFF_LDO2
/
--
--
2
--
--
ms
ms
Short Protection Off
Timer
/
40
Low Dropout Voltage Regulator LDO3 and LDO4 (VIN_VIN3/VIN_VIN4 = VOUT_LDO3/VOUT_LDO4 + 1V, VHWEN
=
1.2V, IOUT = 1mA, CIN= 2.2F, COUT = 2.2F)
VIN_VIN3
/
Input Voltage Range
1.9
--
5.5
V
VIN_VIN4
Output Voltage Range
Output Voltage Step
0.6
--
1.8
25
3.775
--
V
VOUT_LDO3
/
VOUT_LDO4
mV
IOUT_LDO3
/
Maximum Output Current
300
--
--
--
--
150
2
mA
s
%
IOUT_LDO4
Time from VOUT_LDO3
OUT_LDO4 start rising to 90%
nominal value, VOUT_LDO3
OUT_LDO4 = 1.8V, no load
All output range of VOUT_LDO3
OUT_LDO4, IOUT = IOUT(MAX)
/
tSS_LDO3/
V
Soft-Start Time
--
/
tSS_LDO4
V
DC Output Voltage
Accuracy
VOUT_ACCLDO3
/
/
2
VOUT_ACCLDO4
V
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
9
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VLOAD_REG_LDO3
/
Load Regulation
--
0.5
%
0.5
IOUT = 0 to IOUT(MAX)
VLOAD_REG_LDO4
I
OUT = 50mA/300mA, VIN_VIN3 /
VLINE_REG_LDO3
/
Line Regulation
Dropout Voltage
--
--
0.5
%
0.5
VIN_VIN4 = 3.0 to 4.4V,
VO = 1.8V
VLINE_REG_LDO4
I
OUT = 300mA, VOUT_LDO3
OUT_LDO4 = 1.8V
/
VDROPLDO3
/
--
--
150
--
mV
V
VDROPLDO4
(Note 5)
Output Discharge
Resistor
RDIS_LDO3
/
10
RDIS_LDO4
VOUT
/
_LDO3
Over-Voltage Rising
Threshold Detection
OVP_R_LDO3/
OVP_R_LDO4
--
--
--
--
--
--
--
--
V
V
V
V
VOUT
_LDO4
x 120%
VOUT
/
_LDO3
Over-Voltage Falling
Threshold Detection
OVP_F_LDO3
/
VOUT
OVP_F_LDO4
_LDO4
x 110%
VOUT
/
_LDO3
Under-Voltage Rising
Threshold Detection
UVP_R_LDO3
/
VOUT
UVP_R_LDO4
_LDO4
x 90%
VOUT
/
_LDO3
Under-Voltage Falling
Threshold Detection
UVP_F_LDO3
/
VOUT
UVP_F_LDO4
_LDO4
x 80%
--
--
22
27
1
HWEN = 1.2V, IOUT = 0mA
HWEN = 0.3V (disable)
Quiescent Current
A
I
Q_LDO3/IQ_LDO4
0.1
Short Circuit Current
Limit
Isc_LDO3
/
360
--
--
mA
Isc_LDO4
0x03[3:2] = 11
(LDO3 current limit = 360mA),
0x04[3:2] = 11
(LDO4 current limit = 360mA)
ILimt_LDO3
/
Current Limit
360
415
470
mA
ILimt_LDO4
Short Protection On
Timer
tscp_ON_LDO3
tscp_ON_LDO4
tscp_OFF_LDO3
tscp_OFF_LDO4
/
--
--
2
--
--
ms
ms
Short Protection Off
Timer
/
40
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10
DS5112A-02 August 2019
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
I2C Characteristics
SCL, SDA Low Input
Voltage
VI2CIL
--
1.2
--
--
--
--
0.4
--
V
V
V
SCL, SDA High Input
Voltage
VI2CIH
SCL, SDA Low Output
Voltage
VI2COL
0.4
I2C CLK Frequency
I2C Work Voltage
fSCL
VI2Cint
1
--
--
1.8
--
--
--
MHz
V
2
Input Current Each IO Pin
10
--
10
30
A
ns
IIN_I C
2
Data Hold Time
--
tDH_I C
2
Data Set-Up Time
70
--
--
ns
tDS_I C
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV
below its nominal value.
System Characteristics
The following system specifications are guaranteed by designed and are not performed in production testing.
(TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
System Parameter
Over-Temperature
Warning
OTW
115
--
125
20
135
--
°C
°C
°C
°C
Over-Temperature
Warning Hysteresis
OTW_H
OTP
Over-Temperature
Protection
130
--
140
20
150
--
Over-Temperature
Protection Hysteresis
OTP_H
0x0A[4:3] = 01
HWEN Control
HWEN = H to I2C operation
available
HWEN = L to I2C operation stop
HWEN Turn On Delay
HWEN Turn Off Delay
--
--
50
50
--
--
s
s
tHWEN_ON
tHWEN_OFF
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11
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Step Down Converter Buck1 (VIN_B1 = 3.8V, C1 = C2 = 10F, L1 = 1H)
Maximum Output Current
Load Regulation
1.2
--
--
--
--
A
IOUT_BUCK1
1.5
%
VLOAD_REG_BUCK1 CCM, VOUT_BUCK1 = 1.1V
CCM, IOUT = 50/300/1200mA,
VLINE_REG_BUCK1
Line Regulation
--
--
1.5
%
VOUT_BUCK1 = 1.1V, VIN_B1
3.0V to 4.4V
=
CCM, VOUT_BUCK1 = 1.1V, VIN_B1
< 4.35V
--
--
--
10
40
Output Ripple
mV
VRIPPLE_BUCK1
PFM, VOUT_BUCK1 = 1.1V, VIN_B1
< 4.35V
30
0x09[7:6] = 10, time from
VOUT_BUCK1 = 0V rising to 90%
Soft-Start Time
Load Transient
Efficiency
--
--
235
--
--
70
--
s
tSS_BUCK1
nominal value, VOUT_BUCK1
1.1V, no load
=
VOUT_BUCK1 = 1.1V, 20 to 80%
IOUT(MAX), 1? s, recovery time
< 10? s
VTRAN_BUCK1
Eff_BUCK1
VOUT_BUCK1 = 1.1V, IOUT =
200mA to 600mA
85
--
Step Down Converter Buck2 (VIN_B2 = 3.8V, C3 = C4 = 10F, L2 = 1H)
Maximum Output Current
1.2
--
--
--
--
A
IOUT_BUCK2
VLOAD_REG_BUCK2
Load Regulation
1.5
%
CCM, VOUT_BUCK2 = 2.85V
CCM, IOUT = 50/300/1200mA,
VLINE_REG_BUCK2
Line Regulation
Output Ripple
--
--
1.5
%
VOUT_BUCK2 = 2.85V, VIN_B2
3.0V to 4.4V
=
CCM, VOUT_BUCK2 = 2.85 V,
--
--
--
20
50
V
IN_B2 < 4.35V
PFM, VOUT_BUCK2 = 2.85V,
IN_B2 < 4.35V
0x09[7:6] = 10, time from
VOUT_BUCK2 = 0V rising to 90%
mV
VRIPPLE_BUCK2
40
V
Soft-Start Time
--
607
--
s
tSS_BUCK2
nominal value, VOUT_BUCK2
2.85V, no load
=
VOUT_BUCK2 = 2.85V, 20 to 80%
Load Transient
Efficiency
--
--
--
80
--
mV
%
VTRAN_BUCK2
I
OUT(MAX), 1s, recovery time <
10s
VOUT_BUCK2 = 2.85V, IOUT
200mA to 600mA
=
93
Eff_BUCK2
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12
DS5112A-02 August 2019
RT5112A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Low Dropout Voltage Regulator LDO1 and LDO2 (VIN_VIN12 = VOUT_LDO1/VOUT_LDO2 + 1V, VHWEN = 1.2V, IOUT
= 1mA, CIN = 2.2F, COUT = 2.2F)
VRIPPLE_LDO1
VRIPPLE_LDO2
VTRAN_LDO1
VTRAN_LDO2
/
IOUT = 0 to IOUT(MAX)
OUT_LDO1/VOUT_LDO2 = 2.8V
OUT = 1mA to 150mA, 150mA/s,
VOUT_LDO1/VOUT_LDO2 = 2.8V
IN_VIN12 = 3.4V, f = 1kHz, IOUT
,
Output Ripple Voltage
--
--
--
--
10
50
mV
mV
V
/
I
Load Transient
V
=
70
--
--
100mA, VOUT_LDO1/VOUT_LDO2
2.8V
=
Power Supply Rejection PSRR_LDO1
/
dB
Ratio
PSRR_LDO2
VIN_VIN12 = 3.4V, f = 100kHz, IOUT
40
--
--
--
--
= 100mA, VOUT_LDO1/VOUT_LDO2
= 2.8V
eN_LDO1
/
100Hz to 100kHz, IOUT = 100mA,
Output Noise Voltage
50
V
eN_LDO2
VOUT_LDO1/VOUT_LDO2 = 2.8V
Low Dropout Voltage Regulator LDO3 and LDO4 (VIN_VIN3/VIN_VIN4 = VOUT_LDO3/VOUT_LDO4 + 1V, VHWEN
=
1.2V, IOUT = 1mA, CIN= 2.2F, COUT = 2.2F)
VRIPPLE_LDO3
VRIPPLE_LDO4
VTRAN_LDO3
VTRAN_LDO4
/
IOUT = 0 to IOUT(MAX), VOUT_LDO3
/ VOUT_LDO4 = 1.8V
Output Ripple Voltage
--
--
--
--
10
50
mV
/
Load Transient
mV
I
OUT = 1mA to 150mA, 150mA/s
IN_VIN3 / VIN_VIN4 = 1.95V,
V
50
--
--
f = 1kHz, IOUT = 100mA,
VOUT_LDO3/VOUT_LDO4 = 1.8V
Power Supply Rejection PSRR_LDO3
/
dB
Ratio
PSRR_LDO4
VIN_VIN3 / VIN_VIN4 = 1.95V,
f = 10kHz, IOUT = 100mA,
40
--
--
--
--
V
OUT_LDO3/VOUT_LDO4 = 1.8V
100Hz to 100kHz, IOUT = 100mA,
OUT_LDO3/VOUT_LDO4
2.8V/1.8V
eN_LDO3/
eN_LDO4
Output Noise Voltage
50
V
V
=
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RT5112A
Typical Operating Characteristics
Shutdown Current vs. Temperature
Buck1 Quiescent Current vs. Input Voltage
12
1.0
11
10
9
0.8
0.6
0.4
0.2
8
7
VBUCK1 = 1.1V, Temperature = 25°C
HWEN = L
100 125
6
0.0
2.5
3.0
3.5
4.0
4.5
-50
-25
0
25
50
75
Temperature (°C)
Input Voltage (V)
Buck1 Quiescent Current vs. Temperature
Buck1 Efficiency
12
100
90
80
70
60
50
11
10
9
VINB1 = 3.4V
VINB1 = 3.8V
VINB1 = 4.35V
8
7
VINB1 = 3.8V, VBUCK1 = 1.1V
VBUCK1 = 1.1V
0.8 1.0 1.2
6
-50
-25
0
25
50
75
100
125
0.0
0.2
0.4
0.6
Temperature (°C)
Load Current (A)
Buck1 Load Regulation
Buck1 Output Voltage Ripple vs. Load Current
1.13
1.12
1.11
1.10
1.09
1.08
30
25
VINB1 = 4.35V
VINB1 = 3.8V
VINB1 = 3.4V
20
15
10
5
VINB1 = 4.35V
VINB1 = 3.8V
VINB1 = 3.4V
VBUCK1 = 1.1V
1.0
VBUCK1 = 1.1V
0.8 1.0 1.2
0
0.0
0.2
0.4
0.6
0.8
1.2
0.0
0.2
0.4
0.6
Load Current (A)
Load Current (A)
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DS5112A-02 August 2019
RT5112A
Buck1 Switching Frequency vs. Load Current
3.0
Buck1 Power On
SCL
(2V/Div)
2.5
VINB1
(1V/Div)
VINB1 = 4.35V
VINB1 = 3.8V
VINB1 = 3.4V
2.0
1.5
1.0
0.5
0.0
VINB1 = 3.8V, VBUCK1 = 1.1V, IBUCK1 = 0mA
VBUCK1
(500mV/Div)
IIN
VBUCK1 = 1.1V
0.8 1.0 1.2
(50mA/Div)
0.0
0.2
0.4
0.6
Time (200μs/Div)
Load Current (A)
Buck1 Load Transient
Buck1 Power Off
SCL
(2V/Div)
VINB1
(1V/Div)
VBUCK1
(50mV/Div)
VBUCK1
(500mV/Div)
IBUCK1
(200mA/Div)
VINB1 = 3.8V, VBUCK1 = 1.1V, IBUCK1 = 0mA
IIN
VINB1 = 3.8V, VBUCK1 = 1.1V,
IBUCK1 = 240mA to 960mA (tR = tF = 1μs)
(50mA/Div)
Time (50μs/Div)
Time (2ms/Div)
Buck2 Quiescent Current vs. Input Voltage
Buck2 Quiescent Current vs. Temperature
16
15
14
13
12
11
10
16
15
14
13
12
11
10
VBUCK2 = 2.85V, Temperature = 25°C
VINB2 = 3.8V, VBUCK2 = 2.85V
-50
-25
0
25
50
75
100
125
3.0
3.5
4.0
4.5
5.0
Temperature (°C)
Input Voltage (V)
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RT5112A
Buck2 Efficiency
Buck2 Load Regulation
100
95
2.91
2.90
2.89
2.88
2.87
2.86
2.85
2.84
VINB2 = 3.4V
VINB2 = 3.8V
VINB2 = 4.35V
90
85
80
75
70
VINB2 = 4.35V
VINB2 = 3.8V
VINB2 = 3.4V
VBUCK2 = 2.85V
0.8 1.0 1.2
VBUCK2 = 2.85V
0.8 1.0 1.2
0.0
0.2
0.4
0.6
0.0
0.2
0.4
0.6
Load Current (A)
Load Current (A)
Buck2 Output Voltage Ripple vs. Load Current
Buck2 Switching Frequency vs. Load Current
3.0
60
50
2.5
2.0
VINB2 = 4.35V
VINB2 = 3.8V
VINB2 = 3.4V
40
30
20
10
0
1.5
VINB2 = 3.4V
VINB2 = 3.8V
VINB2 = 4.35V
1.0
0.5
VBUCK2 = 2.85V
0.8 1.0 1.2
VBUCK2 = 2.85V
1.0 1.2
0.0
0.0
0.2
0.4
0.6
0.8
0.0
0.2
0.4
0.6
Load Current (A)
Load Current (A)
Buck2 Power On
Buck2 Power Off
SCL
SCL
(2V/Div)
(2V/Div)
VINB2
(1V/Div)
VINB2
(1V/Div)
VINB2 = 3.8V, VBUCK2 = 2.85V, IBUCK2 = 0mA
VBUCK2
(1V/Div)
VBUCK2
(1V/Div)
VINB2 = 3.8V, VBUCK2 = 2.85V, IBUCK2 = 0mA
IIN
IIN
(50mA/Div)
(50mA/Div)
Time (200μs/Div)
Time (2ms/Div)
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DS5112A-02 August 2019
RT5112A
Buck2 Load Transient
LDO Quiescent Current vs. Input Voltage
25
24
23
22
21
20
VBUCK2
(50mV/Div)
LDO4
LDO3
LDO2
LDO1
IBUCK2
(200mA/Div)
VINB2 = 3.8V, VBUCK2 = 2.85V,
IBUCK2 = 240mA to 960mA (tR = tF = 1μs)
VLDO1/VLDO2 = 2.8V, VLDO3/VLDO4 = 1.8V,
Temperature = 25°C
2.5
0.00
0.00
3.0
3.5
4.0
4.5
5.0
5.5
Time (50μs/Div)
Input Voltage (V)
LDO Quiescent Current vs. Temperature
LDO1 Load Regulation
30
28
26
24
22
20
18
16
2.802
2.800
2.798
2.796
2.794
2.792
2.790
2.788
2.786
LDO4
LDO3
LDO2
LDO1
VIN12 = 4.35V
VIN12 = 3.8V
VIN12 = 3.4V
VIN12 = 3V
VIN12/VIN3/VIN4 = 3.8V,
VLDO1/VLDO2 = 2.8V, VLDO3/VLDO4 = 1.8V
VLDO1 = 2.8V
-50
-25
0
25
50
75
100
125
0.05
0.10
0.15
0.20
0.25
0.30
Temperature (°C)
Load Current (A)
LDO2 Load Regulation
LDO3 Load Regulation
2.802
2.800
2.798
2.796
2.794
2.792
2.790
2.788
2.786
1.798
1.796
1.794
1.792
1.790
1.788
1.786
1.784
VIN12 = 4.35V
VIN12 = 3.8V
VIN12 = 3.4V
VIN12 = 3V
VIN3 = 4.35V
VIN3 = 3.8V
VIN3 = 3V
VIN3 = 2.8V
VIN3 = 2.5V
VIN3 = 1.95V
VLDO2 = 2.8V
0.25 0.30
VLDO3 = 1.8V
0.00
0.05
0.10
0.15
0.20
0.05
0.10
0.15
0.20
0.25
0.30
Load Current (A)
Load Current (A)
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RT5112A
LDO4 Load Regulation
LDO1 Dropout Voltage vs. Load Current
1.798
1.796
1.794
1.792
1.790
100
80
60
40
20
0
85°C
25°C
-40°C
VIN4 = 4.35V
VIN4 = 3.8V
VIN4 = 3V
1.788
1.786
1.784
VIN4 = 2.8V
VIN4 = 2.5V
VIN4 = 1.95V
VLDO1 = 2.8V
VLDO4 = 1.8V
0.25 0.30
0.00
0.05
0.10
0.15
0.20
0
50
100
150
200
250
300
Load Current (A)
Load Current (A)
LDO2 Dropout Voltage vs. Load Current
LDO3 Dropout Voltage vs. Load Current
140
120
100
80
100
80
60
40
20
0
85°C
25°C
-40°C
85°C
25°C
-40°C
60
40
20
VLDO2 = 2.8V
VLDO3 = 1.8V
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Load Current (A)
Load Current (A)
LDO4 Dropout Voltage vs. Load Current
LDO1/2 PSRR
20
0
140
120
100
80
85°C
25°C
-40°C
-20
-40
-60
-80
-100
LDO1
LDO2
60
40
20
VIN12 = 3.4V, VLDO1/VLDO2 = 2.8V,
ILDO1/ILDO2 = 100mA
VLDO4 = 1.8V
0
100
1000
10000
100000 1000000 10000000
0
50
100
150
200
250
300
Load Current (A)
Frequency (Hz)
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DS5112A-02 August 2019
RT5112A
LDO1/2 Output Noise
LDO3/4 PSRR
20
0
10
1
LDO1
LDO2
-20
-40
-60
-80
-100
LDO3
LDO4
0.1
0.01
VIN3/VIN4 = 1.95V, VLDO3/VLDO4 = 1.8V,
ILDO3/ILDO4 = 100mA
VLDO1/VLDO2 = 2.8V, ILDO1/ILDO2 = 100mA
1000 10000 100000
100
1000
10000
100000 1000000 10000000
100
Frequency (Hz)
Frequency (Hz)
LDO1 Power On
LDO3/4 Output Noise
10
1
SCL
(2V/Div)
VIN
(1V/Div)
LDO3
LDO4
VLDO1
(1V/Div)
0.1
0.01
VIN = 3.8V, VIN12 = 3.8V,
VLDO1 = 2.8V, ILDO1 = 0mA
IIN
VLDO3/VLDO4 = 1.8V, ILDO3/ILDO4 = 100mA
(50mA/Div)
100
1000
10000
100000
Time (100μs/Div)
Frequency (Hz)
LDO1 Power Off
LDO2 Power On
SCL
(2V/Div)
SCL
(2V/Div)
VIN
(1V/Div)
VIN
(1V/Div)
VIN = 3.8V, VIN12 = 3.8V,
VLDO1 = 2.8V, ILDO1 = 0mA
VLDO1
(1V/Div)
VLDO2
(1V/Div)
VIN = 3.8V, VIN12 = 3.8V,
VLDO2 = 2.8V, ILDO2 = 0mA
IIN
IIN
(50mA/Div)
(50mA/Div)
Time (100μs/Div)
Time (100μs/Div)
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RT5112A
LDO2 Power Off
LDO3 Power On
SCL
SCL
(2V/Div)
(2V/Div)
VIN
(1V/Div)
VIN
(1V/Div)
VIN = 3.8V, VIN12 = 3.8V,
VLDO2 = 2.8V, ILDO2 = 0mA
VLDO2
(1V/Div)
VLDO3
(500mV/Div)
VIN = 3.8V, VIN3 = 2.8V,
VLDO3 = 1.8V, ILDO3 = 0mA
IIN
IIN
(50mA/Div)
(50mA/Div)
Time (100μs/Div)
Time (100μs/Div)
LDO3 Power Off
LDO4 Power On
SCL
(2V/Div)
VIN
(1V/Div)
SCL
(2V/Div)
VIN
(1V/Div)
VLDO3
(500mV/Div)
VIN = 3.8V, VIN3 = 2.8V,
VLDO3 = 1.8V, ILDO3 = 0mA
VLDO4
(500mV/Div)
VIN = 3.8V, VIN4 = 2.8V,
VLDO4 = 1.8V, ILDO4 = 0mA
IIN
IIN
(50mA/Div)
(50mA/Div)
Time (100μs/Div)
Time (100μs/Div)
LDO4 Power Off
LDO1 Load Transient
SCL
(2V/Div)
VIN
VLDO1
(1V/Div)
(10mV/Div)
VLDO4
(500mV/Div)
VIN = 3.8V, VIN4 = 2.8V,
VLDO4 = 1.8V, ILDO4 = 0mA
VIN12 = 3.8V, VLDO1 = 2.8V,
ILDO1 = 1mA to 150mA (tR = tF = 1μs)
IIN
ILDO1
(50mA/Div)
(50mA/Div)
Time (100μs/Div)
Time (5μs/Div)
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DS5112A-02 August 2019
RT5112A
LDO3 Load Transient
LDO2 Load Transient
VLDO3
(10mV/Div)
VLDO2
(10mV/Div)
VIN3 = 2.8V, VLDO3 = 1.8V,
ILDO3 = 1mA to 150mA (tR = tF = 1μs)
VIN12 = 3.8V, VLDO2 = 2.8V,
ILDO2 = 1mA to 150mA (tR = tF = 1μs)
ILDO3
ILDO2
(50mA/Div)
(50mA/Div)
Time (5μs/Div)
Time (5μs/Div)
LDO4 Load Transient
VLDO4
(10mV/Div)
VIN4 = 2.8V, VLDO4 = 1.8V,
ILDO4 = 1mA to 150mA (tR = tF = 1μs)
ILDO4
(50mA/Div)
Time (5μs/Div)
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21
RT5112A
Application Information
When the RT5112A recovers from OTP, it can re-start in
three configurations with register 0x0A[4:3] bits.
The RT5112A is a smart power-management integrated
circuit (PMIC), which includes two Buck converters and
four LDOs.
0x0A[4:3] = 00, the RT5112A is manual re-start with
default register values.
System Under-Voltage Protection and Over-Voltage
Protection
0x0A[4:3] = 01, the RT5112A is auto recovery with last
register values before OTP.
The device does not operate with VSYS voltages below the
Under-Voltage Lock Out (UVLO) level. There is a typical
100mV hysteresis implemented to avoid unstable on/ off
behavior. The RT5112A is initialized in its default state
after VSYS voltage recovers from UVLO. When VSYS voltage
reaches the Over Voltage Protection level, the RT5112A
will disable Buck converter immediately to protect next
stage circuit input. The VSYS UV and OV status bits and
interrupt bits will be set, and INTRB pin will be pulled low
with corresponding to protection detected.
0x0A[4:3] = 10, the RT5112A is latched off. Re-set VIN
or HWEN to re-start the RT5112A with default register
values.
Enable and Disable Control
The HWEN pin controls the RT5112A start up without
enabling channels. If HWEN pin is at low state, the
RT5112Ais in power down mode and I2C will returnNACK
to any request. Only when HWEN pin is at high state, all
channels are controllable via I2C with corresponding
ENABLE command. There is a built-in resistor on HWEN
pin to keep at low state if the pin is left unconnected.
Thermal Protection
The RT5112Afeatures over-temperature warning (OTW)
and over-temperature protection (OTP). The OTW status
bit and interrupt bit are set and INTRB pin will be pulled
low when the junction temperature is higher than typical
125°C. If the junction temperature further exceeds typical
160°C, OTP will be triggered to shut down the device.
The below tables provide channels state with combinations
of different ENABLE pins and register EN bits.
Sequence Control Setting
The RT5112A sequence on/off control setting can be
programmed via I2C with dedicated registers as below.
Table 1. Buck and LDOs Control
EN bits SEQ_CTRL bits Dependent
HWEN pin
Low
SEQ bits
000
On / Off
Off
0
1
0
1
0
1
0
1
No
No
Low
000
Off
Low
000
No
Off
Low
000
No
Off
High
High
High
High
000
No
Off
000
No
On
000
Yes
CTRL
On
000
On / Off
Note : CTRL indicates several operating conditions as below.
(1) SEQ_CTRL[1:0] = 00, set SEQ bits
regardless EN bit.
000 and EN bit = 1, channel is turned off after 7 sequence slot count
(2) SEQ_CTRL[1:0] = 01, set SEQ bits000 and EN bit = 1, channel is turned on depends on EN bit.
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DS5112A-02 August 2019
RT5112A
Sequence (7 slots)
Note :
Registers 0x00[6:4]/ 0x06[6:4] are used to control
Buck1/Buck2 sequence on/off slot.
(1) Any changes in Sequence (7 slots), slot interval
time and soft-start time during sequence on or off
procedure is not valid and will not modify the RT5112A
setting.
Registers 0x01[6:4], 0x02[6:4], 0x03[6:4] and
0x04[6:4] are used to control LDOs sequence on/off
slots.
(2) Channel setting (output voltage, current limit...etc.)
is fixed during on or off sequence.
Slot Interval Time
Register 0x09[7:6] is used to control interval time
between each slot.
(3) Register 0x09[5:4] = 11 will turn off all channels
immediately.
Soft Start Time
(4) HWEN= 0 will turn off all channels and the RT5112A
enters into power down mode.
Register 0x09[7:6] is used to control Bucks sequence
on soft start time.
Normal Control Setting
Register 0x11[1:0] is used to control LDOs sequence
on soft start time.
When register bits 0x09[5:4] = 10, the Bucks and LDOs
on/off control depends on channel Enable bit.
Sequence Control
Registers 0x00[7]/0x06[7] are used to control Bucks
on/off.
Register 0x09[5:4] = 00 is used to enable sequence
off with sequence setting 000.
Register 0x01[7], 0x02[7], 0x03[7] and 0x04[7] are
used to control LDOs on/off.
Register 0x09[5:4] = 01 is used to enable sequence
on with sequence setting000.
HWEN
BUCK1_DELAY
LDOX_DELAY
SEQ_CTRL = 10
SEQ_CTRL = 01
SEQ_CTRL = 00
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 1.
Example for sequence on/off with BUCK1 assign to SLOT1, LDO1 assign to SLOT2, LDO2 assign to SLOT3, LDO3
assign to SLOT4 and LDO4 assign to SLOT5.
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RT5112A
HWEN
BUCK1_DELAY
LDOX_DELAY
SEQ_CTRL = 10
SEQ_CTRL = 01
SEQ_CTRL = 00
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 2.
Example for sequence on/off with BUCK1 assign to SLOT1, LDO1 assign to SLOT3, LDO2 assign to SLOT3, LDO3
assign to SLOT7 and LDO4 assign to SLOT5.
HWEN
BUCK1_DELAY
LDO2_DELAY, LDO3_DELAY and LDO4_DELAY change setting
LDOX_DELAY
SEQ_CTRL = 10
SEQ_CTRL = 01
SEQ_CTRL = 00
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 3.
Example for sequence slot change when on procedure. LDO2 assign from SLOT3 to SLOT5, LDO3 assign from SLOT4
to SLOT6 and LDO4 assign from SLOT5 to SLOT7. There is no influence with on procedure and new setting will
executed after on sequence finish.
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DS5112A-02 August 2019
RT5112A
HWEN
BUCK1_DELAY
LDOX_DELAY
SEQ_CTRL = 10
SEQ_CTRL = 01
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 4.
Example for sequence on is interrupted by HWEN signal low. The RT5112A turns off all channels immediately.
HWEN
BUCK1_DELAY
LDOX_DELAY
SEQ_CTRL = 10
SEQ_CTRL = 01
SEQ_CTRL = 00
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 5.
Example for sequence off is interrupted by HWEN signal low. The RT5112A turns off all channels immediately.
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RT5112A
HWEN
LDOX_DELAY
SEQ_CTRL = 10
BUCK1_EN
LDO1_EN
SEQ_CTRL = 01
SEQ_CTRL = 00
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 6.
Example for sequence control SEQ_CTRL change from 01 to 00. LDO2, LDO3, LDO4 are sequence off and LDO1 is
turned off by itself enable bit. BUCK1 is turned off after 7 sequence slot count even itself enable bit is at high state.
HWEN
LDOX_DELAY
SEQ_CTRL = 10
BUCK1_EN
LDO1_EN
SEQ_CTRL = 01
SEQ_CTRL = 10
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 7.
Example for sequence control SEQ_CTRL change from 01 to 10. LDO2, LDO3, LDO4 are turned off and state of BUCK1,
LDO1 depends on itself enable bit.
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DS5112A-02 August 2019
RT5112A
HWEN
LDOX_DELAY
SEQ_CTRL = 10
BUCK1_EN
LDO1_EN
SEQ_CTRL = 01
SEQ_CTRL = 11
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT7
SLOT6
SLOT5
SLOT4
SLOT3
SLOT2
SLOT1
BUCK1
LDO1
LDO2
LDO3
LDO4
Figure 8.
Example for sequence control SEQ_CTRL change from 01 to 11. All channels are turned off immediately.
Output Voltage Setting
The RT5112Aoutput voltage can be programmed via I2C
with dedicated registers.
Bucks
Auto PFM (Pulse Frequency Modulation) Mode
In order to save power and improve efficiency at low
loads, the Buck operates in PFM mode as the inductor
drops into DCM (Discontinuous Current Mode). The
switching frequency is proportional to loading to reach
output voltage regulation. When load increases and
inductor current becomes continuous again, the Buck
automatically goes back to PWM fixed frequency
mode. Additionally, the RT5112A will enters DSLP
(Deep Sleep) to reach input low quiescent current at
no load.
Bucks
Registers 0x0C[7:0]/0x12[7:0] are used to control
Bucks output voltage.
Register 0x14[7:6] is used to control Bucks voltage
scaling slew rate.
LDOs
Registers 0x0D[7:1], 0x0E[7:1], 0x0F[7:1], 0x10[7:1]
are used to control LDO1, LDO2, LDO3 and LDO4
output voltage.
Register 0x14[5:4] is used to control LDOs voltage
scaling slew rate.
FPWM (Forced Pulse Width Modulation) Mode
The switching frequency is forced into PWM mode
2.5MHz (typ.) operation. In this mode, the inductor
current is in CCM (Continuous Current Mode) and
the voltage is regulated by PWM.
Operating Mode
The RT5112Aprovides different operating modes for Bucks
and LDOs for flexible application. Registers 0x00[1:0],
0x01[1:0], 0x02[1:0], 0x03[1:0], 0x04[1:0] and 0x06[1:0]
are used to control the operating mode.
Normal Mode
The operation is same as Auto PFM mode. The only
one difference is that there is no DSLP in this mode.
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RT5112A
Ultra-Sonic Mode
OCP Mechanism
Bucks
To avoid acoustic noise problem when operation, the
switching frequency is designed to be always higher
than 20kHz even there is no load at output.
When the inductor current reaches the high-side
MOSFET peak current limit threshold, the high-side
MOSFET will be turned-off. The low-side MOSFET
turns on to discharge the inductor current until the
inductor current trips below the low-side MOSFET
valley current limit threshold. After high-side
MOSFET peak current limit triggered, the maximum
inductor current is decided by the inductor current
rising rate and the response delay time of the internal
network.
LDOs
Auto Mode
This mode is for general use.
EN Forced Mode
When ENForced Mode is selected, the RT5112Acan
provide higher PSRR (Power Supply Rejection Ratio)
to mitigate interference from input voltage. However,
it brings out higher quiescent current to get the
function.
LDOs
When the loading reaches the current limit threshold,
the current sent to the output will kept at current
limit level.
Bypass Mode
LDO internal power MOSFET is fully turned on. Input
voltage will pass through it to the output terminal
directly.
Under-Voltage Protection (UVP)
Behavior after UVP
Register 0x0A[7:6] is used to select the operation
after under voltage failure detected.
Channel Protection Features
The RT5112A equips Over-Current Protection, Under-
Voltage Protection and Over-Voltage Protection to prevent
the device from damages causing by abnormal operation
or fault conditions. (over-load, short-circuit, soldering
issue...etc.)
Ovrt-Voltage Protection (OVP)
Behavior after OVP
Register 0x0A[2:1] is used to select the operation
after over voltage failure detected.
Over-Current Protection (OCP)
Behavior after OCP
Register 0x37[7:6] is used to select the operation
after over-current failure detected.
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DS5112A-02 August 2019
RT5112A
Table 2. Protection
Threshold
(typ.)
Deglitch Time
(typ.)
Reset and Threshold
(typ.)
Channel
Type
Protection
VSYS < 2.35V
VSYS 2.25V
(after IC Operation)
UVLO
525s
IC Shutdown
Buck Disable
VSYS 2.35V
OVP
OTW
VSYS 5.9V
200s
50s
VSYS 5.6V
Temperature 125°C
Report only
Temperature 105°C
Selection by 0x0A[4:3]
00 : Manual recovery
after TSD with reset
register
System
OTP
Temperature 140°C
50s
IC Shutdown
01 : Auto recovery after
TSD with no reset
register
10 : Latch off after TSD
with reset register
Selection by 0x0A[7]
0 : Hiccup mode
1 : Latch-off mode
VBUCK VBUCK_SET
x
x
VBUCK VBUCK_SET x
UVP
OVP
OCP
UVP
OVP
OCP
50s
50s
8s
80%
92%
Selection by 0x0A[2]
0 : Discharge mode
1 : Latch-off mode
VBUCK VBUCK_SET
BUCKs
VBUCK VBUCK_SET x 109%
120%
ILXBUCK_peak 2A
Selection by 0x037[7] ILXBUCK_peak < 2A
0 : Hiccup mode
1 : Latch-off mode
ILXBUCK_valley 1.5A
ILXBUCK_valley < 1.5A
(peak - 0.5A)
(peak - 0.5A)
Selection by 0x0A[6]
0 : Hiccup mode
1 : Latch-off mode
VLDO VLDO x 80%
VLDO VLDO x 120%
ILDO > 415mA
50s
50s
8s
VLDO VLDO x 90%
Selection by 0x0A[1]
0 : Discharge mode
1 : NA
LDOs
VLDO VLDO x 110%
ILDO 415mA
Selection by 0x037[6]
0 : Hiccup mode
1 : Latch-off mode
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RT5112A
Interrupt
Fault Event and Status
The RT5112Ainterrupt controller continuously monitors the device operation. Once the fault is ever detected, the fault
event bit will be set to 1 and the open drain interrupt indicate pin INTRB will be driven to ground level. Meanwhile, the
fault status bit will also be set to 1 to show the present fault. When the host reads the fault event bit and set interrupt
clear bit 0x14[0] = 1, the INTRB pin will be released to high impedance. The fault status bit goes back to 0 only till the
fault condition is cleared.
Table 3. Interrupt
Fault Event
BUCK_UV_EVT 0x15[7]
LDO1_UV_EVT 0x15[6]
LDO2_UV_EVT 0x15[5]
LDO3_UV_EVT 0x15[4]
LDO4_UV_EVT 0x15[3]
BUCK2_UV_EVT 0x15[1]
BUCK_OV_EVT 0x16[7]
LDO1_OV_EVT 0x16[6]
LDO2_OV_EVT 0x16[5]
LDO3_OV_EVT 0x16[4]
LDO4_OV_EVT 0x16[3]
BUCK2_OV_EVT 0x16[1]
BUCK_OCP_EVT 0x17[7]
LDO1_OCP_EVT 0x17[6]
LDO2_OCP_EVT 0x17[5]
LDO3_OCP_EVT 0x17[4]
LDO4_OCP_EVT 0x17[3]
BUCK2_OCP_EVT 0x17[1]
TWARN_EVT 0x19[7]
Fault Status
BUCK_UV_STAT 0x2B[7]
LDO1_UV_STAT 0x2B[6]
LDO2_UV_STAT 0x2B[5]
LDO3_UV_STAT 0x2B[4]
LDO4_UV_STAT 0x2B[3]
BUCK2_UV_STAR 0x2B[1]
BUCK_OV_STAT 0x2C[7]
LDO1_OV_STAT 0x2C[6]
LDO2_OV_STAT 0x2C[5]
LDO3_OV_STAT 0x2C[4]
LDO4_OV_STAT 0x2C[3]
BUCK2_OV_STAT 0x2C[1]
BUCK_OCP_STAT 0x2D[7]
LDO1_OCP_STAT 0x2D[6]
LDO2_OCP_STAT 0x2D[5]
LDO3_OCP_STAT 0x2D[4]
LDO4_OCP_STAT 0x2D[3]
BUCK2_OCP_STAT 0x2D[1]
TWARN_STAT 0x2F[7]
Description
BUCK output under-voltage
LDO1 output under-voltage
LDO2 output under-voltage
LDO3 output under-voltage
LDO4 output under-voltage
BUCK2 output under-voltage
BUCK output over-voltage
LDO1 output over-voltage
LDO2 output over-voltage
LDO3 output over-voltage
LDO4 output over-voltage
BUCK2 output over-voltage
BUCK over-current
LDO1 over-current
LDO2 over-current
LDO3 over-current
LDO4 over-current
BUCK2 over-current
Thermal warning
TSD_EVT 0x19[6]
TSD_STAT 0x2F[6]
Thermal shutdown
VSYSUV_EVT 0x19[5]
VSYSOV_EVT 0x19[4]
VSYSUV_STAT 0x2F[5]
VSYSOV_STAT 0x2B[4]
System under-voltage
System over-voltage
Fault Event Mask
The host can set the fault event mask bits to hide the fault events. When the mask bit is set to 1, the corresponding
fault is hidden and the interrupt indicate pin INTRB will keep high impedance without being pulled to ground level. The
host requires to read the fault event bits to clear its value to 0, otherwise the interrupt indicate pin INTRB will be driven
to low level again when mask bits being set to 1. The mask bits will be reset to default value with conditions : HWEN
voltage goes to low level or IC power shutdown.
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DS5112A-02 August 2019
RT5112A
HWEN
Fault
INTRB
MASK = 0
EVENT = 0
Status = 0
INT_CLS = 0
EVENT READ
MASK = 1
MASK = 0
MASK = 1
MASK=0
EVENT = 0
EVENT = 1
EVENT = 0
EVENT = 1
Status = 1
Status = 0
Status = 1
Status = 0
1
INT_CLS = 0
1
INT_CLS = 0
READ
READ
Figure 9.
IL
Component Selection
Inductor Selection
VOUT VESR VOUT1
8COUT fSW
V
ICOUT_RMS RCOUT_ESR
where
ESR
The recommended nominal inductance 1μH for Buck
converter. The inductor saturation current must be
chosen carefully considering the current limit level. It
is suggested to select an inductor with the low DCR to
provide good performance and efficiency for application.
LDOs
Like any low dropout regulator, the external capacitors
of the RT5112A must be carefully selected for
regulator stability and performance. Using a capacitor
of at least 2.2μF (X5R or X7R) is suitable.
Input and Output Capacitor Selection
It is recommended at least a 10μF (6.3V) input capacitor
for Buck, a 10μF (6.3V) output capacitor for Buck. The
ripple voltage is an important index for choosing output
capacitor. This portion consists of two parts. One is
the product of ripple current with the ESR of the output
capacitor, while the other part is formed by the charging
and discharging process of the output capacitor. The
output ripple can be calculated as below.
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RT5112A
I2C Interface
The following table shows the RT5112Aunique address as below.
RT5112A I2C Slave Address
LSB R/W bit
1/0
MSB
R/W
010000
1
43/42
The I2C interface bus must be connect a resistor 2.2kΩ to power node and independent connection to processor,
individually. The I2C timing diagrams are listed below.
Read and Write Function
Read single byte of data from Register
Slave Address
Register Address
Slave Address
MSB
MSB
Data
LSB
A
A
P
S
0
A
A
A
Sr
Sr
1
A
A
Assume Address = m
Data for Address = m
R/W
Read N bytes of data from Registers
Slave Address
Register Address
Slave Address
MSB
Data 1
LSB
S
0
A
1
Assume Address = m
Data for Address = m
LSB
R/W
MSB
Data 2
LSB
Data N
A
A
P
Data for Address = m + N - 1
LSB
Data for Address = m + 1
Write single byte of data to Register
Slave Address
Register Address
MSB
Data
S
0
A
A
A
A
P
Assume Address = m
Data for Address = m
R/W
Write N bytes of data to Registers
Slave Address
Register Address
MSB
Data 1
LSB MSB
A
Data 2
LSB
S
0
A
A
Assume Address = m
Data for Address = m
MSB
Data for Address = m + 1
LSB
R/W
Data N
A
P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave, P Stop, S Start, Sr Repeat Start
I2C Waveform Information
SDA
t
t
BUF
LOW
t
t
F
t
R
t
F
t
t
R
t
SU;DAT
HD;STA
SP
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
HIGH
HD;DAT
S
P
S
S
r
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DS5112A-02 August 2019
RT5112A
I2C Register Table
R : Read only.
RC : Read then Clear.
RW : Read and Wirte.
WC : Write “1” then clear to “0” after this procedure finish.
Note 6. Below registers setting are only available on the RT5112.
0x05, 0x08, 0x0A[5][0], 0x0B[5][1], 0x11[7:2], 0x13[1:0], 0x14[3:2], 0x15[2][0], 0x16[2], 0x17[2], 0x2B[2][0], 0x2C[2],
0x2D[2], 0x30[2], 0x32[2][0], 0x33[2], 0x34[2], 0x37[5][3:2], 0x3B[2] and 0x43[7:6].
Addr
RegName
Bit
BitName
Default Type
Description
Buck enable. This bit is mask if REG0x00[6:4] :
BUCK_DELAY ≠ 3'b000
0 : Disable (default)
7
BUCK_EN
0
RW
1 : Enable
Note : When Buck's latch-off protection happen,
this bit will reset to "0"
Buck power on/off delay time setting:
000 : Controlled by I2C with REG0x00[7] :
BUCK_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
100 : SLOT4
101 : SLOT5
BUCK_
DELAY
6:4
000
RW
110 : SLOT6
111 : SLOT7
0x00 Buck_CTRL
(delay time setting at on/off sequence are reverse)
Note : When Buck's latch-off protection happen,
these bits will reset to "000"
Buck current limit set bit.
00 : 1.5A
01 : 2A (default)
10 : 2.5A
BUCK_
ILIM
3:2
1:0
01
00
RW
RW
11 : 3A
Buck operation mode :
00 : Auto PFM mode (default)
01 : Forced PWM mode
10 : Ultra sonic mode
11 : Normal mode
BUCK_
MODE
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33
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO1 enable. This bit is mask if REG0x01[6:4] :
LDO1_DELAY ≠ 3'b000
0 : Disable (default)
1 : Enable
7
LDO1_EN
0
RW
Note : When LDO1's latch-off protection happen, this
bit will reset to "0"
LDO1 power on/off delay time setting:
000 : Controlled by I2C with REG0x01[7] : LDO1_EN
(default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
LDO1_
DELAY
6:4
000
RW 100 : SLOT4
101 : SLOT5
110 : SLOT6
111 : SLOT7
(delay time setting at on/off sequence are reverse)
0x01 LDO1_CTRL
Note : When LDO1's latch-off protection happen,
these bits will reset to "000"
LDO1 current limit set bit.
00 : 150mA
3:2
1:0
11
00
RW 01 : 250mA
LDO1_ILIM
10 : 300mA
11 : 360mA (default)
LDO1 operation mode :
00 : Auto mode (default)
01 : EN forced mode. (High PSRR mode).
RW 10 : Bypass mode. LDO1 internal power MOSFET
turns on fully.
LDO1_
MODE
11 : Bypass mode. LDO1 internal power MOSFET
turns on fully.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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34
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO2 enable. This bit is mask if REG0x02[6:4] :
LDO2_DELAY ≠ 3'b000
0 : Disable (default)
1 : Enable
7
LDO2_EN
0
RW
Note : When LDO2's latch-off protection happen,
this bit will reset to "0"
LDO2 power on/off delay time setting :
000 : Controlled by I2C with REG0x02[7] :
LDO2_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
RW 100 : SLOT4
101 : SLOT5
LDO2_
DELAY
6:4
000
110 : SLOT6
111 : SLOT7
0x02 LDO2_CTRL
(delay time setting at on/off sequence are reverse)
Note : When LDO2's latch-off protection happen,
these bits will reset to "000"
LDO2 current limit set bit.
00 : 150mA
RW 01 : 250mA
LDO2_
ILIM
3:2
1:0
11
00
10 : 300mA
11 : 360mA (default)
LDO2 operation mode :
00 : Auto mode (default)
01 : EN forced mode. (High PSRR mode).
RW 10 : Bypass mode. LDO2 internal power MOSFET
turns on fully.
LDO2_
MODE
11 : Bypass mode. LDO2 internal power MOSFET
turns on fully.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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35
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO3 enable. This bit is mask if REG0x03[6:4] :
LDO3_DELAY ≠ 3'b000
0 : Disable (default)
1 : Enable
7
LDO3_EN
0
RW
Note : When LDO3's latch-off protection happen,
this bit will reset to "0"
LDO3 power on/off delay time setting :
000 : Controlled by I2C with REG0x03[7] :
LDO3_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
RW 100 : SLOT4
101 : SLOT5
LDO3_
DELAY
6:4
000
110 : SLOT6
111 : SLOT7
0x03 LDO3_CTRL
(delay time setting at on/off sequence are reverse)
Note : When LDO3's latch-off protection happen,
these bits will reset to "000"
LDO3 Current limit set bit.
00 : 150mA
RW 01 : 250mA
LDO3_
ILIM
3:2
1:0
11
00
10 : 300mA
11 : 360mA (default)
LDO3 operation mode :
00 : Auto mode (default)
01 : EN forced mode. (High PSRR mode).
RW 10 : Bypass mode. LDO3 internal power MOSFET
turns on fully.
LDO3_
MODE
11 : Bypass mode. LDO3 internal power MOSFET
turns on fully.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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36
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO4 enable. This bit is mask if REG0x04[6:4] :
LDO4_DELAY ≠ 3'b000
0 : Disable (default)
1 : Enable
7
LDO4_EN
0
RW
Note : When LDO4's latch-off protection happen, this
bit will reset to "0"
LDO4 power on/off delay time setting :
000 : Controlled by I2C with REG0x04[7] : LDO4_EN
(default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
LDO4_DE
LAY
6:4
000
RW 100 : SLOT4
101 : SLOT5
110 : SLOT6
111 : SLOT7
0x04 LDO4_CTRL
(delay time setting at on/off sequence are reverse)
Note : When LDO4's latch-off protection happen,
these bits will reset to "000"
LDO4 current limit set bit.
00 : 150mA
RW 01 : 250mA
LDO4_ILI
M
3:2
1:0
11
00
10 : 300mA
11 : 360mA (default)
LDO4 operation mode :
00 : Auto mode (default)
01 : EN forced mode. (High PSRR mode).
RW 10 : Bypass mode. LDO4 internal power MOSFET
turns on fully.
LDO4_MO
DE
11 : Bypass mode. LDO4 internal power MOSFET
turns on fully.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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37
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Boost linear charge current :
RW 0 : 400mA (default)
7
LCH_ON
0
1 : 800mA
Boost NFC enable. 0x39[2] must set 0 when bit
NFC_EN = 1.
0 : Disable
6
NFC_EN
1
RW
1 : Enable (default)
Voltage scaling slew rate for Boost.
00 : 14mV/s (default)
RW 01 : 10mV/s
10 : 6mV/s
11 : 4mV/s
Boost current limit set bit.
00 : 2A
RW 01 : 2.5A (default)
10 : 3A
BOOST_
SS
5:4
00
01
BOOST_
CTRL
0x05
BOOST_
ILIM
3:2
1:0
11 : 3.5A
Boost operation mode:
00 : Auto PFM mode (default)
RW 01 : Forced PWM mode
10 : Ultra sonic mode
BOOST_
MODE
00
11 : Normal mode
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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38
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
BUCK2 enable. This bit is mask if REG0x06[6:4] :
BUCK2_DELAY ≠ 3'b000
0 : Disable (default)
BUCK2_
EN
7
0
RW
1 : Enable
Note : When Buck2's latch-off protection happen,
this bit will reset to "0"
BUCK2 power on/off delay time setting :
000 : Controlled by I2C with REG0x06[7] :
BUCK2_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
RW 100 : SLOT4
101 : SLOT5
BUCK2_
DELAY
6:4
000
110 : SLOT6
111 : SLOT7
0x06 Buck2_CTRL
(delay time setting at on/off sequence are reverse)
Note : When Buck2's latch-off protection happen,
these bits will reset to "000"
BUCK2 current limit set bit.
00 : 1.5A
RW 01 : 2A (default)
BUCK2_
ILIM
3:2
1:0
01
00
10 : 2.5A
11 : 3A
BUCK2 operation mode:
00 : Auto mode (default)
RW 01 : Forced PWM mode
10 : Ultra sonic mode
BUCK2_
MODE
11 : Normal mode
Addr
RegName
Bit
BitName
Default Type
11001101
Description
Vendor identification
0x07
Product ID
7:0
PID
R
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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39
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Enable bit #7 for the Boost.
RW 0 : Disable (default)
BOOST_
EN7
7
0
0
0
0
0
0
0
0
1 : Enable
Enable bit #6 for the Boost.
BOOST_
EN6
6
5
4
3
2
1
0
RW 0 : Disable (default)
1 : Enable
Enable bit #5 for the Boost.
BOOST_
EN5
RW 0 : Disable (default)
1 : Enable
Enable bit #4 for the Boost.
BOOST_
EN4
RW 0 : Disable (default)
1 : Enable
BOOST_
ENABLE
0x08
Enable bit #3 for the Boost.
BOOST_
EN3
RW 0 : Disable (default)
1 : Enable
Enable bit #2 for the Boost.
BOOST_
EN2
RW 0 : Disable (default)
1 : Enable
Enable bit #1 for the Boost.
BOOST_
EN1
RW 0 : Disable (default)
1 : Enable
Enable bit #0 for the Boost.
BOOST_
EN0
RW 0 : Disable (default)
1 : Enable
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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40
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Set slot period :
00 : 2.73ms
01 : 1.365ms
10 : 0.682ms (default)
11 : 0.341ms
(slot period is the base unit of each SLOT, for
example SLOT2 = 2*slot period; SLOT3 = 3*slot
period)
Set soft-start time slew rate (Buck_SR) :
00 : 1mV/s
RW 01 : 2mV/s
SEQ_SPE
ED[1:0]
7:6
10
10 : 4mV/s (default)
11 : 7mV/s
(Buck's VOUT min. step = 12.5mV, f = 2.5MHz)
(Once slot period is chose, corresponding soft start
time slew rate is determined.)
Note : Buck soft-start time (Buck_tss)
00 : 1ms/V x Vout
0x09 SEQ_PROG
01 : 0.5ms/V x Vout
10 : 0.25ms/V x Vout (default)
11 : 0.143ms/V x Vout
2 bits to control LDOs and Buck's ON/OFF
00 : Power-Down, relative regulators (CHx_DELAY
≠ 3’b000) disable by power off sequence, others
turn off by each EN bit
SEQ_
CTRL[1:0]
01 : Power-UP,relative regulators (CHx_DELAY ≠
3’b000) enable by power on sequence, others turn
on by each EN bit
5:4
10
RW
10 : All regulators's ON/OFF depend on each EN
bit. (default)
11 : All regulators turn off directly.
3:0 Reserved
0000
RW Reserved
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41
RT5112A
Addr
RegName
Bit BitName
Default Type
Description
Buck hiccup or latch off mode selection after VO UV.
0 : Hiccup mode; (continouously hiccup more than 3
times would enter latch-off mode ,select deglitch
time by REG0x38[7:6], hiccup on/off time = 5/8ms)
(default)
BUCK_UV
_LATCH
7
0
0
0
RW
RW
RW
1 : Latch-off mode
LDO hiccup or latch off mode selection after VO UV.
0 : Hiccup mode; (continouously hiccup more than 3
times would enter latch-off mode ,select deglitch
time by REG0x38[3:2], hiccup on/off time = 5/40ms)
(default)
LDO_UV_
LATCH
6
1 : Latch-off mode
Boost hiccup or latch off mode selection after VO UV.
0 : Hiccup mode; (continouously hiccup more than 3
times would enter latch-off mode ,select deglitch
time by REG0x37[3:2], hiccup on/off time =
11/100ms) (default)
BOOST_U
V_LATCH
5
1 : Latch-off mode
IC protection after thermal shutdown :
00 : Manual recovery after TSD with reset I2C
register. The power up sequence is initiated with
default I2C register value
0x0A
Latch
01 : Auto recovery after TSD with no reset I2C
register. The power up sequence is initiated with I2C
register value (default)
4:3
TSD[1:0]
01
RW
10 : Latch off after TSD, all Reg reset. Restart by Vin
start up or (BSTEN = 0 → 1 to restart Boost) or
(HWEN = 0 → 1 to eanble channel), i.e.BSTEN and
HWEN need pull low to unlock
11 : No change, follow before setting
Buck discharge or latch off mode selection after VO
BUCK_OV
_LATCH
OV.
2
0
RW
RW
0 : R Discharge (default)
1: Latch-off mode
LDO discharge mode selection after VO OV.
0 : R Discharge; (During DVS period won't sent OV
Event to INTRB) (default)
LDO_OV_
LATCH
1
0
0
0
1 : NA
Boost latch off mode selection after VO OV.
RW 0 : NA (default)
1 : Latch-off mode
BOOST_O
V_LATCH
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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42
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck active output discharge.
RW 0 : Disable
BUCK_
DIS
7
1
1
1
1 : Enable (default)
LDO active output discharge.
RW 0 : Disable
6
5
LDO_DIS
1 : Enable (default)
Boost active output discharge.
RW 0 : Disable
1 : Enable (default)
BOOST_
DIS
4
3
Reserved
Reserved
0
0
RW Reserved
RW Reserved
Buck2 active output discharge.
RW 0 : Disable
1 : Enable (default)
BUCK2_
DIS
2
1
0x0B DISCHARGE
Boost registers keep and reset control. Self reset
function: it can recover to 0 when set 1 :
0 : Keep Boost relative Reg value Register0x05[7],
0x05[5:2], 0x08[7:0], 0x0A[5], 0x0A[0], 0x14[3:2],
0x37[5], 0x37[3:2] Boost relative bits. (default)
1 : Boost relative Reg recover to default value.
When HWEN OFF and BCTRL = 0 (default), Boost
keeps relative Reg.
When HWEN ON and BCTRL = 1, Boost recover to
default value. BCTRL become 0 automatically,
Boost relative Reg is kept.
When HWEN ON and BCTRL = 0, Boost relative
can be written normally.
1
BCTRL
0
0
WC
When write 1 then it will recover to 0.
0
Reserved
RW Reserved
Addr
RegName
Bit
BitName
Default Type
Description
Buck output voltage can be set default voltage from
0.8V to 3.3V with 12.5mV/step.
00000000 : 0.6V
00000001 : 0.6125V
…
00101000 : 1.1V (default)
…
Buck_Vout
[7:0]
0x0C Buck_Vout
7:0
00101000 RW
11010111 : 3.2875V
11011000 : 3.3V
…
11111111: 3.3V
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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43
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO1 output voltage can be set default voltage from
0.6V to 3.775V with 25mV/step.
0000000 : 0.6V
0000001 : 0.625V
…
1011000 : 2.8V (default)
…
LDO1_
Vout[6:0]
7:1
1011000
RW
0x0D LDO1_Vout
1111110 : 3.75V
1111111 : 3.775V
0
Reserved
0
RW Reserved
Addr
RegName
Bit
BitName
Default Type
Description
LDO2 output voltage can be set default voltage
from 0.6V to 3.775V with 25mV/step.
0000000 : 0.6V
0000001 : 0.625V
…
1011000 : 2.8V (default)
…
LDO2_
Vout[6:0]
7:1
1011000
RW
0x0E LDO2_Vout
1111110 : 3.75V
1111111 : 3.775V
0
Reserved
0
RW Reserved
Addr
RegName
Bit
BitName
Default Type
Description
LDO3 output voltage can be set default voltage from
0.6V to 3.775V with 25mV/step.
0000000 : 0.6V
0000001 : 0.625V
…
0110000 : 1.8V (default)
…
LDO3_
Vout[6:0]
7:1
0110000
RW
0x0F LDO3_Vout
1111110 : 3.75V
1111111 : 3.775V
0
Reserved
0
RW Reserved
Addr
RegName
Bit
BitName
Default Type
Description
LDO4 output voltage can be set default voltage from
0.6V to 3.775V with 25mV/step.
0000000 : 0.6V
0000001 : 0.625V
…
0110000 : 1.8V (default)
…
LDO4_
Vout[6:0]
7:1
0
0110000
RW
0x10 LDO4_Vout
1111110 : 3.75V
1111111 : 3.775V
Reserved
0
RW Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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44
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Boost output voltage can be set default voltage from
4.5V to 5.5V with 25mV/step.
000000 : 4.5V
000001 : 4.525V
…
RW 010100: 5.0V (default)
Boost_
Vout[5:0]
7:2
010100
…
100111: 5.475V
101000: 5.5V
…
0x11 Boost_Vout
111111: 5.5V
Voltage scaling slew rate for LDO.
00 : 100mV/s
RW 01 : 50mV/s (default)
10 : 25mV/s
1:0
LDO_SS
01
11 : 12.5mV/s
Addr
RegName
Bit
BitName
Default Type
Description
Buck2 output voltage can be set default voltage from
0.6V to 3.3V with 12.5mV/step.
00000000 : 0.6V
00000001 : 0.6125V
…
Buck2_
Vout[7:0]
0x12 Buck2_Vout 7:0
10110100 RW 10110100 : 2.85V (default)
…
11010111 : 3.2875V
11011000 : 3.3V
…
11111111: 3.3V
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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45
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck SW on/off speed set. Decrease SW speed can
help the EMI performance.
00 : Slower
01 : Slow (default)
10 : Normal
Buck_SR
[1:0]
7:6
01
01
RW
RW
11 : Fast
Buck2 SW on/off speed set. Decrease SW speed
can help the EMI performance.
00 : Slower
01 : Slow (default)
10 : Normal
Buck2_SR
[1:0]
5:4
0x13
LX_SR
11 : Fast
3
2
Reserved
Reserved
0
0
RW Reserved
RW Reserved
Boost SW on/off speed set. Decrease SW speed
can help the EMI performance.
00 : Fast
01 : Normal
Boost_SR
[1:0]
1:0
10
RW
10 : Slow (default)
11 : Slower
Addr
RegName
Bit
BitName
Default Type
Description
Voltage scaling slew rate for Buck.
00 : 7mV/s
RW 01 : 4mV/s (default)
10 : 2mV/s
BUCK_
DVS
7:6
01
01
01
11 : 1mV/s
Voltage scaling slew rate for LDO.
00 : 36mV/s
RW 01 : 14mV/s (default)
10 : 8.5mV/s
5:4 LDO_DVS
11 : 4mV/s
0x14
DVS
Voltage scaling slew rate for Boost.
00 : 32mV/s
RW 01 : 15mV/s (default)
10 : 8mV/s
BOOST_
3:2
DVS
11 : 4mV/s
1
0
Reserved
INT_CLS
0
0
RW Reserved
Interrupt clear pin.
0 : Normal operation (default)
1 : Refresh interrupt bits.
WC
(After write “1”, the bit will auto return to “0”.)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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46
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : Buck UV event detected
BUCK_
UV_EVT
7
0
0
0
0
0
0
0
0
RC
RC
RC
RC
RC
RC
RC
RC
LDO1 under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO1 UV event detected
LDO1_
UV_EVT
6
5
4
3
2
1
0
LDO2 under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO2 UV event detected
LDO2_
UV_EVT
LDO3 under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO3 UV event detected
LDO3_
UV_EVT
0x15
UV_EVT
LDO4 under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO4 UV event detected
LDO4_
UV_EVT
Boost under-voltage threshold sense
acknowledgement.(raising trigger)
0 : No fault or be masked (default)
1 : Boost UV event detected
BOOST_
UV_EVT
Buck2 under-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : Buck2 UV event detected
BUCK2_
UV_EVT
Boost SCP (VOUT < 0.7V) or VDS protect (VIN –
VOUT > 300mV) or IL > 5A internal Boost FAULT
0 : Not fault or be masked (default)
BOOST_
FAULT_
EVT
1 : Boost fault event detected
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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47
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : Buck OV event detected
BUCK_
OV_EVT
7
0
0
0
0
0
0
RC
RC
RC
RC
RC
RC
RC
LDO1 over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO1 OV event detected
LDO1_
OV_EVT
6
5
4
3
2
LDO2 over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO2 OV event detected
LDO2_
OV_EVT
LDO3 over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO3 OV event detected
LDO3_
OV_EVT
0x16
OV_EVT
LDO4 over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : LDO4 OV event detected
LDO4_
OV_EVT
Boost over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : Boost OV event detected
BOOST_
OV_EVT
Buck2 over-voltage threshold sense
acknowledgement. (raising trigger)
0 : No fault or be masked (default)
1 : Buck2 OV event detected
BUCK2_
OV_EVT
1
0
0
0
Reserved
RC Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
48
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Buck OCP event detected
BUCK_
OCP_EVT
7
0
0
0
0
0
0
RC
RC
RC
RC
RC
RC
RC
LDO1 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO1 OCP event detected
LDO1_
OCP_EVT
6
5
4
3
2
1
LDO2 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO2 OCP event detected
LDO2_
OCP_EVT
LDO3 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO3 OCP event detected
LDO3_
OCP_EVT
0x17
OCP_EVT
LDO4 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO4 OCP event detected
LDO4_
OCP_EVT
Boost over-current protection acknowledgement.
(raising trigger )
0 : No fault or be masked (default)
1 : Boost OCP event detected
BOOST_
OCP_EVT
Buck2 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Buck2 OCP event detected
BUCK2_
OCP_EVT
0
0
0
Reserved
RC Reserved
Addr
RegName
Bit
BitName
Default Type
Description
Thermal warning sense acknowledgement.
(raising/falling trigger)
0 : No fault or be masked (default)
1 : Thermal warning event detected
TWARN_
EVT
7
6
5
4
0
0
0
RC
RC
RC
RC
Thermal shutdown sense acknowledgement.
(raising/falling trigger)
0 : No fault or be masked (default)
1 : Thermal shutdown event detected
TSD_EVT
VSYS under-voltage sense acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Under-voltage event detected
0x19 BASE_EVT
VSYSUV_
EVT
VSYS over-voltage sense acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Over-voltage event detected
VSYSOV_
EVT
0
3:0 Reserved
0000
RC Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
49
RT5112A
Addr
RegName
Bit BitName
Default Type
Description
Chip revision
00000000 : 1st Version
00000001 : 2nd Version
00000010 : 3rd Version
00000011 : 4th Version (default)
...
0x2A Revision ID 7:0
RID[7:0] 00000011
R
11111111 : 256th Version
Addr
RegName
Bit BitName
Default Type
Description
Buck under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BUCK_UV
_STAT
7
0
0
0
0
0
0
0
R
R
R
R
R
R
R
LDO1 under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO1_UV
_STAT
6
LDO2 under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO2_UV
_STAT
5
LDO3 under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO3_UV
_STAT
4
LDO4 under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
0x2B
UV_STAT
LDO4_UV
_STAT
3
Boost under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BOOST_
2
UV_STAT
Buck2 under-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BUCK2_
1
UV_STAT
Boost SCP (VOUT < 0.7V) or VDS protect (VIN –
VOUT > 300mV) or IL > 5A internal boost FAULT
status.
0 : No fault occurs (default)
1 : Fault occurs
BOOST_
FAULT_
STAT
0
0
R
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
50
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BUCK_OV
_STAT
7
0
0
0
0
0
0
R
R
R
R
R
R
LDO1 over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO1_OV
_STAT
6
5
4
3
2
LDO2 over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO2_OV
_STAT
LDO3 over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO3_OV
_STAT
0x2C
OV_STAT
LDO4 over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
LDO4_OV
_STAT
Boost over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BOOST_
OV_STAT
Buck2 over-voltage threshold sense status.
0 : No fault occurs (default)
1 : Fault occurs
BUCK2_
OV_STAT
1
0
0
0
R
R
Reserved
Reserved
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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51
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
BUCK_
OCP_
STAT
Buck over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
7
0
0
0
0
0
0
R
R
R
R
R
R
LDO1_
OCP_
STAT
LDO1 over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
6
5
4
3
2
LDO2_
OCP_
STAT
LDO2 over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
LDO3_
OCP_
STAT
LDO3 over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
0x2D OCP_STAT
LDO4_
OCP_
STAT
LDO4 over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
BOOST_
OCP_
STAT
Boost over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
BUCK2_
OCP_
STAT
Buck2 over-current protection status.
0 : No fault occurs (default)
1 : Fault occurs
1
0
0
0
R
R
Reserved
Reserved
Addr
RegName
Bit
7
BitName
Default Type
Description
Thermal warning sense status.
0 : No fault occurs (default)
1 : Fault occurs
TWARN_
STAT
0
0
0
0
R
R
R
R
Thermal shutdown sense status.
0 : No fault occurs (default)
1 : Fault occurs
TSD_
STAT
6
5
4
3
VSYS under-voltage sense status.
0 : No fault occurs (default)
1 : Fault occurs
VSYSUV_
STAT
0x2F BASE_STAT
VSYS over-voltage sense status.
0 : No fault occurs (default)
1 : Fault occurs
VSYSOV_
STAT
It indicates status of the internal SEQ_ON signal.
0 : SEQ OFF (default)
SEQ_ON
0
R
R
1 : SEQ ON
2:0 Reserved
000
Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
52
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Indicate Buck final enable status.
0 : Disable (default)
1 : Enable
BUCK_EN
_FLG
7
0
0
0
0
0
0
R
R
R
R
R
R
Indicate LDO1 final enable status.
0 : Disable (default)
1 : Enable
LDO1_EN
_FLG
6
5
4
3
2
Indicate LDO2 final enable status.
0 : Disable (default)
1 : Enable
LDO2_EN
_FLG
Indicate LDO3 final enable status.
0 : Disable (default)
1 : Enable
LDO3_EN
_FLG
0x30
EN_FLG
Indicate LDO4 final enable status.
0 : Disable (default)
1 : Enable
LDO4_EN
_FLG
Indicate BOOST final enable status.
0 : Disable (default)
1 : Enable
BOOST_
EN_FLG
Indicate Buck2 final enable status.
0 : Disable (default)
1 : Enable
BUCK2_
EN_FLG
1
0
0
0
R
R
Reserved
Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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53
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck under-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BUCK_UV
_MASK
7
0
0
0
0
0
0
0
LDO1 under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO1_UV
_MASK
6
5
4
3
2
1
LDO2 under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO2_UV
_MASK
LDO3 under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO3_UV
_MASK
LDO4 under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
0x32
UV_MASK
LDO4_UV
_MASK
Boost under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BOOST_
UV_MASK
Buck2 under-voltage threshold sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BUCK2_
UV_MASK
Boost SCP (VOUT < 0.7V) or VDS protect (VIN –
VOUT > 300mV) or IL > 5A internal boost FAULT
RW mask.
BOOST_
FAULT_
MASK
0
0
0 : Interrupt is not masked (default)
1 : Interrupt is masked
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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54
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck over-voltage threshold mask.
BUCK_
OV_MASK
7
0
0
0
0
0
0
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO1 over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO1_OV
_MASK
6
5
4
3
2
LDO2 over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO2_OV
_MASK
LDO3 over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO3_
OV_MASK
0x33 OV_MASK
LDO4 over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO4_
OV_MASK
Boost over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BOOST_
OV_MASK
Buck2 over-voltage threshold mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BUCK2_
OV_MASK
1
0
0
0
Reserved
RW Reserved
Addr
RegName
Bit
7
BitName
Default Type
Description
BUCK_
OCP_
MASK
Buck over-current protection mask.
0
0
0
0
0
0
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO1_
OCP_
MASK
LDO1 over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
6
5
4
3
2
LDO2_
OCP_
MASK
LDO2 over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
LDO3_
OCP_
MASK
LDO3 over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
0x34 OCP_MASK
LDO4_
OCP_
MASK
LDO4 over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BOOST_
OCP_
MASK
Boost over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
BUCK2_
OCP_
MASK
Buck2 over-current protection mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
1
0
0
0
Reserved
RW Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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55
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Thermal warning sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
TWARN_
MASK
7
0
0
0
Thermal shutdown sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
TSD_
MASK
6
5
4
BASE_
MASK
VSYS under-voltage sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
0x36
VSYSUV_
MASK
VSYS over-voltage sense mask.
RW 0 : Interrupt is not masked (default)
1 : Interrupt is masked
VSYSOV_
MASK
0
3:0 Reserved
0000
RW Reserved
Addr
RegName
Bit
BitName
Default Type
Description
Buck Hiccup or latch off mode selection after
current limit.
RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off
mode. Hiccup on/off time = 4ms / 8ms) (default)
1 : Latch-off mode.
BUCK_OC
_LATCH
7
0
0
LDO Hiccup or latch off mode selection after
current limit.
RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off
mode. Hiccup on/off time = 2ms/40ms) (default)
1 : Latch-off mode.
LDO_OC_
LATCH
6
BOOST Hiccup or latch off mode selection after
current limit.
RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off
mode, hiccup on/off time = 10ms/100ms) (default)
1 : Latch-off mode.
0x37
CHx_PT
BOOST_
OC_
LATCH
5
4
0
0
Reserved
RW Reserved
Boost UV deglitch time selection :
00 : 10s
RW 01 : 15s
BST_UV_
DT[1:0]
3:2
11
00
10 : 25s
11: 50s (default)
1:0 Reserved
RW Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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56
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck UV deglitch time selection :
00 : 5s
RW 01 : 10s
Buck_UV_
DT[1:0]
7:6
11
11
11
10 : 15s
11 : 50s (default)
Buck OV deglitch time selection :
00 : 10s
RW 01 : 15s
Buck_OV_
DT[1:0]
5:4
3:2
1:0
10 : 20s
11 : 50s (default)
CHx_deglitch
time
0x38
LDO UV deglitch time selection :
00 : 10s
RW 01 : 15s
LDO_UV_
DT[1:0]
10 : 30s
11 : 50s (default)
LDO OV deglitch time selection :
00 : 5s
RW 01 : 10s
LDO_OV_
DT[1:0]
11
10 : 25s
11 : 50s (default)
Addr
RegName
Bit
BitName
Default Type
Description
VSYSUV deglitch time selection :
00 : 70s
RW 01 : 135s
VSYSUV_
DT[1:0]
7:6
11
10
10 : 265s
11 : 525s (default)
VSYSOV deglitch time selection:
00 : 20s
RW 01 : 50s
VSYSOV_
DT[1:0]
5:4
10 : 180s (default)
11 : 360s
BASEPT_
deglitch time
0x39
VSYSOV turn off Buck
RW 0 : When Vsys_OV occur will turn off BCK (default)
1 : When Vsys_OV occur will not turn off BCK
VSYSOV_
PT
3
2
0
0
NFC load detection. 0x05[6] must set 0 when bit
BST_NFC_force = 1.
0 : AUTO NFC (default)
BST_NFC
_Force
RW
1 : FCCM by load, turn off NFC
1
0
Reserved
Reserved
0
0
RW Reserved
RW Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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57
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
It indicates the states of power on sequence
00 : SEQ_ON hasn't started or needless (default)
01 : SEQ_ON is carrying out (During SLOT1 to
SLOT8 + 4ms)
10 : There are fail soft-start channels during power
on sequence
SEQ_ON_
STAT[1:0]
7:6
00
R
11 : SEQ_ON has completed
It indicateds the fault SLOT during power on
sequence at SEQ_ON_STAT = 2'b10
000 : SLOT1 (default)
001 : SLOT2
010 : SLOT3
011 : SLOT4
100 : SLOT5
101 : SLOT6
110 : SLOT7
111 : SEQ_ON has completed
0x3A
SEQ_ON
SEQ_
COUNT
[2:0]
5:3
000
000
R
R
2:0 Reserved
Reserved
Addr
RegName
Bit
BitName
Default Type
Description
It indicates Buck soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
BCK
7
0
0
0
0
0
0
R
R
R
R
R
R
It indicates LDO1 soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
LDO1
6
5
4
3
2
It indicates LDO2 soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
LDO2
It indicates LDO3 soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
LDO3
0x3B SSEND_CHx
It indicates LDO4 soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
LDO4
It indicates Boost soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
BST
It indicates Buck2 soft-start end or not
0 : Not soft-start end (default)
1 : Soft-start end
sSSEND_
BCK2
1
0
0
0
R
R
Reserved
Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
www.richtek.com
58
DS5112A-02 August 2019
RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
7:6 Reserved
00
RW Reserved
Interrupt reflash pulse width timing.
00 : disable (default)
RW 01 : 2s
INT_DEG[
5:4
00
1:0]
10 : 4s
11 : 8s
Indicate PMU's State
0000 : IDLE (default)
0x42
INT_SET
0001 : ONSEQ (slot1 to slot7 + 4ms, when 4ms
clock end will tigger ONSEQ_END)
0010 : ONSEQ_END
SEQ_STA
3:0
0000
R
T[2:0]
0011 : ENSEQ
0100 : OFFSEQ
0101 : OFFSEQ_END (slot7 to slot1, when slot1
sequence end will tigger OFFSEQ_END)
1111 : Else
Addr
RegName
Bit
BitName
Default Type
Description
BST latch off (BSTEN)
0 : Release (default)
1 : Latch off
BST latch off (HWEN)
0 : Release (default)
1 : Latch off
BCK1 latch off
0 : Release (default)
1 : Latch off
BCK2 latch off
0 : Release (default)
1 : Latch off
PMU_
STAT
0x43 PMU_STAT 7:0
00000000
R
LDO1 latch off
0 : Release (default)
1 : Latch off
LDO2 latch off
0 : Release (default)
1 : Latch off
LDO3 latch off
0 : Release (default)
1 : Latch off
LDO4 latch off
0 : Release (default)
1 : Latch off
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
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59
RT5112A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Thermal Considerations
Four-Layer PCB
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
0
25
50
75
100
125
Ambient Temperature (°C)
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
Figure 10. Derating Curve of Maximum PowerDissipation
Layout Considerations
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a WL-
CSP-25B 2.2x2.3 (BSC) package, the thermal resistance,
θJA, is 31.5°C/W on a standard JEDEC 51-7 high effective-
thermal-conductivity four-layer test board. The maximum
power dissipation at TA = 25°C can be calculated as below
:
The PCB layout is an important step to maintain the high
performance of the RT5112A. Both the high current and
the fast switching nodes demand full attention to the PCB
layout to keep the robustness of the RT5112A through
the PCB layout. Improper layout might lead to the
symptoms of poor line or load regulation, ground and output
voltage shifts, stability issues, unsatisfying EMI behavior
or worsened efficiency. For the best performance of the
RT5112A, the following PCB layout guidelines must be
strictly followed.
PD(MAX) = (125°C − 25°C) / (32.7°C/W) = 3.05W for a WL-
CSP-25B 2.2x2.3 (BSC) package.
The trace from switching node to inductor should be as
short as possible to minimized the switching loop for
better EMI.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 10 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Place the input and output capacitors close to the input
and output pins respectively for good filtering.
Keep the main power traces as wide and short as
possible.
Connect the AGND, DGND, GNDB1 and GNDB2 to a
strong ground plane for maximum thermal dissipation
and noise protection.
Directly connect the Buck output capacitors to the
feedback network to avoid bouncing caused by parasitic
resistance and inductance from the PCB trace.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
60
DS5112A-02 August 2019
RT5112A
Bottom
Layer
TOP Layer
3rd Layer
GND
VOUT_BUCK1
VIN_VIN4
C12
C8
C2
VIN_VIN3
VOUT_LDO4
L1
LDO4
VIN4
FB2
LXB1
C10
GNDB1
FB1
C1
C3
VIN3
C9
LDO3
AGND
LDO2
LDO1
HWEN
DGND
SDA
VINB1
VINB2
VIN_B1
VIN_B2
VOUT_LDO3
VSYS
REF
NC
VOUT_LDO2
C7
INTRB
LXB2
LXB2
VIN12
SCL
GNDB2
C6
VOUT_LDO1
L2
C5
C13
C4
C11
VIN_VIN12
VOUT_BUCK2
Figure 11. PCB Layout Guide
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
61
RT5112A
Outline Dimension
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
0.500
0.170
0.240
2.260
Max
0.600
0.230
0.300
2.340
Min
0.020
0.007
0.009
0.089
Max
0.024
0.009
0.012
0.092
A
A1
b
D
D1
E
1.600
0.063
2.160
2.240
0.085
0.088
E1
e
1.600
0.400
0.063
0.016
25B WL-CSP 2.2x2.3 Package (BSC)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
62
DS5112A-02 August 2019
RT5112A
Footprint Information
Footprint Dimension (mm)
Number of
Pin
Package
Type
Tolerance
±0.025
e
A
B
NSMD
SMD
0.240
0.270
0.340
0.240
WL-CSP2.2x2.3-25(BSC)
25
0.400
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS5112A-02 August 2019
www.richtek.com
63
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