RT5112_技术文档

®

RT5112

Smart Power-Management Integrated Circuit for Camera

Module Application

General Description

Features

The RT5112 device is a smart power management IC

which includes a low-quiescent-current HCOT Buck

converter, a ACOT Boost converter and four high PSRR

low dropout regulators (LDO). One can control the channel

power sequence, output voltage level andDVS slew rate

by setting registers via I²C interface. The output voltage

OVP/UVP, OCP and OTP protection are built in the

RT5112. The RT5112 is available in a WL-CSP-25B

2.2x2.3 (BSC) package.

System Control

 Hardware Enable Pin

 I²C Controlled Interface

 Programmable Channel Power Sequence

 IRQ Output for Indication

 Over-Voltage Protection

 Under-Voltage Protection

 Over-Current Protection

 Over-Temperature Protection

 Available in a WL-CSP-25B 2.2x2.3 (BSC) Package

Applications

High Efficiency Buck Converter

^Wide 2.5V to 5.5V Operating Input Range

^Programmable Output Voltage from 0.6V to 3.3V

with 12.5mV/Step

 Camera Module

 Optical Module

 SSD

^Maximum Continuous Load Current : 1.2A

^HCOT Control Operation

Ordering Information

RT5112

^Low Quiescent Current

Flexible Boost Converter

Package Type

WSC : WL-CSP-25B 2.2x2.3 (BSC)

 Wide 2.5V to 4.4V Operating Input Range

 Programmable Output Voltage from 4.5 V to 5.5V

with 25mV/Step

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

 Maximum Continuous Load Current : 1A

 ACOT Control Operation

 Low Quiescent Current

Four Low Dropout Regulators

 Wide 1.9V to 5.5V Operating Input Range

 Programmable Output Voltage from 0.6V to 3.775V

with 25mV/Step

 High PSRR : 70dB @ 1kHz, 40dB @ 100kHz with

LDO1 / LDO2

 High PSRR : 50dB @ 1kHz, 40dB @ 10kHz with LDO3

/ LDO4

 300mA Low Dropout Voltage Regulators

 Low Quiescent Current

©

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RT5112

Marking Information

Pin Configuration

(TOP VIEW)

1D : Product Code

YMDNN : Date Code

1D YM

DNN

A1

A2

A3

A4

A5

LXB VINB BSTVOUT LXBSTLXBST

B1

GNDB FB1 BSTEN INTRB

C1 C2 C3 C4

NC HWEN DGND SDA

D1 D2 D3 D4

B2

B3

B4

B5

GND

BST

C5

SCL

D5

VIN4 VIN3 VSYS REF VIN12

E1 E2 E3 E4 E5

LDO4 LDO3 AGND LDO2 LDO1

WL-CSP-25B 2.2 x 2.3 (BSC)

Typical Application Circuit

L2

0.47µH

V

3.8V

RT5112

IN_B

A4, A5

A3

LXBST

V

C1

10µF

IN_BST

3.8V

A2

A1

VINB

LXB

1.2A Buck

1A Boost

C3

L1

1µH

BSTVOUT

V

10µF

OUT_BST

V

OUT_BUCK

0.6V to 3.3V

Driver

&

Control

Driver

&

Control

4.5V to 5.5V

C4

22µF

B2

B1

FB1

C2

B5

GNDBST

10µF

GNDB

V

D3 VSYS

B4 INTRB

HWEN C2

BSTEN B3

IN_SYS

3.8V

R1

Control Logic

C13

1µF

V

3.8V

IN_B

2.2K

C5 SCL

E5

LDO1

2

300mA LDO1

Driver &

Control

V

OUT_LDO1

I C

BUS

2

I C

C4

SDA

0.6 to 3.775V

C6

2.2µF

VIN12 D5

V

IN_VIN12

3.8V

2.2µF

C5

300mA LDO2

Driver &

Control

E4

LDO2

V

OUT_LDO2

C7 0.6 to 3.775V

2.2µF

LDO3 E2

300mA LDO3

V

OUT_LDO3

C9 0.6 to 3.775V

2.2µF

Driver &

Control

VIN3 D2

VIN4 D1

V

IN_VIN3

C8 3.8V

2.2µF

V

D4 REF

Ref

C11

10nF

IN_VIN4

300mA LDO4

Driver &

Control

3.8V

C12

2.2µF

LDO4 E1

V

OUT_LDO4

0.6 to 3.775V

C10

2.2µF

AGND

E3

DGND

C3

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DS5112-03 August 2019

RT5112

Component List of Evaluation Board

Reference

Qty

1

Part Number

JMK105CBJ106MV-F

JMK107BBJ226MA-T

JMK105BJ225KV-F

GRM033R60J225ME47D

LMK105BJ103KV-F

LMK063BBJ105MPLF

MEKK2016T1R0M

Description

10F/X5R/6.3V

22F/X5R/6.3V

2.2F/X5R/6.3V

10nF/X5R/6.3V

1F/X5R/10V

Package

0402

0603

0402

0201

0402

0201

2016

2012

Manufacturer

TAIYO YUDEN

MURATA

C1, C2, C3

C4

1

C5, C8, C12

1

C6, C7, C9, C10

1

C11

C13

L1

1

TAIYO YUDEN

MURATA

1

1H/3.1A/50m

L2

1

DFE201210S-R47MH=P2 0.47H/3.4A/32m

Functional Pin Description

Pin No.

Pin Name

Pin Function

A1

LXB

Buck switch output. Connect this pin to an inductor with a wide PCB trace.

Supply voltage input of Buck. The IC operates from a 2.5V to 5.5V input rail. It

requires a 10F decouple ceramic capacitor. Connect this pin to input voltage

with a wide PCB trace.

A2

A3

VINB

Boost output pin. PCB trace length from BSTVOUT to the output filter capacitor

should be as short and wide as possible. It requires a 22F decouple ceramic

capacitor. BSTVOUT is completely disconnected from LXBST when Boost is at

off state.

BSTVOUT

LXBST

Boost switch output. Connect this pin to an inductor with a wide PCB trace and

keep the PCB trace length as short and wide as possible to reduce EMI and

voltage spike.

A4, A5

B1

B2

B3

GNDB

FB1

Buck power ground.

Feedback of Buck. Directly connect the Buck’s output to this pin.

Boost enable control input.

BSTEN

Interrupt output. Open drain output. When interrupt happens, interrupt pin is

pulled down.

B4

INTRB

B5

C1

C2

C3

C4

C5

D1

D2

GNDBST

NC

Boost power ground.

NC internal connection and should keep floating state.

Chip enable control input.

HWEN

DGND

SDA

Digital ground.

I²C data pin.

I²C clock signal input.

SCL

VIN4

LDO4 power supply input. It requires a 2.2F decouple ceramic capacitor.

LDO3 power supply input. It requires a 2.2F decouple ceramic capacitor.

VIN3

System analog power supply. It requires a 1F decouple ceramic capacitor. It

also connected to V_INBexternally.

D3

VSYS

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RT5112

Pin No.

Pin Name

REF

Pin Function

D4

Internal reference output. It requires a 10nF decouple ceramic capacitor.

LDO1 and 2 power supply input. It requires a 2.2F decouple ceramic

capacitor.

D5

VIN12

E1

E2

E3

E4

E5

LDO4

LDO3

AGND

LDO2

LDO1

LDO4 output. It requires a 2.2F decouple ceramic capacitor.

LDO3 output. It requires a 2.2F decouple ceramic capacitor.

Analog ground.

LDO2 output. It requires a 2.2F decouple ceramic capacitor.

LDO1 output. It requires a 2.2F decouple ceramic capacitor.

Functional Block Diagram

LXBST

1.2A Buck

1A Boost

VINB

LXB

BSTVOUT

Driver

&

Control

Driver

&

Control

FB1

GNDBST

GNDB

HWEN

BSTEN

VSYS

Control Logic

INTRB

300mA LDO1

Driver &

Control

SCL

SDA

2

LDO1

VIN12

I C

300mA LDO2

Driver &

Control

LDO2

LDO3

VIN3

VIN4

300mA LDO3

Driver &

Control

Ref

REF

300mA LDO4

Driver &

Control

LDO4

AGND

DGND

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DS5112-03 August 2019

RT5112

Absolute Maximum Ratings (Note 1)

 VSYS, VINB, VIN12, VIN3, VIN4, BSTVOUT, LDO1, LDO2, LDO3,

LDO4, FB1, REF, SCL, SDA, HWEN, BSTEN, INTRB, LXB, LXBST ------------------------------- −0.3V to 6.5V

 LXB, LXBST (< 20ns) --------------------------------------------------------------------------------------------- −2V to 9V

 PowerDissipation, P_D@ T_A= 25°C

WL-CSP-25B 2.2x2.3 (BSC) ----------------------------------------------------------------------------------- 3.05W

 Package Thermal Resistance (Note 2)

WL-CSP-25B 2.2x2.3 (BSC), θ_JA------------------------------------------------------------------------------ 32.7°C/W

 Junction Temperature --------------------------------------------------------------------------------------------- 150°C

 Lead Temperature (Soldering, 10 sec.)----------------------------------------------------------------------- 260°C

 Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Supply Voltage V_{IN_B}, V_SYS------------------------------------------------------------------------------------- 2.5V to 5.5V

 Supply Voltage V_{IN_BST}------------------------------------------------------------------------------------------- 2.5V to V_{OUT_BST}- 0.1V

 Supply Voltage V_{IN_VIN12}, V_{IN_VIN3}, V_{IN_VIN4}---------------------------------------------------------------- 1.9V to 5.5V

 Junction Temperature Range------------------------------------------------------------------------------------ −40°C to 125°C

 Ambient Temperature Range------------------------------------------------------------------------------------ −40°C to 85°C

Electrical Characteristics

(T_A= 25°C, unless otherwise specified.)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

System Parameter

HWEN = BSTEN = H, V_{IN_SYS}

=

V_{IN_B}= V_{IN_BST}= V_{IN_VIN12}

=

--

138

106

I_QTATOL

V_{IN_VIN3}= V_{IN_VIN4}= 3.8V,

LDO/Buck/Boost on, no load,

automode 40°C to 85°C

HWEN = H, V_{IN_SYS}= V_{IN_VIN12}

--

118

10

95

7

Quiescent Current

I_QLDO

A

= V_{IN_VIN3}= V_{IN_VIN4}= 3.8V,

LDO on, no load, automode

HWEN = H, V_{IN_SYS}= V_{IN_B}

3.8V, all power regulators are off

=

I_QBASE

HWEN = L, BSTEN = H, V_{IN_SYS}

12

20

I_QBOOST

= V_{IN_B}= V_{IN_BST}= 3.8V, only

Boost active, no load, automode

Leak current, HWEN = BSTEN =

L, V_{IN_SYS}= V_{IN_B}= V_{IN_BST}

_{IN_VIN12}= V_{IN_VIN3}= V_{IN_VIN4}

2.5V to 5.5V, 40°C to 85°C

=

Leakage Current

--

1.5

A

I_LEAK

V

=

V_SYSUnder-Voltage

Lockout Threshold Rising

UVLO

2.35

2.45

V

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RT5112

Parameter

Symbol

UVLO_H

Test Conditions

Min

Typ

Max

Unit

Hysteresis Voltage of

UVLO

--

100

--

mV

HWEN and BSTEN Control

HWEN and BSTEN Low

Level Input Voltage

--

1.2

--

1

0.4

--

V

V_IL

HWEN and BSTEN High

Level Input Voltage

V_IH

HWEN and BSTEN Pull

Down Resistor

-

M

R_EN

Step Down Buck Converter (V_{IN_B}= 3.8V, C1 = C2 = 10F, L1 = 1H)

Input Voltage Range

Output Voltage Range

Output Voltage Step

2.5

0.6

--

5.5

3.3

--

V

V_{IN_B}

V_{OUT_BUCK}

12.5

mV

All output range of V_{OUT_BUCK}

,

Output Voltage Accuracy

Switching Frequency

--

2

%

2

2

V_{OUT_ACC_BUCK}

I_OUT= I_OUT(MAX)

V_{OUT_BUCK}= 1.1V, operating

2.5

3

MHz

m

f_{SW_BUCK}

under CCM

P-Channel MOSFET On

Resistance

From VINB pin to LXB pin

--

150

200

R_{ON_HG_BUCK}

N-Channel MOSFET On

Resistance

From LXB pin to GNDB pin

--

70

--

140

100

140

m

%

R_{ON_LG_BUCK}

D_{MAX_BUCK}

R_{DIS_BUCK}

Maximum Duty Cycle

Output Discharge

Resistor

80

100

V_{OUT_}



Over-Voltage Rising

Threshold Detection

--

0

--

V

OVP_{_R_BUCK}

OVP_{_F_BUCK}

UVP_{_R_BUCK}

UVP_{_F_BUCK}

I_{FB_LK}

BUCK

x 120%

V_{OUT_}

Over-Voltage Falling

Threshold Detection

BUCK

x 109%

V_{OUT_}

Under-Voltage Rising

Threshold Detection

--

V

BUCK

x 92%

V_{OUT_}

Under-Voltage Falling

Threshold Detection

--

V

BUCK

x 80%

Buck disable, 0x0B[7] = 0 (Buck

discharge disable), V_{IN_B}= 5.5V,

V_LXB= 5.5V, V_FB1= 5.5V

FB1 Leakage Current

50

--

100

nA

Buck disable, 0x0B[7] = 0 (Buck

discharge disable), V_{IN_B}= 5.5V,

V_LXB= 0 or 5.5V

Switch Leakage Current

0

1

A

I_{LXB_LK}

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RT5112

Parameter

Symbol

I_{CL_peak_BUCK}

I_{CL_valley_BUCK}

Test Conditions

V 5.5V

Min

1.5

1

Typ

2

Max

2.5

2

Unit

A

2.5V

UG Peak Current Limit

LG Valley Current Limit



^IN_B

1.5

A

V_{IN_B}= 3.6V

LG Negative Current

Limit

0.5

--

3

A

I_{NCL_NEG_BUCK}

V_{IN_B}= 3.6V, CCM

Minimum On Time

Minimum Off Time

167

20

200

40

250

60

ns

t_{MIN_ON_BUCK}

t_{MIN_OFF_BUCK}

V_{IN_B}= 3.6V, V_{OUT_BUCK}= 1.8V

V_{IN_B}= V_{OUT_BUCK}= 3.3V

Step Up Boost Converter (V_{IN_BST}= 3.8V, C3 = 10F, C4 = 22F, L2 = 0.47H)

Input Voltage Range

Output Voltage Range

Output Voltage Step

2.5

4.5

--

5

4.4

5.5

--

V

V_{IN_BST}

V_{OUT_BST}

25

mV

DC Output Voltage

Accuracy

All output range of V_{OUT_BST}

_OUT= I_OUT(MAX)

,

--

3

2

%

MHz

A

2

2

V_{OUT_ACC_BST}

f_{SW_BST}

I_{SHDN_BST}

I

V_{OUT_BST}= 5V, operating under

CCM

Switching Frequency

Shutdown Current

3.6

0.5

1.5

120

130

140

HWEN = BSTEN = 0V, from

--

V_{IN_BST}to GND

BSTEN = 0, V_{OUT_BST}= 5V, from

V_{OUT_BST}to GND, 0x0B[5] = 0

Reverse Leakage Current

--

A

m



I_{LEAK_BST}

P-Channel MOSFET On

Resistance

From LXBST pin to BSTOUT pin

From LXBST pin to PGND pin

--

95

100

R_{ON_HG_BST}

R_{ON_LG_BST}

R_{DIS_BST}

N-Channel MOSFET On

Resistance

--

Output Discharge

Resistor

60

100

V_{OUT_}

Over-Voltage Rising

Threshold Detection

--

V

OVP_{_R_BST}

OVP_{_F_BST}

UVP_{_R_BST}

BST

x 117%

V_{OUT_}

Over-Voltage Falling

Threshold Detection

BST

x 106%

V_{OUT_}

Under-Voltage Rising

Threshold Detection

BST

x 92.3%

V_{OUT_}

Under-Voltage Falling

Threshold Detection

--

V

nA

A

UVP_{_F_BST}

BST

x 80%

BSTEN = 0V, V_{IN_BST}= V_{LX_BST}

= 5.5V, V_{OUT_BST}= 0V

Switch Leakage Current

100

200

I_{LXBST_LK}

V_{IN_BST}= 2.5 to 4.4V, V_{OUT_BST}

4.5V to 5.5V

=

--

0.4

0.1

--

I_{LC_BST}

Linear Charge Current

Limit

Over OTW protection 120°C

I_{LC_OTW_BST}

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RT5112

Parameter

Symbol

Test Conditions

V_{OUT_BST}= 5V

Min

Typ

Max

Unit

Inductor Valley Current

Limit

2.5

2.8

3.1

A

I_{CL_valley_BST}

Low Dropout Voltage Regulator LDO1 and LDO2 (V_{IN_VIN12}= V_{OUT_LDO1}/V_{OUT_LDO2}+ 1V, V_HWEN= 1.2V, I_OUT

= 1mA, C_IN= 2.2F, C_OUT= 2.2F)

Input Voltage Range

Output Voltage Range

Output Voltage Step

1.9

0.6

--

5.5

3.775

--

V

V_{IN_VIN12}

2.8

25

V_{OUT_LDO1}

/

V_{OUT_LDO2}

mV

I_{OUT_LDO1}

/

Maximum Output Current

300

--

mA

s

I_{OUT_LDO2}

Time from V_{OUT_LDO1}

_{OUT_LDO2}start rising to 90%

nominal value, V_{OUT_LDO1}

_{OUT_LDO2}= 2.8V, no load

All output range of V_{OUT_LDO1}

_{OUT_LDO2}, I_OUT= I_OUT(MAX)

/

V

t_{SS_LDO1}

/

Soft-Start Time

--

150

t_{SS_LDO2}

/

V

DC Output Voltage

Accuracy

V_{OUT_ACC_LDO1}

V_{OUT_ACC_LDO2}

V_{LOAD_REG_LDO1}

V_{LOAD_REG_LDO2}

/

--

2

%

2

V

/

Load Regulation

Line Regulation

0.5

%

0.5

I_OUT= 0 to I_OUT(MAX)

I_OUT= 50mA to 300mA, V_{IN_VIN12}

V_{LINE_REG_LDO1}

/

--

0.5

%

0.5

= 3.0V to 4.4V, V_{OUT_LDO1}

_{OUT_LDO2}= 2.8V

I_OUT= 300mA, V_{OUT_LDO1}

_{OUT_LDO2}= 2.8V

(Note 5)

/

V_{LINE_REG_LDO2}

V

/

V_{DROP_LDO1}

/

Dropout Voltage

--

250

--

mV

V

V_{DROP_LDO2}

Output Discharge

Resistor

R_{DIS_LDO1}

/

10



R_{DIS_LDO2}

V_{OUT_}

/

LDO1

Over-Voltage Rising

Threshold Detection

OVP_{_R_LDO1}

/

--

V

V_{OUT_}

OVP_{_R_LDO2}

LDO2

x 120%

V_{OUT_}

/

LDO1

Over-Voltage Falling

Threshold Detection

OVP_{_F_LDO1}

/

V_{OUT_}

OVP_{_F_LDO2}

LDO2

x 110%

V_{OUT_}

/

LDO1

Under-Voltage Rising

Threshold Detection

UVP_{_R_LDO1}

/

--

V

V_{OUT_}

UVP_{_R_LDO2}

LDO2

x 90%

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RT5112

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_{OUT_}

/

LDO1

Under-Voltage Falling

Threshold Detection

UVP_{_F_LDO1}

/

--

V

V_{OUT_}

UVP_{_F_LDO2}

LDO2

x 80%

--

22

27

1

HWEN = 1.2V, I_OUT= 0mA

HWEN = 0.3V (disable)

Quiescent Current

A

I

_{Q_LDO1}/I_{Q_LDO2}

0.1

Short Circuit Current

Limit

I_{sc_LDO1}

/

360

--

mA

I_{sc_LDO2}

0x01[3:2] = 11 (LDO1 current

limit = 360mA),

0x02[3:2] = 11 (LDO2 current

limit = 360mA)

I_{Limt_LDO1}

/

Current Limit

360

415

470

mA

I_{Limt_LDO2}

Short Protection On

Timer

t_{scp_ON_LDO1}

t_{scp_ON_LDO2}

t_{scp_OFF_LDO1}

t_{scp_OFF_LDO2}

/

--

2

--

ms

Short Protection Off

Timer

/

40

Low Dropout Voltage Regulator LDO3 and LDO4 (V_{IN_VIN3}/V_{IN_VIN4}= V_{OUT_LDO3}/V_{OUT_LDO4}+ 1V, V_HWEN

=

1.2V, I_OUT= 1mA, C_IN= 2.2F, C_OUT= 2.2F)

V_{IN_VIN3}

/

Input Voltage Range

1.9

--

5.5

V

V_{IN_VIN4}

Output Voltage Range

Output Voltage Step

0.6

--

1.8

25

3.775

--

V

V_{OUT_LDO3}

/

V_{OUT_LDO4}

mV

I_{OUT_LDO3}

/

Maximum Output Current

300

--

mA

I_{OUT_LDO4}

Time from V_{OUT_LDO3}

_{OUT_LDO4}start rising to 90%

nominal value, V_{OUT_LDO3}

_{OUT_LDO4}= 1.8V, no load

All output range of V_{OUT_LDO3}

_{OUT_LDO4}, I_OUT= I_OUT(MAX)

/

V

t_{SS_LDO3/}

Soft-Start Time

--

150

s

/

t_{SS_LDO4}

V

DC Output Voltage

Accuracy

V_{OUT_ACC_LDO3}

V_{OUT_ACC_LDO4}

V_{LOAD_REG_LDO3}

V_{LOAD_REG_LDO4}

/

--

2

%

2

V

/

Load Regulation

Line Regulation

0.5

0.5

I_OUT= 0 to I_OUT(MAX)

_OUT= 50mA/300mA, V_{IN_VIN3}

I

/

V_{LINE_REG_LDO3}

/

--

0.5

%

0.5

V

_{IN_VIN4}= 3.0 to 4.4V,

_{OUT_LDO3}/ V_{OUT_LDO4}= 1.8V

V_{LINE_REG_LDO4}

V

I_OUT= 300mA, V_{OUT_LDO3}

_{OUT_LDO4}= 1.8V

(Note 5)

/

V_{DROP_LDO3}

/

Dropout Voltage

--

150

--

mV

V

V_{DROP_LDO4}

Output Discharge

Resistor

R_{DIS_LDO3}

/

10



R_{DIS_LDO4}

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RT5112

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_OUT

/

_LDO3

Over-Voltage Rising

Threshold Detection

OVP_{_R_LDO3}

/

--

V

V_OUT

OVP_{_R_LDO4}

_LDO4

x 120%

V_OUT

/

_LDO3

Over-Voltage Falling

Threshold Detection

OVP_{_F_LDO3}

/

--

V

V_OUT

OVP_{_F_LDO4}

_LDO4

x 110%

V_OUT

/

_LDO3

Under-Voltage Rising

Threshold Detection

UVP_{_R_LDO3}

/

V_OUT

UVP_{_R_LDO4}

_LDO4

x 90%

V_OUT

/

_LDO3

Under-Voltage Falling

Threshold Detection

UVP_{_F_LDO3}

/

V_OUT

UVP_{_F_LDO4}

_LDO4

x 80%

--

22

27

1

HWEN = 1.2V, I_OUT= 0mA

HWEN = 0.3V (disable)

Quiescent Current

A

I

_{Q_LDO3}/I_{Q_LDO4}

0.1

Short Circuit Current

Limit

I_{sc_LDO3}

/

360

--

mA

I_{sc_LDO4}

0x03[3:2] = 11 (LDO3 current limit

= 360mA),

0x04[3:2] = 11 (LDO4 current limit

= 360mA)

I_{Limt_LDO3}

/

Current Limit

360

415

470

mA

I_{Limt_LDO4}

Short Protection On

Timer

t_{scp_ON_LDO3}

t_{scp_ON_LDO4}

t_{scp_OFF_LDO3}

t_{scp_OFF_LDO4}

/

--

2

--

ms

Short Protection Off

Timer

/

40

I²C Characteristics

SCL, SDA Low Input

Voltage

V_I²_CIL

V_I²_CIH

V_I²_COL

--

1.2

--

0.4

--

V

SCL, SDA High Input

Voltage

SCL, SDA Low Output

Voltage

0.4

I²C CLK Frequency

I²C Work Voltage

f_SCL

V_I²_Cint

1

--

1.8

--

MHz

V

2

Input Current Each IO Pin

10

10

A

I_{IN_I C}

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Parameter

Data Hold Time

Symbol

Test Conditions

Min

30

Typ

--

Max

--

Unit

ns

2

t_{DH_I C}

2

Data Set-Up Time

70

--

ns

t_{DS_I C}

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θ_JAis measured under natural convection (still air) at T_A= 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV

below its nominal value.

System Characteristics

The following system specifications are guaranteed by designed and are not performed in production testing.

(T_A= 25°C, unless otherwise specified.)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

System Parameter

Over-Temperature

Warning

OTW

115

--

125

20

135

--

°C

Over-Temperature

Warning Hysteresis

OTW_H

OTP

Over-Temperature

Protection

130

--

140

20

150

--

Over-Temperature

Protection Hysteresis

OTP_H

0x0A[4:3] = 01

HWEN and BSTEN Control

HWEN = H to I²C operation

available

HWEN = L to I²C operation stop

HWEN Turn On Delay

--

50

--

s

t_{HWEN_ON}

HWEN Turn Off Delay

BSTEN Turn On Delay

BSTEN Turn Off Delay

t_{HWEN_OFF}

t_{BSTEN_ON}

t_{BSTEN_OFF}

BSTEN to Boost voltage start

rising

225

16

BSTEN off to Boost switch stop

Step Down Buck Converter (V_{IN_B}= 3.8V, C1 = C2 = 10F, L1 = 1H)

Maximum Output Current

1.2

--

A

I_{OUT_BUCK}

V_{LOAD_REG_BUCK}

Load Regulation

1.5

%

CCM, V_{OUT_BUCK}= 1.1V

CCM, I_OUT= 50/300/1200mA,

V_{LINE_REG_BUCK}

Line Regulation

--

1.5

%

V_{OUT_BUCK}= 1.1V, V_{IN_B}= 3.0V

to 4.4V

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RT5112

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

CCM, I_OUT= 300mA, V_{OUT_BUCK}

= 1.1V, V_{IN_B}< 4.35V

--

10

Output Ripple

Soft-Start Time

mV

V_{RIPPLE_BUCK}

PFM, V_{OUT_BUCK}= 1.1V, V_{IN_B}

4.35V

<

--

30

40

--

0x09[7:6] = 10, time from

V_{OUT_BUCK}= 0V rising to 90%

235

s

t_{SS_BUCK}

nominal value, V_{OUT_BUCK}

1.1V, no load

=

V_{OUT_BUCK}= 1.1V, 20 to 80%

_OUT(MAX), 1s, recovery time <

10s

_{OUT_BUCK}= 1.1V, I_OUT= 200mA

to 600mA

Load Transient

Efficiency

--

70

--

mV

%

V_{TRAN_BUCK}

I

V

85

Eff_{_BUCK}

Step Up Boost Converter (V_{IN_BST}= 3.8V, C3 = 10F, C4 = 22F, L2 = 0.47H)

Maximum Output Current

1

--

A

I_{OUT_BST}

V_{IN_BST}= 2.8V, V_{OUT_BST}= 5V

0x05[5:4] = 00, time from

V_{OUT_BST}= 0V rising to 90%

Soft-Start Time

--

580

s

t_{SS_BST}

nominal value, V_{OUT_BST}= 5V, no

load

Time from BSTEN = H to

Start Up Time

V

_{OUT_BST}rising to 90% nominal

--

700

1.5

s

%

t_{START_BST}

value, V_{OUT_BST}= 5V, no load

Load Regulation

Line Regulation

V_{LOAD_REG_BST}

V_{LINE_REG_BST}

CCM, V_{OUT_BST}= 5V

CCM, I_OUT= 50/1000mA,

V_{IN_BST}= 3V to 4.4V, V_{OUT_BST}=

5V

CCM, I_OUT= 500mA, V_{IN_BST}

3.4V to 4.4V, V_{OUT_BST}= 5V

=

--

40

80

Output Ripple

Load Transient

mV

V_{RIPPLE_BST}

PFM, V_{IN_BST}= 3.4V to 4.4V,

40

V_{OUT_BST}= 5V

V_{OUT_BST}= 5V, 20 to 80%

--

100

150

V_{TRAN_BST}

I_OUT(MAX), 2s, recovery time <

30s

V

_{OUT_BST}= 5V, V_{IN_BST}= 3.4V,

_{OUT_BST}= 10mA

V_{OUT_BST}= 5V, V_{IN_BST}= 3.4V,

_{OUT_BST}= 600mA

V_{OUT_BST}= 5V, V_{IN_BST}= 3.4V,

_{OUT_BST}= 1A

--

88

90

84

10

--

I

Power Efficiency

%

Eff_{_BST}

I

Linear Charge Hiccup On

Time

During linear charge state

ms

t_{LC_ON}

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Parameter

Symbol

t_{LC_OFF}

Test Conditions

Min

Typ

Max

Unit

Linear Charge Hiccup Off

Time

Restart linear charge

--

100

--

ms

ABS Output Over-Voltage

Rising Threshold

Stop switch

Start switch

--

6.5

5.8

--

V

OVP_{_R_ABS_BST}

ABS Output Over-Voltage

Falling Threshold

OVP_{_F_ABS_BST}

Low Dropout Voltage Regulator LDO1 and LDO2 (V_{IN_VIN12}= V_{OUT_LDO1}/V_{OUT_LDO2}+ 1V, V_HWEN= 1.2V, I_OUT

= 1mA, C_IN= 2.2F, C_OUT= 2.2F)

V_{RIPPLE_LDO1}

V_{RIPPLE_LDO2}

V_{TRAN_LDO1}

V_{TRAN_LDO2}

/

I

_OUT= 0 to I_OUT(MAX)

V_{OUT_LDO1}/V_{OUT_LDO2}= 2.8V

_OUT= 1mA to 150mA, 150mA/s,

,

Output Ripple Voltage

Load Transient

--

10

50

mV

/

I

V_{OUT_LDO1}/V_{OUT_LDO2}= 2.8V

V_{IN_VIN12}= 3.4V, f = 1kHz, I_OUT

=

70

--

100mA, V_{OUT_LDO1}/V_{OUT_LDO2}

2.8V

=

Power Supply Rejection PSRR_{_LDO1}

/

dB

Ratio

V_{IN_VIN12}= 3.4V, f = 100kHz,

PSRR_{_LDO2}

40

--

I

_OUT= 100mA,

_{OUT_LDO1}/V_{OUT_LDO2}= 2.8V

V

e_{N_LDO1}

/

100Hz to 100kHz, I_OUT= 100mA,

V_{OUT_LDO1}/V_{OUT_LDO2}= 2.8V

Output Noise Voltage

50

V

e_{N_LDO2}

Low Dropout Voltage Regulator LDO3 and LDO4 (V_{IN_VIN3}/V_{IN_VIN4}= V_{OUT_LDO3}/V_{OUT_LDO4}+ 1V, V_HWEN

=

1.2V, I_OUT= 1mA, C_IN= 2.2F, C_OUT= 2.2F)

V_{RIPPLE_LDO3}

V_{RIPPLE_LDO4}

V_{TRAN_LDO3}

V_{TRAN_LDO4}

/

I_OUT= 0 to I_OUT(MAX)

_{OUT_LDO3}/V_{OUT_LDO4}= 1.8V

I_OUT= 1mA to 150mA, 150mA/s,

,

Output Ripple Voltage

Load Transient

--

10

50

mV

V

/

mV

V_{OUT_LDO3}/V_{OUT_LDO4}= 1.8V

V_{IN_VIN3}/ V_{IN_VIN4}= 1.95V,

50

--

f = 1kHz, I_OUT= 100mA,

_{OUT_LDO3}/V_{OUT_LDO4}= 1.8V

V

Power Supply Rejection PSRR_{_LDO3}

/

dB

Ratio

PSRR_{_LDO4}

V_{IN_VIN3}/ V_{IN_VIN4}= 1.95V,

f = 10kHz, I_OUT= 100mA,

40

--

V_{OUT_LDO3}/V_{OUT_LDO4}= 1.8V

eN_LDO3/

eN_LDO4

100Hz to 100kHz, I_OUT= 100mA,

V_{OUT_LDO3}/V_{OUT_LDO4}= 1.8V

Output Noise Voltage

50

V

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RT5112

Typical Operating Characteristics

Shutdown Current vs. Temperature

Buck Quiescent Current vs. Input Voltage

1.0

12

11

10

9

0.8

0.6

0.4

0.2

8

7

V_BUCK= 1.1V, Temperature = 25°C

HWEN = L, BSTEN = L

50 75 100 125

0.0

6

-50

-25

0

25

2.5

3.0

3.5

4.0

4.5

Temperature (°C)

Input Voltage (V)

Buck Quiescent Current vs. Temperature

Buck Efficiency

12

11

10

9

100

90

80

70

60

50

V_INB= 3.4V

V_INB= 3.8V

V_INB= 4.35V

8

7

V_BUCK= 1.1V

0.8 1.0 1.2

V_INB= 3.8V, V_BUCK= 1.1V

6

-50

-25

0

25

50

75

100

125

0.0

0.2

0.4

0.6

Temperature (°C)

Load Current (A)

Buck Load Regulation

Buck Output Voltage Ripple vs. Load Current

1.13

1.12

1.11

1.10

1.09

1.08

30

25

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

20

15

10

5

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_BUCK= 1.1V

1.0 1.2

V_BUCK= 1.1V

0.8 1.0 1.2

0

0.0

0.2

0.4

0.6

0.8

0.0

0.2

0.4

0.6

Load Current (A)

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Buck Switching Frequency vs. Load Current

3.0

Buck Power On

SCL

(2V/Div)

2.5

2.0

1.5

1.0

0.5

0.0

V_IN

(1V/Div)

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_INB= 3.8V, V_BUCK= 1.1V, I_BUCK= 0mA

V_BUCK

(500mV/Div)

I_IN

V_BUCK= 1.1V

0.8 1.0 1.2

(50mA/Div)

0.0

0.2

0.4

0.6

Time (200μs/Div)

Load Current (A)

Buck Load Transient

Buck Power Off

SCL

(2V/Div)

V_IN

(1V/Div)

V_BUCK

(50mV/Div)

V_BUCK

(500mV/Div)

I_BUCK

(200mA/Div)

V_INB= 3.8V, V_BUCK= 1.1V, I_BUCK= 0mA

I_IN

V_INB= 3.8V, V_BUCK= 1.1V,

I_BUCK= 240mA to 960mA (t_R= t_F= 1μs)

(50mA/Div)

Time (50μs/Div)

Time (2ms/Div)

Boost Quiescent Current vs. Input Voltage

Boost Quiescent Current vs. Temperature

18

17

16

15

14

13

12

11

10

18

17

16

15

14

13

12

11

10

V_BOOST= 5V, Temperature = 25°C

V_IN= 3.8V, V_BOOST= 5V

2.5

3.0

3.5

4.0

4.5

-50

-25

0

25

50

75

100

125

Temperature (°C)

Input Voltage (V)

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RT5112

Boost Efficiency

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_BOOST= 5V, NFCAuto (0x05[6] = 1, 0x39[2] = 0)

0.2 0.4 0.6 0.8 1.0

V_BOOST= 5V, NFCFCCM (0x05[6] = 0, 0x39[2] = 1)

0.2 0.4 0.6 0.8 1.0

50

0.0

Load Current (A)

Boost Load Regulation

5.10

5.08

5.06

5.04

5.02

5.00

4.98

4.96

4.94

4.92

4.90

5.10

5.08

5.06

5.04

5.02

5.00

4.98

4.96

4.94

4.92

4.90

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

V_BOOST= 5V, NFCAuto (0x05[6] = 1, 0x39[2] = 0)

V_BOOST= 5V, NFCFCCM (0x05[6] = 0, 0x39[2] = 1)

0.0 0.2 0.4 0.6 0.8 1.0

0.0

0.2

0.4

0.6

0.8

1.0

Load Current (A)

Boost Output Voltage Ripple vs. Load Current

80

V_INB= 4.35V

V_INB= 3.8V

V_INB= 3.4V

70

60

50

40

30

20

10

0

V_INB= 3.8V

V_INB= 3.4V

70

60

50

40

30

20

10

0

V_BOOST= 5V, NFCAuto (0x05[6] = 1, 0x39[2] = 0)

V_BOOST= 5V, NFCFCCM (0x05[6] = 0, 0x39[2] = 1)

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

Load Current (A)

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Boost Switching Frequency vs. Load Current

3500

Boost Switching Frequency vs. Load Current

3500

3000

2500

2000

3000

2500

2000

1500

V_INB= 3.4V

V_INB= 3.8V

V_INB= 4.35V

V_INB= 3.4V

V_INB= 3.8V

V_INB= 4.35V

1000

500

0

1000

500

V_BOOST= 5V, NFCAuto (0x05[6] = 1, 0x39[2] = 0)

V_BOOST= 5V, NFCFCCM (0x05[6] = 0, 0x39[2] = 1)

0

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

Load Current (A)

Boost Register Power On

Boost Register Power Off

SCL

(2V/Div)

SCL

(2V/Div)

V_IN

(1V/Div)

V_IN

(1V/Div)

V_IN= 3.8V, V_BOOST= 5V, I_BOOST= 0mA

V_BOOST

(2V/Div)

V_BOOST

(2V/Div)

V_IN= 3.8V, V_BOOST= 5V, I_BOOST= 0mA

I_IN

(200mA/Div)

Time (200μs/Div)

Time (2ms/Div)

Boost BSTEN Power On

Boost BSTEN Power Off

BSTEN

(2V/Div)

BSTEN

(2V/Div)

V_IN

(1V/Div)

V_IN

(1V/Div)

V_IN= 3.8V, V_BOOST= 5V, I_BOOST= 0mA

V_BOOST

(2V/Div)

V_BOOST

(2V/Div)

V_IN= 3.8V, V_BOOST= 5V, I_BOOST= 0mA

I_IN

(200mA/Div)

Time (200μs/Div)

Time (2ms/Div)

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Boost Load Transient

V_BOOST

(100mV/Div)

V_BOOST

(100mV/Div)

V_IN= 3.8V, V_BOOST= 5V,

I_BOOST= 200mA to 800mA (t_R= t_F= 2μs),

NFCAuto (0x05[6] = 1, 0x39[2] = 0)

NFCFCCM (0x05[6] = 0, 0x39[2] = 1)

I_BOOST

(200mA/Div)

I_BOOST

(200mA/Div)

Time (200μs/Div)

LDO Quiescent Current vs. Input Voltage

LDO Quiescent Current vs. Temperature

25

24

23

22

21

20

30

28

26

24

22

20

18

16

LDO4

LDO3

LDO2

LDO1

LDO4

LDO3

LDO2

LDO1

V_IN12/V_IN3/V_IN4= 3.8V,

V_LDO1/V_LDO2= 2.8V, V_LDO3/V_LDO4= 1.8V

V_LDO1/V_LDO2= 2.8V, V_LDO3/V_LDO4= 1.8V,

Temperature = 25°C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

-50

-25

0

25

50

75

100

125

Temperature (°C)

Input Voltage (V)

LDO1 Load Regulation

LDO2 Load Regulation

2.802

2.800

2.798

2.796

2.794

2.792

2.790

2.788

2.786

2.800

2.798

2.796

2.794

2.792

2.790

2.788

2.786

V_IN12= 4.35V

V_IN12= 3.8V

V_IN12= 3.4V

V_IN12= 3V

V_IN12= 4.35V

V_IN12= 3.8V

V_IN12= 3.4V

V_IN12= 3V

V_LDO1= 2.8V

0.25 0.30

V_LDO2= 2.8V

0.20 0.25 0.30

0.00

0.05

0.10

0.15

0.20

0.00

0.05

0.10

0.15

Load Current (A)

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LDO3 Load Regulation

LDO4 Load Regulation

1.798

1.796

1.794

1.792

1.790

1.788

1.786

1.784

1.798

1.796

1.794

1.792

1.790

1.788

1.786

1.784

V_IN3= 4.35V

V_IN3= 3.8V

V_IN3= 3V

V_IN3= 2.8V

V_IN3= 2.5V

V_IN3= 1.95V

V_IN4= 4.35V

V_IN4= 3.8V

V_IN4= 3V

V_IN4= 2.8V

V_IN4= 2.5V

V_IN4= 1.95V

V_LDO4= 1.8V

V_LDO3= 1.8V

0.25 0.30

0.00

0.05

0.10

0.15

0.20

0.00

0.05

0.10

0.15

0.20

0.25

0.30

Load Current (A)

LDO1 Dropout Voltage vs. Load Current

LDO2 Dropout Voltage vs. Load Current

100

80

60

40

20

0

100

80

60

40

20

0

85°C

25°C

-40°C

85°C

25°C

-40°C

V_LDO1= 2.8V

V_LDO2= 2.8V

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Load Current (A)

LDO3 Dropout Voltage vs. Load Current

LDO4 Dropout Voltage vs. Load Current

140

120

100

80

140

120

100

80

85°C

25°C

-40°C

85°C

25°C

-40°C

60

40

20

V_LDO3= 1.8V

V_LDO4= 1.8V

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Load Current (A)

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RT5112

LDO3/4 PSRR

LDO1/2 PSRR

20

0

20

0

-20

-40

-60

-80

-100

-20

-40

-60

-80

LDO3

LDO4

LDO1

LDO2

V_IN12= 3.4V, V_LDO1/V_LDO2= 2.8V,

I_LDO1/I_LDO2= 100mA

V_IN3/V_IN4= 1.95V, V_LDO3/V_LDO4= 1.8V,

I_LDO3/I_LDO4= 100mA

-100

100

1000

10000

100000 1000000 10000000

1000

10000

100000 1000000 10000000

Frequency (Hz)

LDO1/2 Output Noise

LDO3/4 Output Noise

10

1

10

1

LDO1

LDO2

LDO3

LDO4

0.1

0.01

V_LDO3/V_LDO4= 1.8V, I_LDO3/I_LDO4= 100mA

V_LDO1/V_LDO2= 2.8V, I_LDO1/I_LDO2= 100mA

1000 10000 100000

0.01

100

1000

10000

100000

Frequency (Hz)

LDO1 Power On

LDO1 Power Off

SCL

(2V/Div)

V_IN

(1V/Div)

V_IN= 3.8V, V_IN12= 3.8V,

V_LDO1= 2.8V, I_LDO1= 0mA

V_LDO1

(1V/Div)

V_LDO1

(1V/Div)

V_IN= 3.8V, V_IN12= 3.8V,

V_LDO1= 2.8V, I_LDO1= 0mA

I_IN

(50mA/Div)

Time (100μs/Div)

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DS5112-03 August 2019

RT5112

LDO2 Power On

LDO2 Power Off

SCL

(2V/Div)

SCL

(2V/Div)

V_IN

(1V/Div)

V_IN= 3.8V, V_IN12= 3.8V,

V_LDO2= 2.8V, I_LDO2= 0mA

V_LDO2

(1V/Div)

V_LDO2

(1V/Div)

V_IN= 3.8V, V_IN12= 3.8V,

V_LDO2= 2.8V, I_LDO2= 0mA

I_IN

(50mA/Div)

Time (100μs/Div)

LDO3 Power On

LDO3 Power Off

SCL

(2V/Div)

V_IN

(1V/Div)

SCL

(2V/Div)

V_IN

(1V/Div)

V_LDO3

V_IN= 3.8V, V_IN3= 2.8V,

V_LDO3= 1.8V, I_LDO3= 0mA

(500mV/Div)

V_LDO3

(500mV/Div)

V_IN= 3.8V, V_IN3= 2.8V,

V_LDO3= 1.8V, I_LDO3= 0mA

I_IN

(50mA/Div)

Time (100μs/Div)

LDO4 Power On

LDO4 Power Off

SCL

(2V/Div)

V_IN

(1V/Div)

SCL

(2V/Div)

V_IN

(1V/Div)

V_LDO4

(500mV/Div)

V_IN= 3.8V, V_IN4= 2.8V,

V_LDO4= 1.8V, I_LDO4= 0mA

V_LDO4

(500mV/Div)

V_IN= 3.8V, V_IN4= 2.8V,

V_LDO4= 1.8V, I_LDO4= 0mA

I_IN

(50mA/Div)

Time (100μs/Div)

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RT5112

LDO2 Load Transient

LDO1 Load Transient

V_LDO2

(10mV/Div)

V_LDO1

(10mV/Div)

V_IN12= 3.8V, V_LDO2= 2.8V,

I_LDO2= 1mA to 150mA (t_R= t_F= 1μs)

V_IN12= 3.8V, V_LDO1= 2.8V,

I_LDO1= 1mA to 150mA (t_R= t_F= 1μs)

I_LDO1

I_LDO2

(50mA/Div)

Time (5μs/Div)

LDO3 Load Transient

LDO4 Load Transient

V_LDO3

V_LDO4

(10mV/Div)

V_IN3= 2.8V, V_LDO3= 1.8V,

V_IN4= 2.8V, V_LDO4= 1.8V,

I_LDO3= 1mA to 150mA (t_R= t_F= 1μs)

I_LDO4= 1mA to 150mA (t_R= t_F= 1μs)

I_LDO4

(50mA/Div)

I_LDO3

(50mA/Div)

Time (5μs/Div)

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DS5112-03 August 2019

RT5112

Application Information

When the RT5112 recovers from OTP, it can re-start in

three configurations with register 0x0A[4:3] bits.

The RT5112 is a smart power-management integrated

circuit (PMIC), which includes a Buck converter, a Boost

converter and four LDOs.

 0x0A[4:3] = 00, the RT5112 is manual re-start with

default register values.

System Under-Voltage Protection and Over-Voltage

Protection

 0x0A[4:3] = 01, the RT5112 is auto recovery with last

register values before OTP.

The device does not operate with V_SYSvoltages below the

Under-Voltage Lock Out (UVLO) level. There is a typical

100mV hysteresis implemented to avoid unstable on/ off

behavior. The RT5112 is initialized in its default state after

V_SYSvoltage recovers from UVLO. When V_SYSvoltage

reaches the Over Voltage Protection level, the RT5112

will disable Buck converter immediately to protect next

stage circuit input. The V_SYSUV and OV status bits and

interrupt bits will be set, and INTRB pin will be pulled low

with corresponding to protection detected.

 0x0A[4:3] = 10, the RT5112 is latched off. Re-set V_INor

HWEN or BSTEN (if Boost is controlled by BSTEN) to

re-start the RT5112 with default register values.

Enable and Disable Control

The HWEN pin controls the RT5112 start up without

enabling channels. If HWENpin is at low state, the RT5112

is in power down mode and I²C will return NACK to any

request. Only when HWENpin is at high state, all channels

are controllable via I²C with corresponding ENABLE

command. The BSTENpin is only used to hardware control

Boost converter enable or disable. There are both built-in

resistors on HWEN and BSTEN pins to keep at low state

if pins are left unconnected.

Thermal Protection

The RT5112 features over-temperature warning (OTW) and

over-temperature protection (OTP). The OTW status bit

and interrupt bit are set and INTRB pin will be pulled low

when the junction temperature is higher than typical

125°C. If the junction temperature further exceeds typical

160°C, OTP will be triggered to shut down the device.

The below tables provide channels state with combinations

of different ENABLE pins and register EN bits.

 Buck and LDOs

Table 1. Buck and LDOs Control

EN bits SEQ_CTRL bits Dependent

HWEN pin

Low

SEQ bits

000

On / Off

Off

0

1

0

1

0

1

0

1

No

Low

000

Off

Low

000

No

Off

Low

000

No

Off

High

000

No

Off

000

No

On

000

Yes

CTRL

On

000

On / Off

Note : CTRL indicates several operating conditions as below.

(1) SEQ_CTRL[1:0] = 00, set SEQ bits

regardless EN bit.

000 and EN bit = 1, channel is turned off after 7 sequence slot count

(2) SEQ_CTRL[1:0] = 01, set SEQ bits000 and EN bit = 1, channel is turned on depends on EN bit.

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RT5112

 Sequence Control Setting

Note :

The RT5112 Buck and LDOs sequence on/off control

setting can be programmed via I²C with dedicated

registers as below.

(1) Any changes in Sequence (7 slots), slot interval

time and soft-start time during sequence on or off

procedure is not valid and will not modify the RT5112

setting.

 Sequence (7 slots)

Register 0x00[6:4] is used to control Buck

sequence on/off slot.

(2) Channel setting (output voltage, current limit...etc.)

is fixed during on or off sequence.

Registers 0x01[6:4], 0x02[6:4], 0x03[6:4] and

0x04[6:4] are used to control LDOs sequence on/

off slots.

(3) Register 0x09[5:4] = 11 will turn off all channels

immediately.

(4) HWEN= 0 will turn off all channels and the RT5112

enters into power down mode.

 Slot Interval Time

Register 0x09[7:6] is used to control interval time

between each slot.

 Normal Control Setting

When register bits 0x09[5:4] = 10, the Buck and LDOs

on/off control depends on channel Enable bit.

 Soft Start Time

Register 0x09[7:6] is used to control Buck

sequence on soft start time.

 Register 0x00[7] is used to control Buck on/off.

 Register 0x01[7], 0x02[7], 0x03[7] and 0x04[7] are

used to control LDOs on/off.

Register 0x11[1:0] is used to control LDOs

sequence on soft start time.

^Sequence Control

Register 0x09[5:4] = 00 is used to enable sequence

off with sequence setting 000.

Register 0x09[5:4] = 01 is used to enable sequence

on with sequence setting000.

HWEN

BUCK_DELAY

LDOX_DELAY

SEQ_CTRL = 10

SEQ_CTRL = 01

SEQ_CTRL = 00

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 1.

Example for sequence on/off with BUCK assign to SLOT1, LDO1 assign to SLOT2, LDO2 assign to SLOT3, LDO3

assign to SLOT4 and LDO4 assign to SLOT5.

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DS5112-03 August 2019

RT5112

HWEN

BUCK_DELAY

LDOX_DELAY

SEQ_CTRL = 10

SEQ_CTRL = 01

SEQ_CTRL = 00

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 2.

Example for sequence on/off with BUCK assign to SLOT1, LDO1 assign to SLOT3, LDO2 assign to SLOT3, LDO3

assign to SLOT7 and LDO4 assign to SLOT5.

HWEN

BUCK_DELAY

LDO2_DELAY, LDO3_DELAY and LDO4_DELAY change setting

LDOX_DELAY

SEQ_CTRL = 10

SEQ_CTRL = 01

SEQ_CTRL = 00

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 3.

Example for sequence slot change when on procedure. LDO2 assign from SLOT3 to SLOT5, LDO3 assign from SLOT4

to SLOT6 and LDO4 assign from SLOT5 to SLOT7. There is no influence with on procedure and new setting will

executed after on sequence finish.

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RT5112

HWEN

BUCK_DELAY

LDOX_DELAY

SEQ_CTRL = 10

SEQ_CTRL = 01

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 4.

Example for sequence on is interrupted by HWEN signal low. The RT5112 turns off all channels immediately.

HWEN

BUCK_DELAY

LDOX_DELAY

SEQ_CTRL = 10

SEQ_CTRL = 01

SEQ_CTRL = 00

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 5.

Example for sequence off is interrupted by HWEN signal low. The RT5112 turns off all channels immediately.

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DS5112-03 August 2019

RT5112

HWEN

LDOX_DELAY

SEQ_CTRL = 10

BUCK_EN

SEQ_CTRL = 01

SEQ_CTRL = 00

LDO1_EN

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 6.

Example for sequence control SEQ_CTRL change from 01 to 00. LDO2, LDO3, LDO4 are sequence off and LDO1 is

turned off by itself enable bit. BUCK1 is turned off after 7 sequence slot count even itself enable bit is at high state.

HWEN

LDOX_DELAY

SEQ_CTRL = 10

BUCK_EN

SEQ_CTRL = 01

SEQ_CTRL = 10

LDO1_EN

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 7.

Example for sequence control SEQ_CTRL change from 01 to 10. LDO2, LDO3, LDO4 are turned off and state of BUCK,

LDO1 depends on itself enable bit.

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RT5112

HWEN

LDOX_DELAY

SEQ_CTRL = 10

BUCK_EN

SEQ_CTRL = 01

SEQ_CTRL = 11

LDO1_EN

SLOT1

SLOT2

SLOT3

SLOT4

SLOT5

SLOT6

SLOT7

SLOT6

SLOT5

SLOT4

SLOT3

SLOT2

SLOT1

BUCK

LDO1

LDO2

LDO3

LDO4

Figure 8.

Example for sequence control SEQ_CTRL change from 01 to 11. All channels are turned off immediately.

 Boost

Table 2. Boost Control

HWEN pin

Low

BSTEN pin

Low

EN bits

On / Off

0

1

0

1

0

1

0

1

Off

On

Off

On

Low

High

Low

High

Low

High

Note : The Boost Control table above shows that the Boost operation requires either BSTEN pin to be high or a

combination of HWEN pin high and one of the EN bits in register 0x08 needs to be set to 1.

 Normal Control Setting

The RT5112 Boost on/off control setting can be programmed via I²C with dedicated registers or external BSTENpin.

 BSTEN pin to hardware control on/off.

 Register 0x08[7] to 0x08[0], each bit is able to software control on/off.

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DS5112-03 August 2019

RT5112

HWEN

BSTEN

BOOST_EN = 0

BOOST_EN = 1

BOOST_EN = 0

BOOST

Figure 9.

Example for normal control with combination of BSTEN pin and EN bits.

HWEN

BSTEN

BOOST_EN = 0

(HWEN = 0 to clear BOOST_EN)

BOOST_EN = 0

(HWEN = 0 to clear BOOST_EN)

BOOST_EN = 0

BOOST

BOOST_EN = 1

Figure 10.

Example for normal control with combination of BSTEN pin and EN bits. BSTEN pin is able to control Boost regardless

of HWEN state.

Output Voltage Setting

Operating Mode

The RT5112 output voltage can be programmed via I²C

The RT5112 provides different operating modes for Buck,

with dedicated registers.

Boost and LDOs for flexible application. Registers

 Buck

0x00[1:0], 0x01[1:0], 0x02[1:0], 0x03[1:0], 0x04[1:0] and

Register 0x0C[7:0] is used to control Buck output

voltage.

0x05[1:0] are used to control the operating mode.

 Buck and Boost

^Auto PFM (Pulse Frequency Modulation) Mode

Register 0x14[7:6] is used to control Buck voltage

scaling slew rate.

In order to save power and improve efficiency at low

loads, the Buck/ Boost operate in PFM mode as the

inductor drops intoDCM (Discontinuous Current Mode).

The switching frequency is proportional to loading to

reach output voltage regulation. When load increases

and inductor current becomes continuous again, the

Buck/ Boost automatically goes back to PWM fixed

frequency mode. Additionally, the RT5112 will enters

DSLP (Deep Sleep) to reach input low quiescent

current at no load.

 Boost

Register 0x11[7:2] is used to control Boost output

voltage.

Register 0x14[3:2] is used to control Boost voltage

scaling slew rate.

 LDOs

Registers 0x0D[7:1], 0x0E[7:1], 0x0F[7:1], 0x10[7:1]

are used to control LDO1, LDO2, LDO3 and LDO4

output voltage.

Register 0x14[5:4] is used to control LDOs voltage

scaling slew rate.

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RT5112

 FPWM (Forced Pulse Width Modulation) Mode

(depends on load) is always higher than 1.6MHz, it

goes back to normal operating.

The switching frequency is forced into PWM mode

operation. In this mode, the inductor current is in CCM

(Continuous Current Mode) and the voltage is regulated

by PWM.

^FCCM NFC (0x05[6] = 0, 0x39[2] = 1)

When the loading is increased to 130mA (typ.), the

RT5112 will activate FCCMNFC function to transit Boost

into FPWM mode operation. The operating switching

frequency is 3MHz (typ.) which is much higher than

847 106kHz to interfereNFC module.

 Normal Mode

The operation is same as Auto PFM mode. The only

one difference is that there is no DSLP in this mode.

 Ultra-Sonic Mode

Channel Protection Features

To avoid acoustic noise problem when operation, the

switching frequency is designed to be always higher

than 20kHz even there is no load at output.

The RT5112 equips Over-Current Protection, Under-

Voltage Protection and Over-Voltage Protection to prevent

the device from damages causing by abnormal operation

or fault conditions. (over-load, short-circuit, soldering

issue...etc.)

^LDOs

 Auto Mode

This mode is for general use.

^Over-Current Protection (OCP)

^EN Forced Mode

 Behavior after OCP

When EN Forced Mode is selected, the RT5112 can

provide higher PSRR (Power Supply Rejection Ratio)

to mitigate interference from input voltage. However,

it brings out higher quiescent current to get the

function.

Register 0x37[7:5] is used to select the operation

after over-current failure detected.

 OCP Mechanism

 Buck

When the inductor current reaches the high-side

MOSFET peak current limit threshold, the high-side

MOSFET will be turned-off. The low-side MOSFET

turns on to discharge the inductor current until the

inductor current trips below the low-side MOSFET

valley current limit threshold. After high-side

MOSFET peak current limit triggered, the maximum

inductor current is decided by the inductor current

rising rate and the response delay time of the internal

network.

^Bypass Mode

LDO internal power MOSFET is fully turned on. Input

voltage will pass through it to the output terminal

directly.

Operating Mode for NFC module (Only Boost)

The RT5112 provides two ways to avoid Boost switching

frequency situated at around 847 106kHz during NFC

module operation duration. Registers 0x05[6] and 0x39[2]

are used to select the method.

 Boost

 Auto NFC (0x05[6] = 1, 0x39[2] = 0)

When the loading current is increased such that

the inductor current is above the high-side MOSFET

valley current limit threshold, the off-time is

increased until the inductor current is decreased to

valley current threshold. The maximum inductor

current is decided by the high-side MOSFET valley

current limit level and internal designed inductor

current ripple.

When switching frequency is close to 600kHz (typ.),

the RT5112 will activateAutoNFC function to increase

the switching frequency to around 1.1MHz (typ.). When

the switching frequency continues to increase to 1.6MHz

(typ.) with increasing load, it will leave Auto NFC

mechanism. If the present switching frequency is

situated at range 600kHz to 1.1MHz when leaving, it

will re-activateAutoNFC function to increase switching

frequency again. Once the present switching frequency

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RT5112

 LDOs

^Ovrt-Voltage Protection (OVP)

 Behavior after OVP

When the loading reaches the current limit threshold,

the current sent to the output will kept at current

limit level.

Register 0x0A[2:0] is used to select the operation

after over voltage failure detected.

^Under-Voltage Protection (UVP)

 Behavior after UVP

Register 0x0A[7:5] is used to select the operation

after under voltage failure detected.

Table 3. Protection

Threshold

(typ.)

Deglitch Time

(typ.)

Reset and Threshold

Channel

Type

Protection

(typ.)

V_SYS< 2.35V

V_SYS 2.25V

UVLO

525s

IC Shutdown

V_SYS 2.35V

(after IC Operation)

OVP

OTW

V_SYS 5.9V

200s

50s

Buck Disable

Report only

V_SYS 5.6V

Temperature 125°C

Temperature 105°C

Selection by 0x0A[4:3]

00 : Manual recovery

after TSD with reset

register

System

OTP

Temperature 140°C

50s

IC Shutdown

01 : Auto recovery after

TSD with no reset

register



10 : Latch off after TSD

with reset register

Selection by 0x0A[7]

0 : Hiccup mode

1 : Latch-off mode

V_BUCKV_{BUCK_SET}

x

V_BUCK V_{BUCK_SET}x

UVP

OVP

OCP

UVP

OVP

50s

8s

80%

92%

Selection by 0x0A[2]

0 : Discharge mode

1 : Latch-off mode

V_BUCK V_{BUCK_SET}

BUCK

V_BUCK V_{BUCK_SET}x 109%

120%

I_{LXBUCK_peak}2A

Selection by 0x037[7] I_{LXBUCK_peak}< 2A

0 : Hiccup mode

1 : Latch-off mode

I_{LXBUCK_valley}1.5A

I_{LXBUCK_valley}< 1.5A

(peak - 0.5A)

Selection by 0x0A[5]

0 : Hiccup mode

1 : Latch-off mode

V_BOOST V_BOOST

x

V_BOOST V_BOOST

92.3%

x

50s

80%

Selection by 0x0A[0]

0 : NA

1 : Latch-off mode

V_BOOSTV_BOOST

V_BOOST V_BOOST

106%

8s

117%

BOOST

ABS

OVP

V_BOOST 6.5V

Stop switch

V_BOOST 5.8V

Selection by 0x037[5]

0 : Hiccup mode I_{LXBOOST_valley}< 2.5A

OCP

I_{LXBOOST_valley} 2.5A

1 : Latch-off mode

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RT5112

Threshold

(typ.)

Deglitch Time

(typ.)

Reset and Threshold

(typ.)

Channel

Type

Protection

Selection by 0x0A[6]

0 : Hiccup mode

1 : Latch-off mode

UVP

OVP

OCP

V_LDO V_LDOx 80%

V_LDO V_LDOx 120%

I_LDO> 415mA

50s

8s

V_LDO V_LDOx 90%

V_LDOV_LDOx 110%

I_LDO 415mA

Selection by 0x0A[1]

0 : Discharge mode

1 : NA

LDOs

Selection by 0x037[6]

0 : Hiccup mode

1 : Latch-off mode

Interrupt

^Fault Event and Status

The RT5112 interrupt controller continuously monitors the device operation. Once the fault is ever detected, the fault

event bit will be set to 1 and the open drain interrupt indicate pin INTRB will be driven to ground level. Meanwhile, the

fault status bit will also be set to 1 to show the present fault. When the host reads the fault event bit and set interrupt

clear bit 0x14[0] = 1, the INTRB pin will be released to high impedance. The fault status bit goes back to 0 only till the

fault condition is cleared.

Table 4. Interrupt

Fault Event

BUCK_UV_EVT 0x15[7]

LDO1_UV_EVT 0x15[6]

LDO2_UV_EVT 0x15[5]

LDO3_UV_EVT 0x15[4]

LDO4_UV_EVT 0x15[3]

BOOST_UV_EVT 0x15[2]

BOOST_FAULT_EVT 0x15[0]

BUCK_OV_EVT 0x16[7]

LDO1_OV_EVT 0x16[6]

LDO2_OV_EVT 0x16[5]

LDO3_OV_EVT 0x16[4]

LDO4_OV_EVT 0x16[3]

BOOST_OV_EVT 0x16[2]

BUCK_OCP_EVT 0x17[7]

LDO1_OCP_EVT 0x17[6]

LDO2_OCP_EVT 0x17[5]

LDO3_OCP_EVT 0x17[4]

Fault Status

BUCK_UV_STAT 0x2B[7]

LDO1_UV_STAT 0x2B[6]

LDO2_UV_STAT 0x2B[5]

LDO3_UV_STAT 0x2B[4]

LDO4_UV_STAT 0x2B[3]

BOOST_UV_STAT 0x2B[2]

BOOST_FAULT_STAT 0x2B[0]

BUCK_OV_STAT 0x2C[7]

LDO1_OV_STAT 0x2C[6]

LDO2_OV_STAT 0x2C[5]

LDO3_OV_STAT 0x2C[4]

LDO4_OV_STAT 0x2C[3]

BOOST_OV_STAT 0x2C[2]

BUCK_OCP_STAT 0x2D[7]

LDO1_OCP_STAT 0x2D[6]

LDO2_OCP_STAT 0x2D[5]

LDO3_OCP_STAT 0x2D[4]

Description

BUCK output under-voltage

LDO1 output under-voltage

LDO2 output under-voltage

LDO3 output under-voltage

LDO4 output under-voltage

BOOST output under-voltage

BOOST internal fault

BUCK output over-voltage

LDO1 output over-voltage

LDO2 output over-voltage

LDO3 output over-voltage

LDO4 output over-voltage

BOOST output over-voltage

BUCK over-current

LDO1 over-current

LDO2 over-current

LDO3 over-current

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RT5112

Fault Event

LDO4_OCP_EVT 0x17[3]

BOOST_OCP_EVT 0x17[2]

TWARN_EVT 0x19[7]

TSD_EVT 0x19[6]

Fault Status

LDO4_OCP_STAT 0x2D[3]

BOOST_OCP_STAT 0x2D[2]

TWARN_STAT 0x2F[7]

TSD_STAT 0x2F[6]

Description

LDO4 over-current

BOOST over-current

Thermal warning

Thermal shutdown

VSYSUV_EVT 0x19[5]

VSYSOV_EVT 0x19[4]

VSYSUV_STAT 0x2F[5]

VSYSOV_STAT 0x2B[4]

System under-voltage

System over-voltage

^Fault Event Mask

The host can set the fault event mask bits to hide the fault events. When the mask bit is set to 1, the corresponding

fault is hidden and the interrupt indicate pin INTRB will keep high impedance without being pulled to ground level. The

host requires to read the fault event bits to clear its value to 0, otherwise the interrupt indicate pin INTRB will be driven

to low level again when mask bits being set to 1. The mask bits will be reset to default value with conditions : HWEN

voltage goes to low level or IC power shutdown.

HWEN

Fault

INTRB

MASK = 0

EVENT = 0

Status = 0

INT_CLS = 0

EVENT READ

MASK = 1

MASK = 0

MASK = 1

MASK=0

EVENT = 0

EVENT = 1

EVENT = 0

EVENT = 1

Status = 1

Status = 0

Status = 1

Status = 0

1

INT_CLS = 0

1

INT_CLS = 0

READ

Figure 11.

Component Selection

capacitor for Buck and a 22μF (6.3V) output capacitor

for Boost. The ripple voltage is an important index for

choosing output capacitor. This portion consists of

two parts. One is the product of ripple current with

the ESR of the output capacitor, while the other part

is formed by the charging and discharging process of

the output capacitor. The output ripple can be

calculated as below.

 Inductor Selection

The recommended nominal inductance 1μH/0.47μH for

Buck/ Boost converter. The inductor saturation current

must be chosen carefully considering the current limit

level. It is suggested to select an inductor with the low

DCR to provide good performance and efficiency for

application.

^Buck

 Input and Output Capacitor Selection

 Buck and Boost

I_L

V_OUT V_ESR V_OUT1



8C_OUTf_SW

It is recommended at least a 10μF (6.3V) input

capacitor for Buck and Boost, a 10μF (6.3V) output

V

 I_{COUT_RMS}R_{COUT_ESR}

where

ESR

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RT5112

 Boost

I_OUTD

f_SWC_OUT

V_OUT V_ESR V_OUT1 V_ESR



V

 I_{COUT_RMS}R_{COUT_ESR}

where

^LDOs

ESR

Like any low dropout regulator, the external capacitors

of the RT5112 must be carefully selected for regulator

stability and performance. Using a capacitor of at least

2.2μF (X5R or X7R) is suitable.

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RT5112

I²C Interface

The following table shows the RT5112 unique address as below.

RT5112 I²C Slave Address

MSB

LSB

R/W bit

R/W

010000

0

1/0

41/40

The I²C interface bus must be connect a resistor 2.2kΩ to power node and independent connection to processor,

individually. The I²C timing diagrams are listed below.

Read N bytes from the RT5112

Slave Address

Register Address

Slave Address

MSB

Data 1

LSB

S

0

A

Sr

1

A

Assume Address = m

Data for Address = m

LSB

R/W

MSB

Data 2

LSB

Data N

A

P

A

Data for Address = m + N - 1

Data for Address = m + 1

Register Address

Write N bytes to the RT5112

Slave Address

MSB

Data 1

LSB MSB

A

Data 2

LSB

S

0

A

Assume Address = m

Data for Address = m

MSB

Data for Address = m + 1

LSB

R/W

Data N

A

P

Data for Address = m + N - 1

Driven by Master,

Driven by Slave, P Stop, S Start, Sr Repeat Start

I²C Waveform Information

SDA

t

BUF

LOW

t

F

t

R

t

F

t

R

t

SU;DAT

HD;STA

SP

SCL

t

SU;STO

HD;STA

SU;STA

t

HIGH

HD;DAT

S

P

S

r

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RT5112

I²C Register Table

R : Read only.

RC : Read then Clear.

RW : Read and Wirte.

WC : Write “1” then clear to “0” after this procedure finish.

Note : Below registers setting are only available on the RT5112A.

0x06, 0x0B[2], 0x12, 0x13[5:4], 0x15[1], 0x16[1], 0x17[1], 0x2B[1], 0x2C[1], 0x2D[1], 0x30[1], 0x32[1], 0x33[1], 0x34[1],

0x3B[1], 0x43[4]

Addr

RegName

Bit BitName

Default Type

Description

Buck enable. This bit is mask if REG0x00[6:4] :

BUCK_DELAY ≠ 3'b000

0 : Disable (default)

7

BUCK_EN

0

RW

1 : Enable

Note : When Buck's latch-off protection happen,

this bit will reset to "0"

Buck power on/off delay time setting:

000 : Controlled by I²C with REG0x00[7] :

BUCK_EN (default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

100 : SLOT4

101 : SLOT5

BUCK_

DELAY

6:4

000

RW

110 : SLOT6

111 : SLOT7

0x00 Buck_CTRL

(delay time setting at on/off sequence are reverse)

Note : When Buck's latch-off protection happen,

these bits will reset to "000"

Buck current limit set bit.

00 : 1.5A

01 : 2A (default)

10 : 2.5A

BUCK_

ILIM

3:2

1:0

01

00

RW

11 : 3A

Buck operation mode :

00 : Auto PFM mode (default)

01 : Forced PWM mode

10 : Ultra sonic mode

11 : Normal mode

BUCK_

MODE

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

LDO1 enable. This bit is mask if REG0x01[6:4] :

LDO1_DELAY ≠ 3'b000

0 : Disable (default)

1 : Enable

7

LDO1_EN

0

RW

Note : When LDO1's latch-off protection happen, this

bit will reset to "0"

LDO1 power on/off delay time setting:

000 : Controlled by I²C with REG0x01[7] : LDO1_EN

(default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

LDO1_

DELAY

6:4

000

RW 100 : SLOT4

101 : SLOT5

110 : SLOT6

111 : SLOT7

(delay time setting at on/off sequence are reverse)

0x01 LDO1_CTRL

Note : When LDO1's latch-off protection happen,

these bits will reset to "000"

LDO1 current limit set bit.

00 : 150mA

3:2

1:0

11

00

RW 01 : 250mA

LDO1_ILIM

10 : 300mA

11 : 360mA (default)

LDO1 operation mode :

00 : Auto mode (default)

01 : EN forced mode. (High PSRR mode).

RW 10 : Bypass mode. LDO1 internal power MOSFET

turns on fully.

LDO1_

MODE

11 : Bypass mode. LDO1 internal power MOSFET

turns on fully.

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

LDO2 enable. This bit is mask if REG0x02[6:4] :

LDO2_DELAY ≠ 3'b000

0 : Disable (default)

1 : Enable

7

LDO2_EN

0

RW

Note : When LDO2's latch-off protection happen,

this bit will reset to "0"

LDO2 power on/off delay time setting :

000 : Controlled by I²C with REG0x02[7] :

LDO2_EN (default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

RW 100 : SLOT4

101 : SLOT5

LDO2_

DELAY

6:4

000

110 : SLOT6

111 : SLOT7

0x02 LDO2_CTRL

(delay time setting at on/off sequence are reverse)

Note : When LDO2's latch-off protection happen,

these bits will reset to "000"

LDO2 current limit set bit.

00 : 150mA

RW 01 : 250mA

LDO2_

ILIM

3:2

1:0

11

00

10 : 300mA

11 : 360mA (default)

LDO2 operation mode :

00 : Auto mode (default)

01 : EN forced mode. (High PSRR mode).

RW 10 : Bypass mode. LDO2 internal power MOSFET

turns on fully.

LDO2_

MODE

11 : Bypass mode. LDO2 internal power MOSFET

turns on fully.

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

LDO3 enable. This bit is mask if REG0x03[6:4] :

LDO3_DELAY ≠ 3'b000

0 : Disable (default)

1 : Enable

7

LDO3_EN

0

RW

Note : When LDO3's latch-off protection happen,

this bit will reset to "0"

LDO3 power on/off delay time setting :

000 : Controlled by I²C with REG0x03[7] :

LDO3_EN (default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

RW 100 : SLOT4

101 : SLOT5

LDO3_

DELAY

6:4

000

110 : SLOT6

111 : SLOT7

0x03 LDO3_CTRL

(delay time setting at on/off sequence are reverse)

Note : When LDO3's latch-off protection happen,

these bits will reset to "000"

LDO3 Current limit set bit.

00 : 150mA

RW 01 : 250mA

LDO3_

ILIM

3:2

1:0

11

00

10 : 300mA

11 : 360mA (default)

LDO3 operation mode :

00 : Auto mode (default)

01 : EN forced mode. (High PSRR mode).

RW 10 : Bypass mode. LDO3 internal power MOSFET

turns on fully.

LDO3_

MODE

11 : Bypass mode. LDO3 internal power MOSFET

turns on fully.

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

LDO4 enable. This bit is mask if REG0x04[6:4] :

LDO4_DELAY ≠ 3'b000

0 : Disable (default)

1 : Enable

7

LDO4_EN

0

RW

Note : When LDO4's latch-off protection happen, this

bit will reset to "0"

LDO4 power on/off delay time setting :

000 : Controlled by I²C with REG0x04[7] : LDO4_EN

(default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

LDO4_DE

LAY

6:4

000

RW 100 : SLOT4

101 : SLOT5

110 : SLOT6

111 : SLOT7

0x04 LDO4_CTRL

(delay time setting at on/off sequence are reverse)

Note : When LDO4's latch-off protection happen,

these bits will reset to "000"

LDO4 current limit set bit.

00 : 150mA

RW 01 : 250mA

LDO4_ILI

M

3:2

1:0

11

00

10 : 300mA

11 : 360mA (default)

LDO4 operation mode :

00 : Auto mode (default)

01 : EN forced mode. (High PSRR mode).

RW 10 : Bypass mode. LDO4 internal power MOSFET

turns on fully.

LDO4_MO

DE

11 : Bypass mode. LDO4 internal power MOSFET

turns on fully.

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Boost linear charge current :

RW 0 : 400mA (default)

1 : 800mA

7

LCH_ON

0

Boost NFC enable. 0x39[2] must set 0 when bit

NFC_EN = 1.

0 : Disable

6

NFC_EN

1

RW

1 : Enable (default)

Voltage scaling slew rate for Boost.

00 : 14mV/s (default)

RW 01 : 10mV/s

10 : 6mV/s

11 : 4mV/s

Boost current limit set bit.

00 : 2A

RW 01 : 2.5A (default)

10 : 3A

BOOST_

SS

5:4

00

01

BOOST_

CTRL

0x05

BOOST_

ILIM

3:2

1:0

11 : 3.5A

Boost operation mode:

00 : Auto PFM mode (default)

RW 01 : Forced PWM mode

10 : Ultra sonic mode

BOOST_

MODE

00

11 : Normal mode

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

BUCK2 enable. This bit is mask if REG0x06[6:4] :

BUCK2_DELAY ≠ 3'b000

0 : Disable (default)

BUCK2_

EN

7

0

RW

1 : Enable

Note : When Buck2's latch-off protection happen,

this bit will reset to "0"

BUCK2 power on/off delay time setting :

000 : Controlled by I²C with REG0x06[7] :

BUCK2_EN (default)

001 : SLOT1

010 : SLOT2

011 : SLOT3

RW 100 : SLOT4

101 : SLOT5

BUCK2_

DELAY

6:4

000

110 : SLOT6

111 : SLOT7

0x06 Buck2_CTRL

(delay time setting at on/off sequence are reverse)

Note : When Buck2's latch-off protection happen,

these bits will reset to "000"

BUCK2 current limit set bit.

00 : 1.5A

RW 01 : 2A (default)

BUCK2_

ILIM

3:2

1:0

01

00

10 : 2.5A

11 : 3A

BUCK2 operation mode:

00 : Auto mode (default)

RW 01 : Forced PWM mode

10 : Ultra sonic mode

BUCK2_

MODE

11 : Normal mode

Addr

RegName

Bit

BitName

Default Type

11001101

Description

Vendor identification

0x07

Product ID

7:0

PID

R

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Enable bit #7 for the Boost.

RW 0 : Disable (default)

BOOST_

EN7

7

0

1 : Enable

Enable bit #6 for the Boost.

BOOST_

EN6

6

5

4

3

2

1

0

RW 0 : Disable (default)

1 : Enable

Enable bit #5 for the Boost.

BOOST_

EN5

RW 0 : Disable (default)

1 : Enable

Enable bit #4 for the Boost.

BOOST_

EN4

RW 0 : Disable (default)

1 : Enable

BOOST_

ENABLE

0x08

Enable bit #3 for the Boost.

BOOST_

EN3

RW 0 : Disable (default)

1 : Enable

Enable bit #2 for the Boost.

BOOST_

EN2

RW 0 : Disable (default)

1 : Enable

Enable bit #1 for the Boost.

BOOST_

EN1

RW 0 : Disable (default)

1 : Enable

Enable bit #0 for the Boost.

BOOST_

EN0

RW 0 : Disable (default)

1 : Enable

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RT5112

Addr

RegName

Bit BitName

Default Type

Description

Set slot period :

00 : 2.73ms

01 : 1.365ms

10 : 0.682ms (default)

11 : 0.341ms

(slot period is the base unit of each SLOT, for

example SLOT2 = 2*slot period; SLOT3 = 3*slot

period)

Set soft-start time slew rate (Buck_SR) :

00 : 1mV/s

RW 01 : 2mV/s

SEQ_SPE

7:6

10

ED[1:0]

10 : 4mV/s (default)

11 : 7mV/s

(Buck's VOUT min. step = 12.5mV, f = 2.5MHz)

(Once slot period is chose, corresponding soft start

time slew rate is determined.)

Note : Buck soft-start time (Buck_tss)

00 : 1ms/V x Vout

0x09 SEQ_PROG

01 : 0.5ms/V x Vout

10 : 0.25ms/V x Vout (default)

11 : 0.143ms/V x Vout

2 bits to control LDOs and Buck's ON/OFF

00 : Power-Down, relative regulators (CHx_DELAY

≠ 3’b000) disable by power off sequence, others

turn off by each EN bit

SEQ_

5:4

01 : Power-UP,relative regulators (CHx_DELAY ≠

3’b000) enable by power on sequence, others turn

on by each EN bit

10

RW

CTRL[1:0]

10 : All regulators's ON/OFF depend on each EN

bit. (default)

11 : All regulators turn off directly.

3:0 Reserved

0000

RW Reserved

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck hiccup or latch off mode selection after V_OUV.

0 : Hiccup mode; (continouously hiccup more than 3

times would enter latch-off mode ,select deglitch

time by REG0x38[7:6], hiccup on/off time = 5/8ms)

(default)

BUCK_UV

_LATCH

7

0

RW

1 : Latch-off mode

LDO hiccup or latch off mode selection after V_OUV.

0 : Hiccup mode; (continouously hiccup more than 3

times would enter latch-off mode ,select deglitch

time by REG0x38[3:2], hiccup on/off time = 5/40ms)

(default)

LDO_UV_

LATCH

6

5

1 : Latch-off mode

Boost hiccup or latch off mode selection after V_OUV.

0 : Hiccup mode; (continouously hiccup more than 3

times would enter latch-off mode ,select deglitch

time by REG0x37[3:2], hiccup on/off time =

11/100ms) (default)

BOOST_U

V_LATCH

1 : Latch-off mode

IC protection after thermal shutdown :

00 : Manual recovery after TSD with reset I²C

register. The power up sequence is initiated with

default I²C register value

0x0A

Latch

01 : Auto recovery after TSD with no reset I²C

register. The power up sequence is initiated with I²C

register value (default)

4:3

TSD[1:0]

01

RW

10 : Latch off after TSD, all Reg reset. Restart by Vin

start up or (BSTEN = 0 → 1 to restart Boost) or

(HWEN = 0 → 1 to eanble channel), i.e.BSTEN and

HWEN need pull low to unlock

11 : No change, follow before setting

Buck discharge or latch off mode selection after V_O

BUCK_OV

_LATCH

OV.

2

0

RW

0 : R Discharge (default)

1: Latch-off mode

LDO discharge mode selection after V_OOV.

0 : R Discharge; (During DVS period won't sent OV

Event to INTRB) (default)

LDO_OV_

LATCH

1

0

1 : NA

Boost latch off mode selection after V_OOV.

RW 0 : NA (default)

1 : Latch-off mode

BOOST_O

V_LATCH

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RT5112

Addr

RegName

Bit BitName

Default Type

Description

Buck active output discharge.

RW 0 : Disable

BUCK_

DIS

7

1

1 : Enable (default)

LDO active output discharge.

RW 0 : Disable

6

5

LDO_DIS

1 : Enable (default)

Boost active output discharge.

RW 0 : Disable

1 : Enable (default)

BOOST_

DIS

4

3

Reserved

0

RW Reserved

Buck2 active output discharge.

RW 0 : Disable

1 : Enable (default)

BUCK2_

DIS

2

1

0x0B DISCHARGE

Boost registers keep and reset control. Self reset

function: it can recover to 0 when set 1 :

0 : Keep Boost relative Reg value Register0x05[7],

0x05[5:2], 0x08[7:0], 0x0A[5], 0x0A[0], 0x14[3:2],

0x37[5], 0x37[3:2] Boost relative bits. (default)

1 : Boost relative Reg recover to default value.

When HWEN OFF and BCTRL = 0 (default), Boost

keeps relative Reg.

When HWEN ON and BCTRL = 1, Boost recover to

default value. BCTRL become 0 automatically,

Boost relative Reg is kept.

When HWEN ON and BCTRL = 0, Boost relative

can be written normally.

1

0

BCTRL

0

WC

When write 1 then it will recover to 0.

Reserved

RW Reserved

Addr

RegName

Bit BitName

Default Type

Description

Buck output voltage can be set default voltage from

0.8V to 3.3V with 12.5mV/step.

00000000 : 0.6V

00000001 : 0.6125V

…

00101000 : 1.1V (default)

…

Buck_Vout

0x0C Buck_Vout

7:0

00101000 RW

[7:0]

11010111 : 3.2875V

11011000 : 3.3V

…

11111111: 3.3V

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RT5112

Addr

RegName

Bit

BitName

Default Type

Description

LDO1 output voltage can be set default voltage from

0.6V to 3.775V with 25mV/step.

0000000 : 0.6V

0000001 : 0.625V

…

1011000 : 2.8V (default)

…

LDO1_

Vout[6:0]

7:1

1011000

RW

0x0D LDO1_Vout

1111110 : 3.75V

1111111 : 3.775V

0

Reserved

0

RW Reserved

Addr

RegName

Bit

BitName

Default Type

Description

LDO2 output voltage can be set default voltage

from 0.6V to 3.775V with 25mV/step.

0000000 : 0.6V

0000001 : 0.625V

…

1011000 : 2.8V (default)

…

LDO2_

Vout[6:0]

7:1

1011000

RW

0x0E LDO2_Vout

1111110 : 3.75V

1111111 : 3.775V

0

Reserved

0

RW Reserved

Addr

RegName

Bit

BitName

Default Type

Description

LDO3 output voltage can be set default voltage from

0.6V to 3.775V with 25mV/step.

0000000 : 0.6V

0000001 : 0.625V

…

0110000 : 1.8V (default)

…

LDO3_

Vout[6:0]

7:1

0110000

RW

0x0F LDO3_Vout

1111110 : 3.75V

1111111 : 3.775V

0

Reserved

0

RW Reserved

Addr

RegName

Bit

BitName

Default Type

Description

LDO4 output voltage can be set default voltage from

0.6V to 3.775V with 25mV/step.

0000000 : 0.6V

0000001 : 0.625V

…

0110000 : 1.8V (default)

…

LDO4_

Vout[6:0]

7:1

0

0110000

RW

0x10 LDO4_Vout

1111110 : 3.75V

1111111 : 3.775V

Reserved

0

RW Reserved

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47

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Boost output voltage can be set default voltage from

4.5V to 5.5V with 25mV/step.

000000 : 4.5V

000001 : 4.525V

…

RW 010100: 5.0V (default)

Boost_

Vout[5:0]

7:2

010100

…

100111: 5.475V

101000: 5.5V

…

0x11 Boost_Vout

111111: 5.5V

Voltage scaling slew rate for LDO.

00 : 100mV/s

RW 01 : 50mV/s (default)

10 : 25mV/s

1:0

LDO_SS

01

11 : 12.5mV/s

Addr

RegName

Bit

BitName

Default Type

Description

Buck2 output voltage can be set default voltage from

0.6V to 3.3V with 12.5mV/step.

00000000 : 0.6V

00000001 : 0.6125V

…

Buck2_

Vout[7:0]

0x12 Buck2_Vout 7:0

10110100 RW 10110100 : 2.85V (default)

…

11010111 : 3.2875V

11011000 : 3.3V

…

11111111: 3.3V

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48

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck SW on/off speed set. Decrease SW speed can

help the EMI performance.

00 : Slower

01 : Slow (default)

10 : Normal

Buck_SR

[1:0]

7:6

01

RW

11 : Fast

Buck2 SW on/off speed set. Decrease SW speed

can help the EMI performance.

00 : Slower

01 : Slow (default)

10 : Normal

Buck2_SR

[1:0]

5:4

0x13

LX_SR

11 : Fast

3

2

Reserved

0

RW Reserved

Boost SW on/off speed set. Decrease SW speed

can help the EMI performance.

00 : Fast

01 : Normal

Boost_SR

[1:0]

1:0

10

RW

10 : Slow (default)

11 : Slower

Addr

RegName

Bit

BitName

Default Type

Description

Voltage scaling slew rate for Buck.

00 : 7mV/s

RW 01 : 4mV/s (default)

10 : 2mV/s

BUCK_

DVS

7:6

01

11 : 1mV/s

Voltage scaling slew rate for LDO.

00 : 36mV/s

RW 01 : 14mV/s (default)

10 : 8.5mV/s

5:4 LDO_DVS

11 : 4mV/s

0x14

DVS

Voltage scaling slew rate for Boost.

00 : 32mV/s

RW 01 : 15mV/s (default)

10 : 8mV/s

BOOST_

3:2

DVS

11 : 4mV/s

1

0

Reserved

INT_CLS

0

RW Reserved

Interrupt clear pin.

0 : Normal operation (default)

1 : Refresh interrupt bits.

WC

(After write “1”, the bit will auto return to “0”.)

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49

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : Buck UV event detected

BUCK_

UV_EVT

7

0

RC

LDO1 under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO1 UV event detected

LDO1_

UV_EVT

6

5

4

3

2

1

0

LDO2 under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO2 UV event detected

LDO2_

UV_EVT

LDO3 under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO3 UV event detected

LDO3_

UV_EVT

0x15

UV_EVT

LDO4 under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO4 UV event detected

LDO4_

UV_EVT

Boost under-voltage threshold sense

acknowledgement.(raising trigger)

0 : No fault or be masked (default)

1 : Boost UV event detected

BOOST_

UV_EVT

Buck2 under-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : Buck2 UV event detected

BUCK2_

UV_EVT

Boost SCP (VOUT < 0.7V) or VDS protect (VIN –

VOUT > 300mV) or IL > 5A internal Boost FAULT

0 : Not fault or be masked (default)

BOOST_

FAULT_

EVT

1 : Boost fault event detected

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50

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : Buck OV event detected

BUCK_

OV_EVT

7

0

RC

LDO1 over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO1 OV event detected

LDO1_

OV_EVT

6

5

4

3

2

LDO2 over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO2 OV event detected

LDO2_

OV_EVT

LDO3 over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO3 OV event detected

LDO3_

OV_EVT

0x16

OV_EVT

LDO4 over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : LDO4 OV event detected

LDO4_

OV_EVT

Boost over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : Boost OV event detected

BOOST_

OV_EVT

Buck2 over-voltage threshold sense

acknowledgement. (raising trigger)

0 : No fault or be masked (default)

1 : Buck2 OV event detected

BUCK2_

OV_EVT

1

0

Reserved

RC Reserved

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51

RT5112

Addr

RegName

Bit BitName

Default Type

Description

Buck over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : Buck OCP event detected

BUCK_

7

0

RC

OCP_EVT

LDO1 over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : LDO1 OCP event detected

LDO1_

6

OCP_EVT

LDO2 over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : LDO2 OCP event detected

LDO2_

5

OCP_EVT

LDO3 over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : LDO3 OCP event detected

LDO3_

4

OCP_EVT

0x17

OCP_EVT

LDO4 over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : LDO4 OCP event detected

LDO4_

3

OCP_EVT

Boost over-current protection acknowledgement.

(raising trigger )

0 : No fault or be masked (default)

1 : Boost OCP event detected

BOOST_

2

OCP_EVT

Buck2 over-current protection acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : Buck2 OCP event detected

BUCK2_

1

0

OCP_EVT

0

Reserved

RC Reserved

Addr

RegName

Bit BitName

Default Type

Description

Thermal warning sense acknowledgement.

(raising/falling trigger)

0 : No fault or be masked (default)

1 : Thermal warning event detected

TWARN_

7

0

RC

EVT

Thermal shutdown sense acknowledgement.

(raising/falling trigger)

0 : No fault or be masked (default)

1 : Thermal shutdown event detected

6

5

4

TSD_EVT

VSYS under-voltage sense acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : Under-voltage event detected

0x19 BASE_EVT

VSYSUV_

EVT

VSYS over-voltage sense acknowledgement.

(raising trigger)

0 : No fault or be masked (default)

1 : Over-voltage event detected

VSYSOV_

EVT

0

3:0 Reserved

0000

RC Reserved

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52

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Chip revision

00000000 : 1^stVersion

00000001 : 2^ndVersion

00000010 : 3^rdVersion

00000011 : 4^thVersion (default)

...

0x2A Revision ID 7:0

RID[7:0] 00000011

R

11111111 : 256^thVersion

Addr

RegName

Bit

BitName

Default Type

Description

Buck under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BUCK_UV

_STAT

7

0

R

LDO1 under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO1_UV

_STAT

6

5

4

3

2

1

LDO2 under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO2_UV

_STAT

LDO3 under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO3_UV

_STAT

LDO4 under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

0x2B

UV_STAT

LDO4_UV

_STAT

Boost under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BOOST_

UV_STAT

Buck2 under-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BUCK2_

UV_STAT

Boost SCP (VOUT < 0.7V) or VDS protect (VIN –

VOUT > 300mV) or IL > 5A internal boost FAULT

status.

0 : No fault occurs (default)

1 : Fault occurs

BOOST_

FAULT_

STAT

0

R

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53

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BUCK_OV

_STAT

7

0

R

LDO1 over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO1_OV

_STAT

6

5

4

3

2

LDO2 over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO2_OV

_STAT

LDO3 over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO3_OV

_STAT

0x2C

OV_STAT

LDO4 over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

LDO4_OV

_STAT

Boost over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BOOST_

OV_STAT

Buck2 over-voltage threshold sense status.

0 : No fault occurs (default)

1 : Fault occurs

BUCK2_

OV_STAT

1

0

R

Reserved

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54

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

BUCK_

OCP_

STAT

Buck over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

7

0

R

LDO1_

OCP_

STAT

LDO1 over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

6

5

4

3

2

LDO2_

OCP_

STAT

LDO2 over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

LDO3_

OCP_

STAT

LDO3 over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

0x2D OCP_STAT

LDO4_

OCP_

STAT

LDO4 over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

BOOST_

OCP_

STAT

Boost over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

BUCK2_

OCP_

STAT

Buck2 over-current protection status.

0 : No fault occurs (default)

1 : Fault occurs

1

0

R

Reserved

Addr

RegName

Bit

7

BitName

Default Type

Description

Thermal warning sense status.

0 : No fault occurs (default)

1 : Fault occurs

TWARN_

STAT

0

R

Thermal shutdown sense status.

0 : No fault occurs (default)

1 : Fault occurs

TSD_

STAT

6

5

4

3

VSYS under-voltage sense status.

0 : No fault occurs (default)

1 : Fault occurs

VSYSUV_

STAT

0x2F BASE_STAT

VSYS over-voltage sense status.

0 : No fault occurs (default)

1 : Fault occurs

VSYSOV_

STAT

It indicates status of the internal SEQ_ON signal.

0 : SEQ OFF (default)

SEQ_ON

0

R

1 : SEQ ON

2:0 Reserved

000

Reserved

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55

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Indicate Buck final enable status.

0 : Disable (default)

1 : Enable

BUCK_EN

_FLG

7

0

R

Indicate LDO1 final enable status.

0 : Disable (default)

1 : Enable

LDO1_EN

_FLG

6

5

4

3

2

Indicate LDO2 final enable status.

0 : Disable (default)

1 : Enable

LDO2_EN

_FLG

Indicate LDO3 final enable status.

0 : Disable (default)

1 : Enable

LDO3_EN

_FLG

0x30

EN_FLG

Indicate LDO4 final enable status.

0 : Disable (default)

1 : Enable

LDO4_EN

_FLG

Indicate BOOST final enable status.

0 : Disable (default)

1 : Enable

BOOST_

EN_FLG

Indicate Buck2 final enable status.

0 : Disable (default)

1 : Enable

BUCK2_

EN_FLG

1

0

R

Reserved

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56

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck under-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BUCK_UV

_MASK

7

0

LDO1 under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO1_UV

_MASK

6

5

4

3

2

1

LDO2 under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO2_UV

_MASK

LDO3 under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO3_UV

_MASK

LDO4 under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

0x32

UV_MASK

LDO4_UV

_MASK

Boost under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BOOST_

UV_MASK

Buck2 under-voltage threshold sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BUCK2_

UV_MASK

Boost SCP (VOUT < 0.7V) or VDS protect (VIN –

VOUT > 300mV) or IL > 5A internal boost FAULT

RW mask.

BOOST_

FAULT_

MASK

0

0 : Interrupt is not masked (default)

1 : Interrupt is masked

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57

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BUCK_

OV_MASK

7

0

LDO1 over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO1_OV

_MASK

6

5

4

3

2

LDO2 over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO2_OV

_MASK

LDO3 over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO3_

OV_MASK

0x33 OV_MASK

LDO4 over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO4_

OV_MASK

Boost over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BOOST_

OV_MASK

Buck2 over-voltage threshold mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BUCK2_

OV_MASK

1

0

Reserved

RW Reserved

Addr

RegName

Bit

7

BitName

Default Type

Description

BUCK_

OCP_

MASK

Buck over-current protection mask.

0

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO1_

OCP_

MASK

LDO1 over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

6

5

4

3

2

LDO2_

OCP_

MASK

LDO2 over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

LDO3_

OCP_

MASK

LDO3 over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

0x34 OCP_MASK

LDO4_

OCP_

MASK

LDO4 over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BOOST_

OCP_

MASK

Boost over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

BUCK2_

OCP_

MASK

Buck2 over-current protection mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

1

0

Reserved

RW Reserved

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58

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Thermal warning sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

TWARN_

MASK

7

0

Thermal shutdown sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

TSD_

MASK

6

5

4

BASE_

MASK

VSYS under-voltage sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

0x36

VSYSUV_

MASK

VSYS over-voltage sense mask.

RW 0 : Interrupt is not masked (default)

1 : Interrupt is masked

VSYSOV_

MASK

0

3:0 Reserved

0000

RW Reserved

Addr

RegName

Bit

BitName

Default Type

Description

Buck Hiccup or latch off mode selection after

current limit.

RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off

mode. Hiccup on/off time = 4ms / 8ms) (default)

1 : Latch-off mode.

BUCK_OC

_LATCH

7

0

LDO Hiccup or latch off mode selection after

current limit.

RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off

mode. Hiccup on/off time = 2ms/40ms) (default)

1 : Latch-off mode.

LDO_OC_

LATCH

6

BOOST Hiccup or latch off mode selection after

current limit.

RW 0 : Hiccup mode; (Hiccup 3 times will enter latch-off

mode, hiccup on/off time = 10ms/100ms) (default)

1 : Latch-off mode.

0x37

CHx_PT

BOOST_

OC_

LATCH

5

4

0

Reserved

RW Reserved

Boost UV deglitch time selection :

00 : 10s

RW 01 : 15s

BST_UV_

DT[1:0]

3:2

11

00

10 : 25s

11: 50s (default)

1:0 Reserved

RW Reserved

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59

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

Buck UV deglitch time selection :

00 : 5s

RW 01 : 10s

Buck_UV_

DT[1:0]

7:6

11

10 : 15s

11 : 50s (default)

Buck OV deglitch time selection :

00 : 10s

RW 01 : 15s

Buck_OV_

DT[1:0]

5:4

3:2

1:0

10 : 20s

11 : 50s (default)

CHx_deglitch

time

0x38

LDO UV deglitch time selection :

00 : 10s

RW 01 : 15s

LDO_UV_

DT[1:0]

10 : 30s

11 : 50s (default)

LDO OV deglitch time selection :

00 : 5s

RW 01 : 10s

LDO_OV_

DT[1:0]

11

10 : 25s

11 : 50s (default)

Addr

RegName

Bit

BitName

Default Type

Description

VSYSUV deglitch time selection :

00 : 70s

RW 01 : 135s

VSYSUV_

DT[1:0]

7:6

11

10

10 : 265s

11 : 525s (default)

VSYSOV deglitch time selection:

00 : 20s

RW 01 : 50s

VSYSOV_

DT[1:0]

5:4

10 : 180s (default)

11 : 360s

BASEPT_

deglitch time

0x39

VSYSOV turn off Buck

RW 0 : When Vsys_OV occur will turn off BCK (default)

1 : When Vsys_OV occur will not turn off BCK

VSYSOV_

PT

3

2

0

NFC load detection. 0x05[6] must set 0 when bit

BST_NFC_force = 1.

0 : AUTO NFC (default)

BST_NFC

_Force

RW

1 : FCCM by load, turn off NFC

1

0

Reserved

0

RW Reserved

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60

DS5112-03 August 2019

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

It indicates the states of power on sequence

00 : SEQ_ON hasn't started or needless (default)

01 : SEQ_ON is carrying out (During SLOT1 to

SLOT8 + 4ms)

10 : There are fail soft-start channels during power

on sequence

SEQ_ON_

STAT[1:0]

7:6

00

R

11 : SEQ_ON has completed

It indicateds the fault SLOT during power on

sequence at SEQ_ON_STAT = 2'b10

000 : SLOT1 (default)

001 : SLOT2

010 : SLOT3

011 : SLOT4

100 : SLOT5

101 : SLOT6

110 : SLOT7

111 : SEQ_ON has completed

0x3A

SEQ_ON

SEQ_

COUNT

[2:0]

5:3

000

R

2:0 Reserved

Reserved

Addr

RegName

Bit

BitName

Default Type

Description

It indicates Buck soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

BCK

7

0

R

It indicates LDO1 soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

LDO1

6

5

4

3

2

It indicates LDO2 soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

LDO2

It indicates LDO3 soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

LDO3

0x3B SSEND_CHx

It indicates LDO4 soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

LDO4

It indicates Boost soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

BST

It indicates Buck2 soft-start end or not

0 : Not soft-start end (default)

1 : Soft-start end

sSSEND_

BCK2

1

0

R

Reserved

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is a registered trademark of Richtek Technology Corporation.

DS5112-03 August 2019

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61

RT5112

Addr

RegName

Bit

BitName

Default Type

Description

7:6 Reserved

00

RW Reserved

Interrupt reflash pulse width timing.

00 : disable (default)

RW 01 : 2s

INT_DEG[

5:4

00

1:0]

10 : 4s

11 : 8s

Indicate PMU's State

0000 : IDLE (default)

0x42

INT_SET

0001 : ONSEQ (slot1 to slot7 + 4ms, when 4ms

clock end will tigger ONSEQ_END)

0010 : ONSEQ_END

SEQ_STA

3:0

0000

R

T[2:0]

0011 : ENSEQ

0100 : OFFSEQ

0101 : OFFSEQ_END (slot7 to slot1, when slot1

sequence end will tigger OFFSEQ_END)

1111 : Else

Addr

RegName

Bit

BitName

Default Type

Description

BST latch off (BSTEN)

0 : Release (default)

1 : Latch off

BST latch off (HWEN)

0 : Release (default)

1 : Latch off

BCK1 latch off

0 : Release (default)

1 : Latch off

BCK2 latch off

0 : Release (default)

1 : Latch off

PMU_

STAT

0x43 PMU_STAT 7:0

00000000

R

LDO1 latch off

0 : Release (default)

1 : Latch off

LDO2 latch off

0 : Release (default)

1 : Latch off

LDO3 latch off

0 : Release (default)

1 : Latch off

LDO4 latch off

0 : Release (default)

1 : Latch off

©

is a registered trademark of Richtek Technology Corporation.

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62

DS5112-03 August 2019

RT5112

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Thermal Considerations

Four-Layer PCB

The junction temperature should never exceed the

absolute maximum junction temperature T_J(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

0

25

50

75

100

125

Ambient Temperature (°C)

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction-to-ambient

thermal resistance.

Figure 12.Derating Curve of Maximum PowerDissipation

Layout Considerations

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125°C. The junction-to-ambient thermal

resistance, θ_JA, is highly package dependent. For a WL-

CSP-25B 2.2x2.3 (BSC) package, the thermal resistance,

θ_JA, is 31.5°C/W on a standard JEDEC 51-7 high effective-

thermal-conductivity four-layer test board. The maximum

power dissipation at T_A= 25°C can be calculated as below

:

The PCB layout is an important step to maintain the high

performance of the RT5112. Both the high current and the

fast switching nodes demand full attention to the PCB

layout to keep the robustness of the RT5112 through the

PCB layout. Improper layout might lead to the symptoms

of poor line or load regulation, ground and output voltage

shifts, stability issues, unsatisfying EMI behavior or

worsened efficiency. For the best performance of the

RT5112, the following PCB layout guidelines must be

strictly followed.

P_D(MAX)= (125°C − 25°C) / (32.7°C/W) = 3.05W for a WL-

CSP-25B 2.2x2.3 (BSC) package.

 The trace from switching node to inductor should be as

short as possible to minimized the switching loop for

better EMI.

The maximum power dissipation depends on the operating

ambient temperature for the fixed T_J(MAX)and the thermal

resistance, θ_JA. The derating curves in Figure 12 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

 Place the input and output capacitors close to the input

and output pins respectively for good filtering.

 Keep the main power traces as wide and short as

possible.

 Connect the AGND, DGND, GNDB and GNDBST to a

strong ground plane for maximum thermal dissipation

and noise protection.

 Directly connect the Buck output capacitors to the

feedback network to avoid bouncing caused by parasitic

resistance and inductance from the PCB trace.

©

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DS5112-03 August 2019

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63

RT5112

Bottom

Layer

TOP Layer

3rd Layer

GND

V_{OUT_BUCK}

V_{IN_VIN4}

C12

C8

C2

V_{IN_VIN3}

V_{OUT_LDO4}

L1

LDO4

VIN4

NC

GNDB

C10

LXB

VINB

C1

VIN3

FB1

C9

LDO3

AGND

LDO2

LDO1

HWEN

DGND

SDA

V_{OUT_LDO3}

BST

VOUT

VSYS

REF

BSTEN

INTRB

V_{OUT_BOOST}

V_{OUT_LDO2}

C7

LX

BST

GND

BST

LX

BST

C4

VIN12

SCL

C6

L2

V_{OUT_LDO1}

C5

C13

C3

C11

V_{IN_VIN12}

V_{IN_B}

Figure 13. PCB Layout Guide

©

is a registered trademark of Richtek Technology Corporation.

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64

DS5112-03 August 2019

RT5112

Outline Dimension

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

0.500

0.170

0.240

2.260

Max

0.600

0.230

0.300

2.340

Min

0.020

0.007

0.009

0.089

Max

0.024

0.009

0.012

0.092

A

A1

b

D

D1

E

1.600

0.063

2.160

2.240

0.085

0.088

E1

e

1.600

0.400

0.063

0.016

25B WL-CSP 2.2x2.3 Package (BSC)

©

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DS5112-03 August 2019

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65

RT5112

Footprint Information

Footprint Dimension (mm)

Number of

Package

Type

Tolerance

±0.025

e

A

B

NSMD

SMD

0.240

0.270

0.340

0.240

WL-CSP2.2x2.3-25(BSC)

25

0.400

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

www.richtek.com

66

DS5112-03 August 2019


型号：	RT5112
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总66页 (文件大小：891K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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