RT9246 [RICHTEK]
Multi-Phase PWM Controller for CPU Core Power Supply; 多相PWM控制器，用于CPU核心供电
| 型号： | RT9246 |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Multi-Phase PWM Controller for CPU Core Power Supply |
| 文件： | 总17页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9246
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
z Multi-Phase Power Conversion with Automatic
The RT9246 is a multi-phase buck DC/DC controller
integrated with all control functions for GHz CPU VRM.
The RT9246 controls 2 or 3 buck switching stages
operating in interleaved phase set automatically. The multi-
phase architecture provides high output current while
maintaining low power dissipation on power devices and
low stress on input and output capacitors. The high
equivalent operating frequency also reduces the
component dimension and the output voltage ripple in load
transient.
Phase Selection
z K8 DAC Output with Active Droop Compensation
for Fast Load Transient
z Smooth VCORE Transition at VID Jump
z Power Stage Thermal Balance by RDS(ON) Current
Sense
z Hiccup Mode Over-Current Protection
z Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and
Soft-Start
RT9246 controls both voltage and current loops to achieve
good regulation, response & power stage thermal balance.
Precise current loop using RDS(ON) as sense component
builds precise load line for strict VRM DC & transient
specification and also ensures thermal balance of different
power stages. The settings of current sense, droop tuning,
VCORE initial offset and over current protection are
independent to compensation circuit of voltage loop. The
feature greatly facilitates the flexibility of CPU power supply
design and tuning.
z High Ripple Frequency Times Channel Number
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z AMD® AthlonTM 64 and OpteronTM Processors Voltage
Regulator
z Low Output Voltage, High CurrentDC-DC Converters
z Voltage Regulator Modules
Pin Configurations
TheDAC output of RT9246 supports K8 CPU by 5-bit VID
input, precise initial value & smooth VCORE transient at
VID jump. The IC monitors the VCORE voltage for PGOOD
and over-voltage protection. Soft-start, over-current
protection and programmable under-voltage lockout are
also provided to assure the safety of microprocessor and
power system.
(TOP VIEW)
VID4
VID3
VID2
VID1
VID0
SS2
VCC
28
27
26
25
24
23
22
21
PWM1
PWM2
PWM3
2
3
4
5
6
7
8
ISN1
ISP1
ISP2
ISP3
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
Ordering Information
9
20
19
18
17
16
15
ISN23
GND
RT9246
10
11
12
13
14
ADJ
Package Type
C : TSSOP-28
VDIF
VSEN
IMAX
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
TSSOP-28
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9246-06 March 2007
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RT9246
Typical Application Circuit
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DS9246-06 March 2007
RT9246
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5)
RT (Pin 13)
Switching frequency setting. Connect this pin toGNDwith
a resistor to set the frequency.
DAC voltage identification inputs for K8. These pins are
internally pulled to 2.4V if left open.
VOSS (Pin 14)
SS2 (Pin 6)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
DAC O/P ramping speed control for K8. Connect this pin
to GND with a capacitor to set the rising/falling time at
VID jump.
IMAX (Pin 15)
Over-Current protection set.
SGND (Pin 7)
VSEN (Pin 16)
VCORE differential sense negative input.
VCORE differential sense positive input.
FB (Pin 8)
VDIF (Pin 17)
Inverting input of the internal error amplifier.
VCORE differential sense output.
COMP (Pin 9)
ADJ (Pin 18)
Output of the error amplifier and input of the PWM
comparator.
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
PGOOD (Pin 10)
GND (Pin 19)
Power good open-drain output.
IC ground.
DVD (Pin 11)
ISN23 (Pin 20)
Programmable power UVLO detection or converter enable
input.
RDS(ON) current sense inputs from converter 2nd & 3rd phase
channel sense components'GNDnode.
SS (Pin 12)
ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
RDS(ON) current sense inputs for individual converter
channels. Tie this pin to the component's sense node.
Frequency vs. RRT
450
ISN1 (Pin 24)
400
350
300
250
200
150
100
50
RDS(ON) current sense inputs from converter 1st channel
sense component'sGNDnode.
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 2 channels, connect PWM3 high.
VCC (Pin 28)
0
IC power supply. Connect this pin to a 5V supply.
0
10
20
30
40
50
60
70
RRT (k Ω)
DS9246-06 March 2007
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RT9246
Function Block Diagram
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RT9246
Table 1. Output Voltage Program
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Nominal Output Voltage DACOUT
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.200
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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RT9246
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND-0.3V to VCC+0.3V
z Power Dissipation, PD @ TA = 25°C
TSSOP-28 ------------------------------------------------------------------------------------------------------ 1W
z Package Thermal Resistance (Note 4)
TSSOP-28, θJA -------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10%
z Ambient Temperature Range--------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range--------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
VCC Supply Current
Symbol
Test Conditions
PWM 1,2,3 Open
VCC Rising
Min
Typ
Max Units
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
ICC
--
12
--
mA
VCCRTH
VCCHYS
VDVDTP
VDVDHYS
4.0
0.2
0.79
--
4.2
0.5
4.5
--
V
V
Input High
Input Low
Enable
0.85
250
0.91
--
V
VDVD Threshold
mV
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
fOSC
170
50
--
200
--
230
400
--
kHz
kHz
V
RRT = 12kΩ
RRT = 12kΩ
fOSC_ADJ
ΔVOSC
VRV
1.9
1.0
66
Ramp Valley
--
--
V
Maximum On-Time of Each Channel
RT Pin Voltage
62
0.55
75
%
VRT
0.60
0.65
V
RRT = 12kΩ
VDAC ≥ 1V
Reference and DAC
--
--
--
--
+1
+10
0.8
--
%
mV
V
−1
−10
--
DACOUT Voltage Accuracy
ΔVDAC
VDAC < 1V
DAC (VID0-VID4) Input Low
DAC (VID0-VID4) Input High
ΔVILDAC
ΔVIHDAC
2
V
To be continued
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RT9246
Parameter
DAC (VID0-VID4) Pull-up Voltage
DAC (VID0-VID4) Bias Current
VOSS Pin Voltage
Symbol
Test Conditions
Min
2.2
Typ
2.4
60
Max Units
2.6
80
V
μA
V
IBIAS_DAC
40
VVOSS
0.95
1.0
1.05
R
VOSS = 100kΩ
Error Amplifier
DC Gain
--
--
--
85
10
3
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
Differential Sense Amplifier
Input Impedance
ZIMP
GBW
SR
--
--
--
16
10
3
--
--
--
kΩ
Gain-Bandwidth Product
Slew Rate
MHz
V/μs
Current Sense GM Amplifier
ISP 1,2,3 Full Scale Source Current
ISP 1,2,3 Current for OCP
Protection
IISPFSS
IISPOCP
60
90
--
--
--
--
μA
μA
IMAX Voltage
VIMAX
ISS
RIMAX = 10k
VSS = 1V
0.55
--
0.60
13
0.65
--
V
μA
%
SS Current
Over-Voltage Trip (VSEN/DACOUT)
Power Good
--
140
--
ΔOVT
Lower Threshold (VSEN/DACOUT)
Output Low Voltage
VSEN Rising
IPGOOD = 4mA
--
--
92
--
--
%
V
VPGOOD−
VPGOODL
0.2
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
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RT9246
Typical Operating Characteristics
Current Balance
Current Balance
ILOAD = 30A
ILOAD = 60A
(5V/Div)
PWM2
PWM1
PWM3
(5V/Div)
PWM2
PWM1
PWM3
IPWM2
IPWM2
IPWM1
IPWM3
IPWM1
IPWM3
(5A/Div)
(2.5A/Div)
Time (1us/Div)
Time (1us/Div)
Current Balance @ Soft Start
Current Balance @ Soft Start
ILOAD = 0A
ILOAD = 30A
(5V/Div)
SS
(5V/Div)
SS
(0.5A/Div)
(5A/Div)
IPWM1
IPWM3
IPWM1
IPWM2
IPWM2
IPWM3
Time (10ms/Div)
Time (10ms/Div)
DVD Disable
DVD Enable
(200mV/Div)
DVD
VCORE
SS
(200mV/Div)
VCORE
(200mV/Div)
DVD
(1V/Div)
(200mV/Div)
PGOOD
(500mV/Div)
PGOOD
SS
(500mV/Div)
(1V/Div)
Time (4ms/Div)
Time (2ms/Div)
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RT9246
OCP Steady State
OCP Power Up
ILOAD = 30A to short
ILOAD = short
(5V/Div)
(5V/Div)
(5V/Div)
SS
SS
(5V/Div)
PWM
PWM
(10A/Div)
(5A/Div)
IPWM3
IPWM3
Time (40ms/Div)
Time (20ms/Div)
Soft Start
Transient Response
VCORE (200mV/Div)
PWM1
PWM2
PWM3
SS (1V/Div)
VCORE
PGOOD (1V/Div)
Time (10ms/Div)
Time (200us/Div)
VID On Fly Falling
VID On Fly Rising
CSS2 = 0F
CSS2 = 0F
(5V/Div)
(5V/Div)
VID
VCORE
SS
VID
VCORE
SS
(500mV/Div)
(500mV/Div)
(500mV/Div)
(500mV/Div)
Time (200ns/Div)
Time (200ns/Div)
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RT9246
VID On Fly Falling
VID On Fly Rising
CSS2 = 1nF
CSS2 = 1nF
(5V/Div)
(5V/Div)
VID
VCORE
SS
VID
(500mV/Div)
(500mV/Div)
(500mV/Div)
(500mV/Div)
VCORE
SS
Time (200ns/Div)
Time (200ns/Div)
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DS9246-06 March 2007
RT9246
Application Information
Fault Detection
RT9246 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9246 and its companion MOSFET driver provides high
quality CPU power and all protection functions to meet
the requirement of modern VRM.
The chip detects VCORE for over voltage and power good
detection. The “hiccup mode” operation of over-current
protection is adopted to reduce the short circuit current.
The inrush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
Voltage Control
Phase Setting and Converter Start Up
RT9246 senses the CPU VCORE by an precise instrumental
amplifier to minimize the voltage drop on PCB trace at
heavy load. VSEN& SGNDare the differential inputs. VDIF
is the output node of the differential voltage & the input for
PGOOD & OVP sense. The internal high accuracy VID
DAC provides the reference voltage for K8 compliance.
Control loop consists of error amplifier, multi-phase pulse
width modulator, driver and power components. Like
conventional voltage mode PWM controller, the output
voltage is locked at the VREF of error amplifier and the
error signal is used as the control signal VC of pulse width
modulator. The PWM signals of different channels are
generated by comparison of EA output and split-phase
sawtooth wave. Power stage transforms VIN to output by
PWM signal on-time ratio.
RT9246 interfaces with companion MOSFET drivers (like
RT9600, RT9602 or RT9603 series) for correct converter
initialization. The tri-state PWM output (high, low and high
impedance) pins sense the interface voltage at IC POR
period (both VCC and DVD trip). The channel is enabled if
the pin voltage is 1.2V less than VCC. Please tie the PWM
output to VCC and the current sense pins to GND or left
floating if the channel is unused. For 2-Channel application,
connect PWM3 high.
Current Sensing Setting
RT9246 senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal circuit (see
Figure 1). Be careful to chooseGNDsense input, ISN, of
theGM amplifier for effective channel current balance.
Current Balance
RT9246 senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal balance circuit.
The current balance circuit sums and averages the current
signals then produces the balancing signals injected to
pulse width modulator. If the current of some power
channel is greater than average, the balancing signal
reduces the output pulse width to keep the balance.
IX1
Current
I
Balance
X
X
X
IBP
R
R
<
SP1
ISP1
ISN1
Sample
&
Hold
-
2I
I
Droop Tune
R
<
<
GM
IL
S
+
IBN
SN1
Over-Current
Detection
IX2
Current
Balance
I
2I
I
X
X
X
IBP
R
<
SP2
ISP2
Sample
&
Hold
-
Droop Tune
<
<
GM
+
R
Load Droop
S
I
L
IBN
Over-Current
Detection
R
SN23
ISN23
The sensed power channel current signals regulate the
reference of DAC to form a output voltage droop
proportional to the load current. The droop or so-called
“active voltage positioning” can reduce the output voltage
ripple at load transient and the LC filter size.
IBN
Channel 2 & 3
GND return
Current
Balance
I
2I
I
+
X
X
X
<
GM
ISP3
Sample
&
Hold
-
Droop Tune
<
<
R
IBP
SP3
R
I
S
L
Over-Current
Detection
IX3
Figure 1. Current Sense Circuit
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RT9246
IL ×RS
RSP
IX =
The sensing circuit gets
by local feedback.
Protection and SS Function
RSP = RSN for channel 1 & RSP = 2RSN for channel 2 & 3 (at
3 phase operation) to cancel the voltage drop caused by
GM amplifier input bias current. IX is sampled and held
just before low side MOSFET turns off (See Figure 2).
Therefore,
For OVP, the RT9246 detects the VCORE by VDIF pin voltage
of the differential amplifier output. Eliminate the delay due
to compensation network (compared to sensing FB
voltage) for fast and accurate detection. The trip point of
OVP is 140% of normal output level. The PWM outputs
are pulled low to turn on the low side MOSFET and turn
off the high side MOSFET of the synchronous rectifier at
OVP. The OVP latch can only be reset by VCC or DVD
restart power on reset sequence. The PGOOD detection
trip point of VCORE is 92% lower than the normal level.
The PGOOD open drain output pulls low when VCORE is
lower than the trip point. For VID jumping issue, only power
fail conditions (VCC & DVD are lower than trip point or
OVP) reset the output low.
I
L (S/H) × R
V
O
T
OFF
I
X (S/H)
=
S , IL (S/H) = IL (AVG)
−
×
,
R
SP
L
2
V
IN − V
O
⎡
⎤
T
OFF
=
× 5uS for fosc = 200kHz
⎢
⎥
V
IN
⎣
⎦
⎡
⎤
⎥
⎥
⎥
V
IN − V
O
⎡
⎤
V
O
−
× 5uS
⎢
⎢
⎣
⎥
⎦
R
S
V
IN
⎢
I
X (S/H) = IL(AVG)
−
×
2L
R
SP
⎢
⎢
⎣
⎥
⎦
Falling Slope = Vo/L
Inductor Current
IL
Soft-start circuit generates a ramp voltage by charging
external capacitor with 13μA current after IC POR acts.
The PWM pulse width and VCORE are clamped by the
rising ramp to reduce the inrush current and protect the
power devices.
IL(AVG)
IL(S/H)
PWM Signal & High Side MOSFET Gate Signal
Over-current protection trip point is set by the resistor
RIMAX connected to IMAX pin. OCP is triggered if one
channel
0.6V
⎛
⎞
Low Side MOSFET Gate Signal
S/H current signal I >
×1.4. Controller forces
⎜
⎟
X
R
IMAX
⎝
⎠
Figure 2. Inductor Current and PWM Signal
PWM output latched at high impedance to turn off both
high and low side MOSFETs in the power stage and initial
the hiccup mode protection. The SS pin voltage is pulled
low with a 13μAcurrent after it is less than 90% VCC. The
converter restarts after SS pin voltage < 0.2V. Three times
of OCP disable the converter and only release the latch
by POR acts (see Figure 4).
DAC Offset Voltage & Droop Tuning
The DAC offset voltage is set by compensation network
1V
Rf1
⎛
⎞
×
⎜
⎟
& VOSS pin external resistors by
.
RVOSS
4
⎝
⎠
The S/H current signals from power channels are injected
to ADJ pin to create droop voltage.VADJ = RADJ× 2IX
∑
CCOoUuNntT==22 CCOoUuNntT==33
Count =1
The DAC output voltage decreases by VADJ to form the
VCORE load droop (see Figure 3).
S.S
V
DAC
+
VCORE
2I
V
X1
X2
X3
ADJ
-
0V
COMP
+
-
2I
2I
∑
Overload
Applied
EA
Current
Source
>
IVOSS
1
4
ILOAD
0A
1V
IVOSS =
RVOSS
+
-
FB
R
ADJ
V
OSS
R
R
ADJ
VOSS
F1
T3,T4
T0,T1
T2
TIME
V
CORE
Figure 4.
Figure 3. DAC Offset Voltage & Droop Tune Circuit
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DS9246-06 March 2007
RT9246
3-Phase Converter and Components Function Grouping
12V
VCC
BST
DRVH
SW
RT9603
IN
DRVL
PGND
SGND
VSEN
VDIF
PWM1
VID
12V
ISP1
ISN1
PGOOD
VCC
BST
DRVH
RT9246
Compensation
& Offset
V
SW
CORE
COMP
FB
RT9603
PWM2
IN
DRVL
PGND
ADJ
Droop Setting
ISP2
ISN23
12V
DVD
12V
Driver Power
UVLO
VOSS
SS, SS2
ISP3
VCC
BST
DAC Offset
Voltage Setting
SS2
DRVH
PWM3
SW
IMAX
GND
RT9603
IN
DRVL
PGND
OCP Setting
Current Sense
Components
Design Procedure Suggestion
VRM Load Line Setting
Voltage Loop Setting
a. Droop amplitude (ADJ pin resistor).
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. No load offset (additional resistor in compensation
network).
b. Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
c. DAC offset voltage setting (VOSS pin & compen sation
network resistor).
c. Kelvin sense for VCORE
.
Power Sequence & SS
Current Loop Setting
DVD pin external resistor and SS pin capacitor.
a. GM amplifier S/H current (current sense component
RDS(ON), ISPx & ISNx pin external resistor value, keep
ISPx current < 60μA at full load condition for better
load line linearity).
PCB Layout
a. Kelvin sense for current sense GM amplifier input.
b. Refer to layout guide for other item.
b. Over-current protection trip point (IMAX pin resistor,
keep ISPx current < 90μA at OCP condition for
precision issue).
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RT9246
Design Example
Given:
Asymptotic Bode Plot of PWM Loop Gain
100
80
60
40
20
0
Apply for three phase converter
VIN = 12V
Uncompensated EA Gain
VCORE = 1.5V
I
LOAD (max) = 60A
VDROOP = 120mV at full load
Compensated EA Gain
PWM Loop Gain
-20
-40
-60
OCP trip point set at 30A for each channel (S/H)
RDS(ON) = 6mΩ of low side MOSFET at 27°C
L = 2μH
Modulator Gain
10
100
1K
10K
100K 1M 10M
COUT = 9,000μF with 2mΩ ESR.
Frequency (Hz)
Figure 6.
1. Compensation Setting
2. Droop & DAC Offset Setting
a. Modulator Gain, Pole and Zero :
For each channel the load current is 60A / 3 = 20A
From the following formula :
and the ripple current, ΔIL, is given as :
V
IN
12V
Modulator Gain =
=
= 4.2 (12.46dB)
3
2
V
RAMP
1.5V
2uH
1.5V
12V
⎛
⎞
⎟
1.9V×
5us x
x 1−
= 3.28A
⎜
where VRAMP : ramp amplitude of sawtooth wave
1
⎝
⎠
ΔIL
The load current, I , at S/H is
.
20A −
= 18.36A
L
LC Filter Pole =
= 1.2kHz and
2
2π x LC
Using the following formula to select the appropriate
IX (MAX) for the S/H of GM amplifier :
1
ESR Zero =
= 8.8kHz
R
DS(ON) × 18.36A
2π xESR x COUT
I
X (MAX)
=
R
SP
b. EA Compensation Network :
The suggested IX is in the order of 40 to 50μA, select
RSP = RSN = 2.4kΩ, then IX (MAX) will be 45.9μA.
Select R1 = 2.4kΩ, R2 = 24kΩ, C1 = 6.6nF,
C2 = 33pF and use the type 2 compensation
scheme shown in Figure 5.
VDROOP = 120mV = 45.9μA × 2 × 3 (phase no.) × RADJ
therefore RADJ will be 435Ω.
,
C1
C3
R2
C2
R3
The R
of MOSFET varies with temperature rise.
DS(ON)
When the low side MOSFET working at 70°C and
5000ppm/°C temperature coefficient of RDS(ON), the
RDS(ON) at 70°C is given as :
6mΩ × {1+ (70°C − 27°C) × 5000ppm/°C} = 7.3mΩ.
RADJ at 70°C is given as :
R1
VDIF
>
COMP
FB
R3,C3 are used in type
-
+
3 compensation scheme
(left NC in type 2)
DACOUT
RADJ_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 358Ω
3. Over-Current Protection Setting
Figure 5.
OCP trip point set at 30A for each channel,
From the following formulas :
1
R
DS(ON) ×30A
0.6V
1
I
X
=
=1.4 ×
F
Z
=
, F
P
=
, RIMAX = 11.2kΩ
RSP
RIMAX
C
1
1
×C
+ C
2
2
2π x R
2
x C
1
⎛
⎞
⎟
2π x R x
2
⎜
⎝
R
R
2
C
⎠
Take the temperature rise into account, the RIMAX at
70°C will be :
RIMAX_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 9.2kΩ
Middle Band Gain =
1
By calculation, the FZ = 1kHz, F = 200kHz and
P
Middle Band Gain is 10 (i.e 20dB).
The asymptotic bode plot of EA compensation and
PWM loop gain is shown as Figure 6.
4. Soft-Start Capacitor Selection
CSS = 0.1μF is the suitable value for most application.
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14
DS9246-06 March 2007
RT9246
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to ISP1,2,3 and ISN1,ISN23 should be located not more than 0.5 inch from the IC and away
from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signalGND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
L1
SW1
VOUT
VIN
RIN
COUT
RL
CIN
V
L2
SW2
Figure 7. Power Stage Ripple Current Path
DS9246-06 March 2007
www.richtek.com
15
RT9246
Next to IC
+12V
CBP
+12V or +5V
PWM
+5VIN
VCC
CBP
IMAX
CBOOT
VCC
IN
BST
VOSS
Next to IC
COMP
DRVH
LO1
COUT
VCORE
CC
RC
SW
RT9246
CIN
RT9603
DRVL
Kelvin
Sense
Locate next
to FB Pin
RSP
FB
PGND
ISPx
ISNx
RFB
RSN
Locate near MOSFETs
VSEN
ADJ
GND
For Thermal Couple
Figure 8. Layout Consideration
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16
DS9246-06 March 2007
RT9246
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
0.850
0.050
0.800
0.178
9.601
1.200
0.152
1.050
0.305
9.804
0.033
0.002
0.031
0.007
0.378
0.047
0.006
0.041
0.012
0.386
D
e
0.650
0.026
E
6.300
4.293
0.450
6.500
4.496
0.762
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9246-06 March 2007
www.richtek.com
17
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